[PATCH 00/21] Various fixes and extensions to Exynos4 clock driver

[PATCH 00/21] Various fixes and extensions to Exynos4 clock driver

[Tomasz Figa]

This series is a collection of various fixes and extensions to Exynos4
clock driver, which improve coverage of clocks present on Exynos4 SoCs
and fix problems discovered during our internal work and testing.

Andrzej Hajda (1):
  clk: samsung: exynos4: Add missing CMU_TOP and ISP clocks

Lukasz Majewski (1):
  clk: samsung: exynos4: Export clocks used by exynos cpufreq drivers

Sylwester Nawrocki (2):
  clk: samsung: exynos4: Correct sclk_mfc clock definition
  clk: samsung: exynos4: Add camera related clock definitions

Tomasz Figa (17):
  clk: samsung: exynos4: Use mout_mpll_user_* on Exynos4x12
  clk: samsung: exynos4: Add missing mout_mipihsi clock
  clk: samsung: exynos4: Add missing sclk_audio0 clock
  clk: samsung: exynos4: Export sclk_pcm0
  clk: samsung: exynos4: Move dac and mixer to Exynos4210-specific
    clocks
  clk: samsung: pll: Remove unimplemented ops
  clk: samsung: exynos4: Export mout_core clock of Exynos4210
  clk: samsung: exynos4: Add G3D clocks
  clk: samsung: exynos4: Add missing mout_sata on Exynos4210
  clk: samsung: exynos4: Define {E,V}PLL registers
  clk: samsung: exynos4: Use SRC_MASK_PERIL{0,1} definitions
  clk: samsung: exynos4: Remove SoC-specific registers from save list
  clk: samsung: exynos4: Add E4210 prefix to LCD1 clock registers
  clk: samsung: exynos4: Add E4210 prefix to GATE_IP_PERIR register
  clk: samsung: exynos4: Remove E4X12 prefix from SRC_DMC register
  clk: samsung: exynos4: Add missing registers to suspend save list
  clk: samsung: exynos4: Add support for SoC-specific register save list

 .../devicetree/bindings/clock/exynos4-clock.txt    |  61 ++-
 drivers/clk/samsung/clk-exynos4.c                  | 491 +++++++++++++++------
 drivers/clk/samsung/clk-exynos5250.c               |   3 +-
 drivers/clk/samsung/clk-exynos5440.c               |   2 +-
 drivers/clk/samsung/clk-pll.c                      |  80 ----
 drivers/clk/samsung/clk.c                          |   9 +-
 drivers/clk/samsung/clk.h                          |   3 +-
 7 files changed, 437 insertions(+), 212 deletions(-)

-- 
1.8.1.5

[PATCH 01/21] clk: samsung: exynos4: Correct sclk_mfc clock definition

[Tomasz Figa]

From: Sylwester Nawrocki <s.nawrocki@samsung.com>

This clock must be exported to allow lookup using device tree.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 Documentation/devicetree/bindings/clock/exynos4-clock.txt | 2 +-
 drivers/clk/samsung/clk-exynos4.c                         | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
index e874add..8b58232 100644
--- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -91,7 +91,7 @@ Exynos4 SoC and this is specified where applicable.
   sclk_i2s1           167
   sclk_i2s2           168
   sclk_mipihsi        169     Exynos4412
-
+  sclk_mfc            170
 
 	      [Peripheral Clock Gates]
 
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index e1bb81a..44a99b5 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -122,7 +122,7 @@ enum exynos4_clks {
 	sclk_sata, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_uart4,
 	sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
 	sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1,
-	sclk_i2s2, sclk_mipihsi,
+	sclk_i2s2, sclk_mipihsi, sclk_mfc,
 
 	/* gate clocks */
 	fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
@@ -355,7 +355,7 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = {
 	DIV(none, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
 	DIV(none, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
 	DIV(none, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
-	DIV(none, "div_mfc", "mout_mfc", DIV_MFC, 0, 4),
+	DIV(sclk_mfc, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4),
 	DIV(none, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
 	DIV(none, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
 	DIV(none, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
-- 
1.8.1.5

[PATCH 02/21] clk: samsung: exynos4: Use mout_mpll_user_* on Exynos4x12

[Tomasz Figa]

Many clock muxes of Exynos 4x12 uses mout_mpll_user_* clocks instead of
sclk_mpll as one of their parents.

This patch moves such clocks from common array into SoC-specific arrays
and adjusts their parent lists respectively.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 .../devicetree/bindings/clock/exynos4-clock.txt    |   2 +
 drivers/clk/samsung/clk-exynos4.c                  | 172 +++++++++++++--------
 2 files changed, 113 insertions(+), 61 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
index 8b58232..d029605 100644
--- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -42,6 +42,8 @@ Exynos4 SoC and this is specified where applicable.
   aclk100             14
   aclk160             15
   aclk133             16
+  mout_mpll_user_t    17      Exynos4x12
+  mout_mpll_user_c    18      Exynos4x12
 
 
             [Clock Gate for Special Clocks]
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 44a99b5..8edd64c 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -112,7 +112,7 @@ enum exynos4_clks {
 	/* core clocks */
 	xxti, xusbxti, fin_pll, fout_apll, fout_mpll, fout_epll, fout_vpll,
 	sclk_apll, sclk_mpll, sclk_epll, sclk_vpll, arm_clk, aclk200, aclk100,
-	aclk160, aclk133,
+	aclk160, aclk133, mout_mpll_user_t, mout_mpll_user_c, /* 18 */
 
 	/* gate for special clocks (sclk) */
 	sclk_fimc0 = 128, sclk_fimc1, sclk_fimc2, sclk_fimc3, sclk_cam0,
@@ -218,35 +218,53 @@ PNAME(mout_apll_p)	= { "fin_pll", "fout_apll", };
 PNAME(mout_mpll_p)	= { "fin_pll", "fout_mpll", };
 PNAME(mout_epll_p)	= { "fin_pll", "fout_epll", };
 PNAME(mout_vpllsrc_p)	= { "fin_pll", "sclk_hdmi24m", };
-PNAME(sclk_vpll_p4210)	= { "mout_vpllsrc", "fout_vpll", };
 PNAME(mout_vpll_p)	= { "fin_pll", "fout_vpll", };
-PNAME(mout_core_p)	= { "mout_apll", "sclk_mpll", };
-PNAME(sclk_ampll_p)	= { "sclk_mpll", "sclk_apll", };
-PNAME(mout_mpll_user_p)	= { "fin_pll", "sclk_mpll", };
-PNAME(aclk_p4412)	= { "mout_mpll_user", "sclk_apll", };
 PNAME(sclk_evpll_p)	= { "sclk_epll", "sclk_vpll", };
 PNAME(mout_mfc_p)	= { "mout_mfc0", "mout_mfc1", };
 PNAME(mout_g3d_p)	= { "mout_g3d0", "mout_g3d1", };
 PNAME(mout_g2d_p)	= { "mout_g2d0", "mout_g2d1", };
-PNAME(mout_mixer_p4210)	= { "sclk_dac", "sclk_hdmi", };
-PNAME(mout_dac_p4210)	= { "sclk_vpll", "sclk_hdmiphy", };
 PNAME(mout_hdmi_p)	= { "sclk_pixel", "sclk_hdmiphy", };
 PNAME(mout_jpeg_p)	= { "mout_jpeg0", "mout_jpeg1", };
-PNAME(group1_p)		= { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
-				"none",	"sclk_hdmiphy", "sclk_mpll",
-				"sclk_epll", "sclk_vpll", };
-PNAME(mout_audio0_p)	= { "cdclk0", "none", "sclk_hdmi24m", "sclk_usbphy0",
-				"xxti", "xusbxti", "sclk_mpll", "sclk_epll",
-				"sclk_vpll" };
-PNAME(mout_audio1_p)	= { "cdclk1", "none", "sclk_hdmi24m", "sclk_usbphy0",
-				"xxti", "xusbxti", "sclk_mpll", "sclk_epll",
-				"sclk_vpll", };
-PNAME(mout_audio2_p)	= { "cdclk2", "none", "sclk_hdmi24m", "sclk_usbphy0",
-				"xxti", "xusbxti", "sclk_mpll", "sclk_epll",
-				"sclk_vpll", };
 PNAME(mout_spdif_p)	= { "sclk_audio0", "sclk_audio1", "sclk_audio2",
 				"spdif_extclk", };
 
+/* Exynos 4210-specific parent groups */
+PNAME(sclk_vpll_p4210)	= { "mout_vpllsrc", "fout_vpll", };
+PNAME(mout_core_p4210)	= { "mout_apll", "sclk_mpll", };
+PNAME(sclk_ampll_p4210)	= { "sclk_mpll", "sclk_apll", };
+PNAME(group1_p4210)	= { "xxti", "xusbxti", "sclk_hdmi24m",
+				"sclk_usbphy0", "none",	"sclk_hdmiphy",
+				"sclk_mpll", "sclk_epll", "sclk_vpll", };
+PNAME(mout_audio0_p4210) = { "cdclk0", "none", "sclk_hdmi24m",
+				"sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
+				"sclk_epll", "sclk_vpll" };
+PNAME(mout_audio1_p4210) = { "cdclk1", "none", "sclk_hdmi24m",
+				"sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
+				"sclk_epll", "sclk_vpll", };
+PNAME(mout_audio2_p4210) = { "cdclk2", "none", "sclk_hdmi24m",
+				"sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
+				"sclk_epll", "sclk_vpll", };
+PNAME(mout_mixer_p4210)	= { "sclk_dac", "sclk_hdmi", };
+PNAME(mout_dac_p4210)	= { "sclk_vpll", "sclk_hdmiphy", };
+
+/* Exynos 4x12-specific parent groups */
+PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", };
+PNAME(mout_core_p4x12)	= { "mout_apll", "mout_mpll_user_c", };
+PNAME(sclk_ampll_p4x12)	= { "mout_mpll_user_t", "sclk_apll", };
+PNAME(group1_p4x12)	= { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
+				"none",	"sclk_hdmiphy", "mout_mpll_user_t",
+				"sclk_epll", "sclk_vpll", };
+PNAME(mout_audio0_p4x12) = { "cdclk0", "none", "sclk_hdmi24m",
+				"sclk_usbphy0", "xxti", "xusbxti",
+				"mout_mpll_user_t", "sclk_epll", "sclk_vpll" };
+PNAME(mout_audio1_p4x12) = { "cdclk1", "none", "sclk_hdmi24m",
+				"sclk_usbphy0", "xxti", "xusbxti",
+				"mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
+PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m",
+				"sclk_usbphy0", "xxti", "xusbxti",
+				"mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
+PNAME(aclk_p4412)	= { "mout_mpll_user_t", "sclk_apll", };
+
 /* fixed rate clocks generated outside the soc */
 struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
 	FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0),
@@ -267,80 +285,112 @@ struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
 /* list of mux clocks supported in all exynos4 soc's */
 struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
 	MUX(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
-	MUX(none, "mout_core", mout_core_p, SRC_CPU, 16, 1),
-	MUX(none, "mout_fimc0", group1_p, SRC_CAM, 0, 4),
-	MUX(none, "mout_fimc1", group1_p, SRC_CAM, 4, 4),
-	MUX(none, "mout_fimc2", group1_p, SRC_CAM, 8, 4),
-	MUX(none, "mout_fimc3", group1_p, SRC_CAM, 12, 4),
-	MUX(none, "mout_cam0", group1_p, SRC_CAM, 16, 4),
-	MUX(none, "mout_cam1", group1_p, SRC_CAM, 20, 4),
-	MUX(none, "mout_csis0", group1_p, SRC_CAM, 24, 4),
-	MUX(none, "mout_csis1", group1_p, SRC_CAM, 28, 4),
 	MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
-	MUX(none, "mout_mfc0", sclk_ampll_p, SRC_MFC, 0, 1),
 	MUX(none, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
 	MUX(none, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
-	MUX(none, "mout_g3d0", sclk_ampll_p, SRC_G3D, 0, 1),
 	MUX(none, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1),
 	MUX(none, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
-	MUX(none, "mout_fimd0", group1_p, SRC_LCD0, 0, 4),
-	MUX(none, "mout_mipi0", group1_p, SRC_LCD0, 12, 4),
-	MUX(none, "mout_audio0", mout_audio0_p, SRC_MAUDIO, 0, 4),
-	MUX(none, "mout_mmc0", group1_p, SRC_FSYS, 0, 4),
-	MUX(none, "mout_mmc1", group1_p, SRC_FSYS, 4, 4),
-	MUX(none, "mout_mmc2", group1_p, SRC_FSYS, 8, 4),
-	MUX(none, "mout_mmc3", group1_p, SRC_FSYS, 12, 4),
-	MUX(none, "mout_mmc4", group1_p, SRC_FSYS, 16, 4),
-	MUX(none, "mout_uart0", group1_p, SRC_PERIL0, 0, 4),
-	MUX(none, "mout_uart1", group1_p, SRC_PERIL0, 4, 4),
-	MUX(none, "mout_uart2", group1_p, SRC_PERIL0, 8, 4),
-	MUX(none, "mout_uart3", group1_p, SRC_PERIL0, 12, 4),
-	MUX(none, "mout_uart4", group1_p, SRC_PERIL0, 16, 4),
-	MUX(none, "mout_audio1", mout_audio1_p, SRC_PERIL1, 0, 4),
-	MUX(none, "mout_audio2", mout_audio2_p, SRC_PERIL1, 4, 4),
 	MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
-	MUX(none, "mout_spi0", group1_p, SRC_PERIL1, 16, 4),
-	MUX(none, "mout_spi1", group1_p, SRC_PERIL1, 20, 4),
-	MUX(none, "mout_spi2", group1_p, SRC_PERIL1, 24, 4),
 	MUX_A(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1, "sclk_epll"),
 };
 
 /* list of mux clocks supported in exynos4210 soc */
 struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
-	MUX(none, "mout_aclk200", sclk_ampll_p, SRC_TOP0, 12, 1),
-	MUX(none, "mout_aclk100", sclk_ampll_p, SRC_TOP0, 16, 1),
-	MUX(none, "mout_aclk160", sclk_ampll_p, SRC_TOP0, 20, 1),
-	MUX(none, "mout_aclk133", sclk_ampll_p, SRC_TOP0, 24, 1),
+	MUX(none, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
+	MUX(none, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
+	MUX(none, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
+	MUX(none, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1),
 	MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
 	MUX(none, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1),
 	MUX(none, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1),
-	MUX(none, "mout_g2d0", sclk_ampll_p, E4210_SRC_IMAGE, 0, 1),
+	MUX(none, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1),
 	MUX(none, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1),
 	MUX(none, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1),
-	MUX(none, "mout_fimd1", group1_p, SRC_LCD1, 0, 4),
-	MUX(none, "mout_mipi1", group1_p, SRC_LCD1, 12, 4),
+	MUX(none, "mout_fimd1", group1_p4210, SRC_LCD1, 0, 4),
+	MUX(none, "mout_mipi1", group1_p4210, SRC_LCD1, 12, 4),
 	MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "sclk_mpll"),
+	MUX(none, "mout_core", mout_core_p4210, SRC_CPU, 16, 1),
 	MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210,
 			SRC_TOP0, 8, 1, "sclk_vpll"),
+	MUX(none, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
+	MUX(none, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4),
+	MUX(none, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4),
+	MUX(none, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4),
+	MUX(none, "mout_cam0", group1_p4210, SRC_CAM, 16, 4),
+	MUX(none, "mout_cam1", group1_p4210, SRC_CAM, 20, 4),
+	MUX(none, "mout_csis0", group1_p4210, SRC_CAM, 24, 4),
+	MUX(none, "mout_csis1", group1_p4210, SRC_CAM, 28, 4),
+	MUX(none, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1),
+	MUX(none, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1),
+	MUX(none, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4),
+	MUX(none, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4),
+	MUX(none, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4),
+	MUX(none, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4),
+	MUX(none, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4),
+	MUX(none, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4),
+	MUX(none, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4),
+	MUX(none, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4),
+	MUX(none, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4),
+	MUX(none, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4),
+	MUX(none, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4),
+	MUX(none, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4),
+	MUX(none, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4),
+	MUX(none, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4),
+	MUX(none, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4),
+	MUX(none, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4),
+	MUX(none, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4),
+	MUX(none, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4),
 };
 
 /* list of mux clocks supported in exynos4x12 soc */
 struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
-	MUX(none, "mout_mpll_user", mout_mpll_user_p, SRC_LEFTBUS, 4, 1),
+	MUX(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12,
+			SRC_CPU, 24, 1),
+	MUX(mout_mpll_user_t, "mout_mpll_user_t", mout_mpll_user_p4x12,
+			SRC_TOP1, 12, 1),
 	MUX(none, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1),
 	MUX(none, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1),
 	MUX(none, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1),
 	MUX(none, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1),
-	MUX(none, "mout_mdnie0", group1_p, SRC_LCD0, 4, 4),
-	MUX(none, "mout_mdnie_pwm0", group1_p, SRC_LCD0, 8, 4),
-	MUX(none, "mout_sata", sclk_ampll_p, SRC_FSYS, 24, 1),
-	MUX(none, "mout_jpeg0", sclk_ampll_p, E4X12_SRC_CAM1, 0, 1),
+	MUX(none, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4),
+	MUX(none, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4),
+	MUX(none, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1),
+	MUX(none, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1),
 	MUX(none, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1),
 	MUX(none, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
 	MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p,
 			E4X12_SRC_DMC, 12, 1, "sclk_mpll"),
 	MUX_A(sclk_vpll, "sclk_vpll", mout_vpll_p,
 			SRC_TOP0, 8, 1, "sclk_vpll"),
+	MUX(none, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
+	MUX(none, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
+	MUX(none, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
+	MUX(none, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4),
+	MUX(none, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4),
+	MUX(none, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4),
+	MUX(none, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4),
+	MUX(none, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4),
+	MUX(none, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4),
+	MUX(none, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1),
+	MUX(none, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1),
+	MUX(none, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4),
+	MUX(none, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4),
+	MUX(none, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4),
+	MUX(none, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4),
+	MUX(none, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4),
+	MUX(none, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4),
+	MUX(none, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4),
+	MUX(none, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4),
+	MUX(none, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4),
+	MUX(none, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4),
+	MUX(none, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4),
+	MUX(none, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4),
+	MUX(none, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4),
+	MUX(none, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4),
+	MUX(none, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4),
+	MUX(none, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4),
+	MUX(none, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4),
+	MUX(none, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4),
 };
 
 /* list of divider clocks supported in all exynos4 soc's */
-- 
1.8.1.5

[PATCH 03/21] clk: samsung: exynos4: Add missing mout_mipihsi clock

[Tomasz Figa]

This patch adds missing output of mux MIPIHSI which is needed for
div_mipihsi clock.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 drivers/clk/samsung/clk-exynos4.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 8edd64c..42c098d 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -381,6 +381,7 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
 	MUX(none, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4),
 	MUX(none, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4),
 	MUX(none, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4),
+	MUX(none, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1),
 	MUX(none, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4),
 	MUX(none, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4),
 	MUX(none, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4),
-- 
1.8.1.5

[PATCH 04/21] clk: samsung: exynos4: Add missing sclk_audio0 clock

[Tomasz Figa]

This clock is a parent of mout_spdif and sclk_pcm0.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 drivers/clk/samsung/clk-exynos4.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 42c098d..0e89d97 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -508,6 +508,8 @@ struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
 			CLK_SET_RATE_PARENT, 0),
 	GATE(sclk_mipi0, "sclk_mipi0", "div_mipi_pre0",
 			SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0),
+	GATE(sclk_audio0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0,
+			CLK_SET_RATE_PARENT, 0),
 	GATE(sclk_audio1, "sclk_audio1", "div_audio1", 0xc354, 0,
 			CLK_SET_RATE_PARENT, 0),
 	GATE_D(vp, "s5p-mixer", "vp", "aclk160", GATE_IP_TV, 0, 0, 0),
-- 
1.8.1.5

[PATCH 05/21] clk: samsung: exynos4: Export sclk_pcm0

[Tomasz Figa]

This clock is used by PCM interface 0.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 Documentation/devicetree/bindings/clock/exynos4-clock.txt | 1 +
 drivers/clk/samsung/clk-exynos4.c                         | 4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
index d029605..ac7cec4 100644
--- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -94,6 +94,7 @@ Exynos4 SoC and this is specified where applicable.
   sclk_i2s2           168
   sclk_mipihsi        169     Exynos4412
   sclk_mfc            170
+  sclk_pcm0           171
 
 	      [Peripheral Clock Gates]
 
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 0e89d97..96f2e74 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -122,7 +122,7 @@ enum exynos4_clks {
 	sclk_sata, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_uart4,
 	sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
 	sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1,
-	sclk_i2s2, sclk_mipihsi, sclk_mfc,
+	sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0,
 
 	/* gate clocks */
 	fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
@@ -411,7 +411,7 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = {
 	DIV(none, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
 	DIV(none, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
 	DIV(none, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
-	DIV(none, "div_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8),
+	DIV(sclk_pcm0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8),
 	DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
 	DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
 	DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
-- 
1.8.1.5

[PATCH 06/21] clk: samsung: exynos4: Move dac and mixer to Exynos4210-specific clocks

[Tomasz Figa]

The sclk_dac and sclk_mixer clocks are not present on Exynos4x12.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 drivers/clk/samsung/clk-exynos4.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 96f2e74..c1e6451 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -483,8 +483,6 @@ struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
 	 * of the clocks can be removed.
 	 */
 	GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
-	GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
-	GATE(sclk_dac, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
 	GATE(sclk_spdif, "sclk_spdif", "mout_spdif", 0xc354, 8, 0, 0),
 	GATE(jpeg, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0),
 	GATE(mie0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0),
@@ -681,6 +679,8 @@ struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
 			SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0),
 	GATE(sclk_sata, "sclk_sata", "div_sata",
 			SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
+	GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
+	GATE(sclk_dac, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
 	GATE_A(tsadc, "tsadc", "aclk100", GATE_IP_PERIL, 15, 0, 0, "adc"),
 	GATE_A(mct, "mct", "aclk100", GATE_IP_PERIR, 13, 0, 0, "mct"),
 	GATE_A(wdt, "watchdog", "aclk100", GATE_IP_PERIR, 14, 0, 0, "watchdog"),
-- 
1.8.1.5

[PATCH 07/21] clk: samsung: exynos4: Export clocks used by exynos cpufreq drivers

[Tomasz Figa]

From: Lukasz Majewski <l.majewski@samsung.com>

This patch exports clocks used by Exynos cpufreq drivers to allow lookup
using device tree. (Support to cpufreq drivers will be added in further
patches.)

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 Documentation/devicetree/bindings/clock/exynos4-clock.txt | 2 ++
 drivers/clk/samsung/clk-exynos4.c                         | 8 +++++---
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
index ac7cec4..51c572a 100644
--- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -44,6 +44,8 @@ Exynos4 SoC and this is specified where applicable.
   aclk133             16
   mout_mpll_user_t    17      Exynos4x12
   mout_mpll_user_c    18      Exynos4x12
+  mout_core           19
+  mout_apll           20
 
 
             [Clock Gate for Special Clocks]
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index c1e6451..5592a78 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -112,7 +112,8 @@ enum exynos4_clks {
 	/* core clocks */
 	xxti, xusbxti, fin_pll, fout_apll, fout_mpll, fout_epll, fout_vpll,
 	sclk_apll, sclk_mpll, sclk_epll, sclk_vpll, arm_clk, aclk200, aclk100,
-	aclk160, aclk133, mout_mpll_user_t, mout_mpll_user_c, /* 18 */
+	aclk160, aclk133, mout_mpll_user_t, mout_mpll_user_c, mout_core,
+	mout_apll, /* 20 */
 
 	/* gate for special clocks (sclk) */
 	sclk_fimc0 = 128, sclk_fimc1, sclk_fimc2, sclk_fimc3, sclk_cam0,
@@ -284,7 +285,8 @@ struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
 
 /* list of mux clocks supported in all exynos4 soc's */
 struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
-	MUX(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
+	MUX_F(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+			CLK_SET_RATE_PARENT, 0),
 	MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
 	MUX(none, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
 	MUX(none, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
@@ -362,7 +364,7 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
 			E4X12_SRC_DMC, 12, 1, "sclk_mpll"),
 	MUX_A(sclk_vpll, "sclk_vpll", mout_vpll_p,
 			SRC_TOP0, 8, 1, "sclk_vpll"),
-	MUX(none, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
+	MUX(mout_core, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
 	MUX(none, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
 	MUX(none, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
 	MUX(none, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4),
-- 
1.8.1.5

[PATCH 08/21] clk: samsung: pll: Remove unimplemented ops

[Tomasz Figa]

Unimplemented clock operations should be simply omitted instead of returning
error values.

This patch removes unimplemented PLL operations to fix problems caused
by returning error code in round_rate callback.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 drivers/clk/samsung/clk-pll.c | 80 -------------------------------------------
 1 file changed, 80 deletions(-)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 4b24511..89135f6 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -49,24 +49,8 @@ static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
 	return (unsigned long)fvco;
 }
 
-/* todo: implement pl35xx clock round rate operation */
-static long samsung_pll35xx_round_rate(struct clk_hw *hw,
-				unsigned long drate, unsigned long *prate)
-{
-	return -ENOTSUPP;
-}
-
-/* todo: implement pl35xx clock set rate */
-static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
-				unsigned long prate)
-{
-	return -ENOTSUPP;
-}
-
 static const struct clk_ops samsung_pll35xx_clk_ops = {
 	.recalc_rate = samsung_pll35xx_recalc_rate,
-	.round_rate = samsung_pll35xx_round_rate,
-	.set_rate = samsung_pll35xx_set_rate,
 };
 
 struct clk * __init samsung_clk_register_pll35xx(const char *name,
@@ -144,24 +128,8 @@ static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
 	return (unsigned long)fvco;
 }
 
-/* todo: implement pl36xx clock round rate operation */
-static long samsung_pll36xx_round_rate(struct clk_hw *hw,
-				unsigned long drate, unsigned long *prate)
-{
-	return -ENOTSUPP;
-}
-
-/* todo: implement pl36xx clock set rate */
-static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate,
-				unsigned long prate)
-{
-	return -ENOTSUPP;
-}
-
 static const struct clk_ops samsung_pll36xx_clk_ops = {
 	.recalc_rate = samsung_pll36xx_recalc_rate,
-	.round_rate = samsung_pll36xx_round_rate,
-	.set_rate = samsung_pll36xx_set_rate,
 };
 
 struct clk * __init samsung_clk_register_pll36xx(const char *name,
@@ -239,24 +207,8 @@ static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw,
 	return (unsigned long)fvco;
 }
 
-/* todo: implement pl45xx clock round rate operation */
-static long samsung_pll45xx_round_rate(struct clk_hw *hw,
-				unsigned long drate, unsigned long *prate)
-{
-	return -ENOTSUPP;
-}
-
-/* todo: implement pl45xx clock set rate */
-static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate,
-				unsigned long prate)
-{
-	return -ENOTSUPP;
-}
-
 static const struct clk_ops samsung_pll45xx_clk_ops = {
 	.recalc_rate = samsung_pll45xx_recalc_rate,
-	.round_rate = samsung_pll45xx_round_rate,
-	.set_rate = samsung_pll45xx_set_rate,
 };
 
 struct clk * __init samsung_clk_register_pll45xx(const char *name,
@@ -342,24 +294,8 @@ static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
 	return (unsigned long)fvco;
 }
 
-/* todo: implement pl46xx clock round rate operation */
-static long samsung_pll46xx_round_rate(struct clk_hw *hw,
-				unsigned long drate, unsigned long *prate)
-{
-	return -ENOTSUPP;
-}
-
-/* todo: implement pl46xx clock set rate */
-static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
-				unsigned long prate)
-{
-	return -ENOTSUPP;
-}
-
 static const struct clk_ops samsung_pll46xx_clk_ops = {
 	.recalc_rate = samsung_pll46xx_recalc_rate,
-	.round_rate = samsung_pll46xx_round_rate,
-	.set_rate = samsung_pll46xx_set_rate,
 };
 
 struct clk * __init samsung_clk_register_pll46xx(const char *name,
@@ -441,24 +377,8 @@ static unsigned long samsung_pll2550x_recalc_rate(struct clk_hw *hw,
 	return (unsigned long)fvco;
 }
 
-/* todo: implement pl2550x clock round rate operation */
-static long samsung_pll2550x_round_rate(struct clk_hw *hw,
-				unsigned long drate, unsigned long *prate)
-{
-	return -ENOTSUPP;
-}
-
-/* todo: implement pl2550x clock set rate */
-static int samsung_pll2550x_set_rate(struct clk_hw *hw, unsigned long drate,
-				unsigned long prate)
-{
-	return -ENOTSUPP;
-}
-
 static const struct clk_ops samsung_pll2550x_clk_ops = {
 	.recalc_rate = samsung_pll2550x_recalc_rate,
-	.round_rate = samsung_pll2550x_round_rate,
-	.set_rate = samsung_pll2550x_set_rate,
 };
 
 struct clk * __init samsung_clk_register_pll2550x(const char *name,
-- 
1.8.1.5

[PATCH 09/21] clk: samsung: exynos4: Export mout_core clock of Exynos4210

[Tomasz Figa]

This patch enables clock lookup registration for mout_core clock used in
Exynos4210 cpufreq driver.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 drivers/clk/samsung/clk-exynos4.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 5592a78..8c4cffb 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -311,7 +311,7 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
 	MUX(none, "mout_fimd1", group1_p4210, SRC_LCD1, 0, 4),
 	MUX(none, "mout_mipi1", group1_p4210, SRC_LCD1, 12, 4),
 	MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "sclk_mpll"),
-	MUX(none, "mout_core", mout_core_p4210, SRC_CPU, 16, 1),
+	MUX_A(mout_core, "mout_core", mout_core_p4210, SRC_CPU, 16, 1, "mout_core"),
 	MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210,
 			SRC_TOP0, 8, 1, "sclk_vpll"),
 	MUX(none, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
-- 
1.8.1.5

[PATCH 10/21] clk: samsung: exynos4: Add camera related clock definitions

[Tomasz Figa]

From: Sylwester Nawrocki <s.nawrocki@samsung.com>

This patch adds several gate and mux clocks related to camera and ISP
blocks.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 .../devicetree/bindings/clock/exynos4-clock.txt    | 20 +++++++++
 drivers/clk/samsung/clk-exynos4.c                  | 50 ++++++++++++++--------
 2 files changed, 53 insertions(+), 17 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
index 51c572a..657b889 100644
--- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -198,6 +198,26 @@ Exynos4 SoC and this is specified where applicable.
   audss               348
   mipi_hsi            349     Exynos4210
   mdma2               350     Exynos4210
+  pixelasyncm0        351
+  pixelasyncm1        352
+  fimc_lite0          353     Exynos4x12
+  fimc_lite1          354     Exynos4x12
+  ppmuispx            355     Exynos4x12
+  ppmuispmx           356     Exynos4x12
+
+			[Mux Clocks]
+
+	Clock		ID	SoC (if specific)
+	-----------------------------------------------
+
+	mout_fimc0	384
+	mout_fimc1	385
+	mout_fimc2	386
+	mout_fimc3	387
+	mout_cam0	388
+	mout_cam1	389
+	mout_csis0	390
+	mout_csis1	391
 
 Example 1: An example of a clock controller node is listed below.
 
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 8c4cffb..728ffaf 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -87,6 +87,7 @@
 #define E4210_MPLL_CON0		0x14108
 #define SRC_CPU			0x14200
 #define DIV_CPU0		0x14500
+#define E4X12_GATE_ISP0		0x18800
 
 /* the exynos4 soc type */
 enum exynos4_soc {
@@ -136,7 +137,12 @@ enum exynos4_clks {
 	uart4, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc,
 	spi0, spi1, spi2, i2s1, i2s2, pcm0, i2s0, pcm1, pcm2, pwm, slimbus,
 	spdif, ac97, modemif, chipid, sysreg, hdmi_cec, mct, wdt, rtc, keyif,
-	audss, mipi_hsi, mdma2,
+	audss, mipi_hsi, mdma2, pixelasyncm0, pixelasyncm1, fimc_lite0,
+	fimc_lite1, ppmuispx, ppmuispmx,
+
+	/* mux clocks */
+	mout_fimc0 = 384, mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0,
+	mout_cam1, mout_csis0, mout_csis1,
 
 	nr_clks,
 };
@@ -314,14 +320,14 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
 	MUX_A(mout_core, "mout_core", mout_core_p4210, SRC_CPU, 16, 1, "mout_core"),
 	MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210,
 			SRC_TOP0, 8, 1, "sclk_vpll"),
-	MUX(none, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
-	MUX(none, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4),
-	MUX(none, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4),
-	MUX(none, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4),
-	MUX(none, "mout_cam0", group1_p4210, SRC_CAM, 16, 4),
-	MUX(none, "mout_cam1", group1_p4210, SRC_CAM, 20, 4),
-	MUX(none, "mout_csis0", group1_p4210, SRC_CAM, 24, 4),
-	MUX(none, "mout_csis1", group1_p4210, SRC_CAM, 28, 4),
+	MUX(mout_fimc0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
+	MUX(mout_fimc1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4),
+	MUX(mout_fimc2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4),
+	MUX(mout_fimc3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4),
+	MUX(mout_cam0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4),
+	MUX(mout_cam1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4),
+	MUX(mout_csis0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4),
+	MUX(mout_csis1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4),
 	MUX(none, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1),
 	MUX(none, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1),
 	MUX(none, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4),
@@ -365,14 +371,14 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
 	MUX_A(sclk_vpll, "sclk_vpll", mout_vpll_p,
 			SRC_TOP0, 8, 1, "sclk_vpll"),
 	MUX(mout_core, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
-	MUX(none, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
-	MUX(none, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
-	MUX(none, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4),
-	MUX(none, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4),
-	MUX(none, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4),
-	MUX(none, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4),
-	MUX(none, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4),
-	MUX(none, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4),
+	MUX(mout_fimc0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
+	MUX(mout_fimc1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
+	MUX(mout_fimc2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4),
+	MUX(mout_fimc3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4),
+	MUX(mout_cam0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4),
+	MUX(mout_cam1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4),
+	MUX(mout_csis0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4),
+	MUX(mout_csis1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4),
 	MUX(none, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1),
 	MUX(none, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1),
 	MUX(none, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4),
@@ -587,6 +593,8 @@ struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
 			GATE_IP_CAM, 10, 0, 0, "sysmmu"),
 	GATE_DA(smmu_jpeg, "exynos-sysmmu.3", "smmu_jpeg", "aclk160",
 			GATE_IP_CAM, 11, 0, 0, "sysmmu"),
+	GATE(pixelasyncm0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0),
+	GATE(pixelasyncm1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0),
 	GATE_DA(smmu_tv, "exynos-sysmmu.2", "smmu_tv", "aclk160",
 			GATE_IP_TV, 4, 0, 0, "sysmmu"),
 	GATE_DA(mfc, "s5p-mfc", "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0, "mfc"),
@@ -721,6 +729,14 @@ struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
 			E4X12_GATE_IP_MAUDIO, 2, 0, 0, "pcm"),
 	GATE_DA(i2s0, "samsung-i2s.0", "i2s0", "aclk100",
 			E4X12_GATE_IP_MAUDIO, 3, 0, 0, "iis"),
+	GATE(fimc_lite0, "lite0", "aclk200", E4X12_GATE_ISP0, 3,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(fimc_lite1, "lite1", "aclk200", E4X12_GATE_ISP0, 4,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(ppmuispmx, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(ppmuispx, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
+			CLK_IGNORE_UNUSED, 0),
 };
 
 #ifdef CONFIG_OF
-- 
1.8.1.5

[PATCH 11/21] clk: samsung: exynos4: Add G3D clocks

[Tomasz Figa]

This patch adds clocks needed for G3D block present on Exynos 4 SoCs.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 .../devicetree/bindings/clock/exynos4-clock.txt    |  4 ++++
 drivers/clk/samsung/clk-exynos4.c                  | 22 ++++++++++++++--------
 2 files changed, 18 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
index 657b889..1863032 100644
--- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -97,6 +97,7 @@ Exynos4 SoC and this is specified where applicable.
   sclk_mipihsi        169     Exynos4412
   sclk_mfc            170
   sclk_pcm0           171
+  sclk_g3d            172
 
 	      [Peripheral Clock Gates]
 
@@ -218,6 +219,9 @@ Exynos4 SoC and this is specified where applicable.
 	mout_cam1	389
 	mout_csis0	390
 	mout_csis1	391
+	mout_g3d0	392
+	mout_g3d1	393
+	mout_g3d	394
 
 Example 1: An example of a clock controller node is listed below.
 
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 728ffaf..694b890 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -124,7 +124,7 @@ enum exynos4_clks {
 	sclk_sata, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_uart4,
 	sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
 	sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1,
-	sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0,
+	sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d,
 
 	/* gate clocks */
 	fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
@@ -142,7 +142,7 @@ enum exynos4_clks {
 
 	/* mux clocks */
 	mout_fimc0 = 384, mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0,
-	mout_cam1, mout_csis0, mout_csis1,
+	mout_cam1, mout_csis0, mout_csis1, mout_g3d0, mout_g3d1, mout_g3d,
 
 	nr_clks,
 };
@@ -296,8 +296,10 @@ struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
 	MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
 	MUX(none, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
 	MUX(none, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
-	MUX(none, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1),
-	MUX(none, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
+	MUX_F(mout_g3d1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1,
+			CLK_SET_RATE_PARENT, 0),
+	MUX_F(mout_g3d, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1,
+			CLK_SET_RATE_PARENT, 0),
 	MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
 	MUX_A(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1, "sclk_epll"),
 };
@@ -329,7 +331,8 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
 	MUX(mout_csis0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4),
 	MUX(mout_csis1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4),
 	MUX(none, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1),
-	MUX(none, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1),
+	MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1,
+			CLK_SET_RATE_PARENT, 0),
 	MUX(none, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4),
 	MUX(none, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4),
 	MUX(none, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4),
@@ -380,7 +383,8 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
 	MUX(mout_csis0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4),
 	MUX(mout_csis1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4),
 	MUX(none, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1),
-	MUX(none, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1),
+	MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1,
+			CLK_SET_RATE_PARENT, 0),
 	MUX(none, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4),
 	MUX(none, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4),
 	MUX(none, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4),
@@ -415,7 +419,8 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = {
 	DIV(none, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
 	DIV(none, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
 	DIV(sclk_mfc, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4),
-	DIV(none, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
+	DIV_F(none, "div_g3d", "mout_g3d", DIV_G3D, 0, 4,
+			CLK_SET_RATE_PARENT, 0),
 	DIV(none, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
 	DIV(none, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
 	DIV(none, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
@@ -501,7 +506,8 @@ struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
 	GATE(smmu_fimd1, "smmu_fimd1", "aclk160", GATE_IP_LCD1, 4, 0, 0),
 	GATE(tsi, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0),
 	GATE(sromc, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
-	GATE(g3d, "g3d", "aclk200", GATE_IP_G3D, 0, 0, 0),
+	GATE(sclk_g3d, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0,
+			CLK_SET_RATE_PARENT, 0),
 	GATE(usb_device, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
 	GATE(onenand, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
 	GATE(nfcon, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0),
-- 
1.8.1.5

[PATCH 12/21] clk: samsung: exynos4: Add missing CMU_TOP and ISP clocks

[Tomasz Figa]

From: Andrzej Hajda <a.hajda@samsung.com>

The patch adds missing clocks to TOP and ISP clock domains.
It also adds clock gates for ISP sub-blocks.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 .../devicetree/bindings/clock/exynos4-clock.txt    |  30 ++++++
 drivers/clk/samsung/clk-exynos4.c                  | 110 ++++++++++++++++++++-
 2 files changed, 137 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
index 1863032..662007e 100644
--- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -98,6 +98,10 @@ Exynos4 SoC and this is specified where applicable.
   sclk_mfc            170
   sclk_pcm0           171
   sclk_g3d            172
+  sclk_pwm_isp        173     Exynos4x12
+  sclk_spi0_isp       174     Exynos4x12
+  sclk_spi1_isp       175     Exynos4x12
+  sclk_uart_isp       176     Exynos4x12
 
 	      [Peripheral Clock Gates]
 
@@ -205,6 +209,32 @@ Exynos4 SoC and this is specified where applicable.
   fimc_lite1          354     Exynos4x12
   ppmuispx            355     Exynos4x12
   ppmuispmx           356     Exynos4x12
+  fimc_isp            357     Exynos4x12
+  fimc_drc            358     Exynos4x12
+  fimc_fd             359     Exynos4x12
+  mcuisp              360     Exynos4x12
+  gicisp              361     Exynos4x12
+  smmu_isp            362     Exynos4x12
+  smmu_drc            363     Exynos4x12
+  smmu_fd             364     Exynos4x12
+  smmu_lite0          365     Exynos4x12
+  smmu_lite1          366     Exynos4x12
+  mcuctl_isp          367     Exynos4x12
+  mpwm_isp            368     Exynos4x12
+  i2c0_isp            369     Exynos4x12
+  i2c1_isp            370     Exynos4x12
+  mtcadc_isp          371     Exynos4x12
+  pwm_isp             372     Exynos4x12
+  wdt_isp             373     Exynos4x12
+  uart_isp            374     Exynos4x12
+  asyncaxim           375     Exynos4x12
+  smmu_ispcx          376     Exynos4x12
+  spi0_isp            377     Exynos4x12
+  spi1_isp            378     Exynos4x12
+  pwm_isp_sclk        379     Exynos4x12
+  spi0_isp_sclk       380     Exynos4x12
+  spi1_isp_sclk       381     Exynos4x12
+  uart_isp_sclk       382     Exynos4x12
 
 			[Mux Clocks]
 
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 694b890..0586421 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -34,6 +34,7 @@
 #define E4210_SRC_IMAGE		0xc230
 #define SRC_LCD0		0xc234
 #define SRC_LCD1		0xc238
+#define E4X12_SRC_ISP		0xc238
 #define SRC_MAUDIO		0xc23c
 #define SRC_FSYS		0xc240
 #define SRC_PERIL0		0xc250
@@ -43,6 +44,7 @@
 #define SRC_MASK_TV		0xc324
 #define SRC_MASK_LCD0		0xc334
 #define SRC_MASK_LCD1		0xc338
+#define E4X12_SRC_MASK_ISP	0xc338
 #define SRC_MASK_MAUDIO		0xc33c
 #define SRC_MASK_FSYS		0xc340
 #define SRC_MASK_PERIL0		0xc350
@@ -76,6 +78,7 @@
 #define E4210_GATE_IP_IMAGE	0xc930
 #define GATE_IP_LCD0		0xc934
 #define GATE_IP_LCD1		0xc938
+#define E4X12_GATE_IP_ISP	0xc938
 #define E4X12_GATE_IP_MAUDIO	0xc93c
 #define GATE_IP_FSYS		0xc940
 #define GATE_IP_GPS		0xc94c
@@ -87,7 +90,10 @@
 #define E4210_MPLL_CON0		0x14108
 #define SRC_CPU			0x14200
 #define DIV_CPU0		0x14500
+#define E4X12_DIV_ISP0		0x18300
+#define E4X12_DIV_ISP1		0x18304
 #define E4X12_GATE_ISP0		0x18800
+#define E4X12_GATE_ISP1		0x18804
 
 /* the exynos4 soc type */
 enum exynos4_soc {
@@ -124,7 +130,8 @@ enum exynos4_clks {
 	sclk_sata, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_uart4,
 	sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
 	sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1,
-	sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d,
+	sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d, sclk_pwm_isp,
+	sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp,
 
 	/* gate clocks */
 	fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
@@ -138,7 +145,11 @@ enum exynos4_clks {
 	spi0, spi1, spi2, i2s1, i2s2, pcm0, i2s0, pcm1, pcm2, pwm, slimbus,
 	spdif, ac97, modemif, chipid, sysreg, hdmi_cec, mct, wdt, rtc, keyif,
 	audss, mipi_hsi, mdma2, pixelasyncm0, pixelasyncm1, fimc_lite0,
-	fimc_lite1, ppmuispx, ppmuispmx,
+	fimc_lite1, ppmuispx, ppmuispmx, fimc_isp, fimc_drc, fimc_fd, mcuisp,
+	gicisp, smmu_isp, smmu_drc, smmu_fd, smmu_lite0, smmu_lite1, mcuctl_isp,
+	mpwm_isp, i2c0_isp, i2c1_isp, mtcadc_isp, pwm_isp, wdt_isp, uart_isp,
+	asyncaxim, smmu_ispcx, spi0_isp, spi1_isp, pwm_isp_sclk, spi0_isp_sclk,
+	spi1_isp_sclk, uart_isp_sclk,
 
 	/* mux clocks */
 	mout_fimc0 = 384, mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0,
@@ -234,6 +245,8 @@ PNAME(mout_hdmi_p)	= { "sclk_pixel", "sclk_hdmiphy", };
 PNAME(mout_jpeg_p)	= { "mout_jpeg0", "mout_jpeg1", };
 PNAME(mout_spdif_p)	= { "sclk_audio0", "sclk_audio1", "sclk_audio2",
 				"spdif_extclk", };
+PNAME(mout_onenand_p)  = {"aclk133", "aclk160", };
+PNAME(mout_onenand1_p) = {"mout_onenand", "sclk_vpll", };
 
 /* Exynos 4210-specific parent groups */
 PNAME(sclk_vpll_p4210)	= { "mout_vpllsrc", "fout_vpll", };
@@ -271,6 +284,9 @@ PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m",
 				"sclk_usbphy0", "xxti", "xusbxti",
 				"mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
 PNAME(aclk_p4412)	= { "mout_mpll_user_t", "sclk_apll", };
+PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", };
+PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
+PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
 
 /* fixed rate clocks generated outside the soc */
 struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
@@ -301,7 +317,9 @@ struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
 	MUX_F(mout_g3d, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1,
 			CLK_SET_RATE_PARENT, 0),
 	MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
+	MUX(none, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
 	MUX_A(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1, "sclk_epll"),
+	MUX(none, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
 };
 
 /* list of mux clocks supported in exynos4210 soc */
@@ -357,8 +375,15 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
 struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
 	MUX(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12,
 			SRC_CPU, 24, 1),
+	MUX(none, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
+	MUX(none, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1),
 	MUX(mout_mpll_user_t, "mout_mpll_user_t", mout_mpll_user_p4x12,
 			SRC_TOP1, 12, 1),
+	MUX(none, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12,
+			SRC_TOP1, 16, 1),
+	MUX(aclk200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1),
+	MUX(none, "aclk400_mcuisp", mout_user_aclk400_mcuisp_p4x12,
+			SRC_TOP1, 24, 1),
 	MUX(none, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1),
 	MUX(none, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1),
 	MUX(none, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1),
@@ -404,6 +429,10 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
 	MUX(none, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4),
 	MUX(none, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4),
 	MUX(none, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4),
+	MUX(none, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4),
+	MUX(none, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
+	MUX(none, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
+	MUX(none, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
 };
 
 /* list of divider clocks supported in all exynos4 soc's */
@@ -430,10 +459,10 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = {
 	DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
 	DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
 	DIV(sclk_pixel, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4),
-	DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
 	DIV(aclk100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4),
 	DIV(aclk160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3),
 	DIV(aclk133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3),
+	DIV(none, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3),
 	DIV(sclk_slimbus, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4),
 	DIV(sclk_pcm1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8),
 	DIV(sclk_pcm2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8),
@@ -471,6 +500,7 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = {
 
 /* list of divider clocks supported in exynos4210 soc */
 struct samsung_div_clock exynos4210_div_clks[] __initdata = {
+	DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
 	DIV(none, "div_g2d", "mout_g2d", DIV_IMAGE, 0, 4),
 	DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
 	DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
@@ -486,6 +516,20 @@ struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
 	DIV(none, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
 	DIV(none, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4),
 	DIV(none, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4),
+	DIV(none, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3),
+	DIV(none, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3),
+	DIV(none, "div_aclk400_mcuisp", "mout_aclk400_mcuisp", DIV_TOP, 24, 3),
+	DIV(none, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4),
+	DIV(none, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4),
+	DIV(none, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8),
+	DIV(none, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4),
+	DIV(none, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8),
+	DIV(none, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4),
+	DIV(none, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3),
+	DIV(none, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3),
+	DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
+	DIV(none, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 4, 3),
+	DIV(none, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3),
 };
 
 /* list of gate clocks supported in all exynos4 soc's */
@@ -729,20 +773,80 @@ struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
 	GATE_A(rtc, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, 0, 0, "rtc"),
 	GATE_A(keyif, "keyif", "aclk100",
 			E4X12_GATE_IP_PERIR, 16, 0, 0, "keypad"),
+	GATE(sclk_pwm_isp, "sclk_pwm_isp", "div_pwm_isp",
+			E4X12_SRC_MASK_ISP, 0, CLK_SET_RATE_PARENT, 0),
+	GATE(sclk_spi0_isp, "sclk_spi0_isp", "div_spi0_isp_pre",
+			E4X12_SRC_MASK_ISP, 4, CLK_SET_RATE_PARENT, 0),
+	GATE(sclk_spi1_isp, "sclk_spi1_isp", "div_spi1_isp_pre",
+			E4X12_SRC_MASK_ISP, 8, CLK_SET_RATE_PARENT, 0),
+	GATE(sclk_uart_isp, "sclk_uart_isp", "div_uart_isp",
+			E4X12_SRC_MASK_ISP, 12, CLK_SET_RATE_PARENT, 0),
+	GATE(pwm_isp_sclk, "pwm_isp_sclk", "sclk_pwm_isp",
+			E4X12_GATE_IP_ISP, 0, 0, 0),
+	GATE(spi0_isp_sclk, "spi0_isp_sclk", "sclk_spi0_isp",
+			E4X12_GATE_IP_ISP, 1, 0, 0),
+	GATE(spi1_isp_sclk, "spi1_isp_sclk", "sclk_spi1_isp",
+			E4X12_GATE_IP_ISP, 2, 0, 0),
+	GATE(uart_isp_sclk, "uart_isp_sclk", "sclk_uart_isp",
+			E4X12_GATE_IP_ISP, 3, 0, 0),
 	GATE_A(wdt, "watchdog", "aclk100",
 			E4X12_GATE_IP_PERIR, 14, 0, 0, "watchdog"),
 	GATE_DA(pcm0, "samsung-pcm.0", "pcm0", "aclk100",
 			E4X12_GATE_IP_MAUDIO, 2, 0, 0, "pcm"),
 	GATE_DA(i2s0, "samsung-i2s.0", "i2s0", "aclk100",
 			E4X12_GATE_IP_MAUDIO, 3, 0, 0, "iis"),
+	GATE(fimc_isp, "isp", "aclk200", E4X12_GATE_ISP0, 0,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(fimc_drc, "drc", "aclk200", E4X12_GATE_ISP0, 1,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(fimc_fd, "fd", "aclk200", E4X12_GATE_ISP0, 2,
+			CLK_IGNORE_UNUSED, 0),
 	GATE(fimc_lite0, "lite0", "aclk200", E4X12_GATE_ISP0, 3,
 			CLK_IGNORE_UNUSED, 0),
 	GATE(fimc_lite1, "lite1", "aclk200", E4X12_GATE_ISP0, 4,
 			CLK_IGNORE_UNUSED, 0),
+	GATE(mcuisp, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(gicisp, "gicisp", "aclk200", E4X12_GATE_ISP0, 7,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(smmu_isp, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(smmu_drc, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(smmu_fd, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(smmu_lite0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(smmu_lite1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12,
+			CLK_IGNORE_UNUSED, 0),
 	GATE(ppmuispmx, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20,
 			CLK_IGNORE_UNUSED, 0),
 	GATE(ppmuispx, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
 			CLK_IGNORE_UNUSED, 0),
+	GATE(mcuctl_isp, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(mpwm_isp, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(i2c0_isp, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(i2c1_isp, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(mtcadc_isp, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(pwm_isp, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(wdt_isp, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(uart_isp, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(asyncaxim, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(smmu_ispcx, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(spi0_isp, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
+			CLK_IGNORE_UNUSED, 0),
 };
 
 #ifdef CONFIG_OF
-- 
1.8.1.5

[PATCH 13/21] clk: samsung: exynos4: Add missing mout_sata on Exynos4210

[Tomasz Figa]

This patch adds missing mout_sata that is a parent of div_sata clock.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 drivers/clk/samsung/clk-exynos4.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 0586421..959402f 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -359,6 +359,7 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
 	MUX(none, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4),
 	MUX(none, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4),
 	MUX(none, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4),
+	MUX(none, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1),
 	MUX(none, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4),
 	MUX(none, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4),
 	MUX(none, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4),
-- 
1.8.1.5

[PATCH 14/21] clk: samsung: exynos4: Define {E,V}PLL registers

[Tomasz Figa]

This patch adds preprocessor definitions of EPLL and VPLL registers and
replaces all occurences of offsets of related registers with new
definitions.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 drivers/clk/samsung/clk-exynos4.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 959402f..8ce3b25 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -25,6 +25,14 @@
 #define E4X12_GATE_IP_IMAGE	0x4930
 #define GATE_IP_RIGHTBUS	0x8800
 #define E4X12_GATE_IP_PERIR	0x8960
+#define EPLL_LOCK		0xc010
+#define VPLL_LOCK		0xc020
+#define EPLL_CON0		0xc110
+#define EPLL_CON1		0xc114
+#define EPLL_CON2		0xc118
+#define VPLL_CON0		0xc120
+#define VPLL_CON1		0xc124
+#define VPLL_CON2		0xc128
 #define SRC_TOP0		0xc210
 #define SRC_TOP1		0xc214
 #define SRC_CAM			0xc220
@@ -968,18 +976,18 @@ void __init exynos4_clk_init(struct device_node *np)
 		mpll = samsung_clk_register_pll45xx("fout_mpll", "fin_pll",
 					reg_base + E4210_MPLL_CON0, pll_4508);
 		epll = samsung_clk_register_pll46xx("fout_epll", "fin_pll",
-					reg_base + 0xc110, pll_4600);
+					reg_base + EPLL_CON0, pll_4600);
 		vpll = samsung_clk_register_pll46xx("fout_vpll", "mout_vpllsrc",
-					reg_base + 0xc120, pll_4650c);
+					reg_base + VPLL_CON0, pll_4650c);
 	} else {
 		apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
 					reg_base + APLL_CON0);
 		mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
 					reg_base + E4X12_MPLL_CON0);
 		epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
-					reg_base + 0xc110);
+					reg_base + EPLL_CON0);
 		vpll = samsung_clk_register_pll36xx("fout_vpll", "fin_pll",
-					reg_base + 0xc120);
+					reg_base + VPLL_CON0);
 	}
 
 	samsung_clk_add_lookup(apll, fout_apll);
-- 
1.8.1.5

[PATCH 15/21] clk: samsung: exynos4: Use SRC_MASK_PERIL{0,1} definitions

[Tomasz Figa]

There are definitions of SRC_MASK_PERIL0 and SRC_MASK_PERIL1 registers,
but they are not used for clock definitions. This patch modifies related
clock definitions to use defined macros instead of numeric offsets.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 drivers/clk/samsung/clk-exynos4.c | 30 +++++++++++++++++++-----------
 1 file changed, 19 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 8ce3b25..e7c6acd 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -549,7 +549,7 @@ struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
 	 * of the clocks can be removed.
 	 */
 	GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
-	GATE(sclk_spdif, "sclk_spdif", "mout_spdif", 0xc354, 8, 0, 0),
+	GATE(sclk_spdif, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0, 0),
 	GATE(jpeg, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0),
 	GATE(mie0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0),
 	GATE(dsim0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0),
@@ -575,7 +575,7 @@ struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
 			SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0),
 	GATE(sclk_audio0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0,
 			CLK_SET_RATE_PARENT, 0),
-	GATE(sclk_audio1, "sclk_audio1", "div_audio1", 0xc354, 0,
+	GATE(sclk_audio1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0,
 			CLK_SET_RATE_PARENT, 0),
 	GATE_D(vp, "s5p-mixer", "vp", "aclk160", GATE_IP_TV, 0, 0, 0),
 	GATE_D(mixer, "s5p-mixer", "mixer", "aclk160", GATE_IP_TV, 1, 0, 0),
@@ -613,23 +613,31 @@ struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
 	GATE_DA(sclk_mmc4, NULL, "sclk_mmc4", "div_mmc_pre4",
 			SRC_MASK_FSYS, 16, CLK_SET_RATE_PARENT, 0, "ciu"),
 	GATE_DA(sclk_uart0, "exynos4210-uart.0", "uclk0", "div_uart0",
-			0xc350, 0, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"),
+			SRC_MASK_PERIL0, 0, CLK_SET_RATE_PARENT,
+			0, "clk_uart_baud0"),
 	GATE_DA(sclk_uart1, "exynos4210-uart.1", "uclk1", "div_uart1",
-			0xc350, 4, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"),
+			SRC_MASK_PERIL0, 4, CLK_SET_RATE_PARENT,
+			0, "clk_uart_baud0"),
 	GATE_DA(sclk_uart2, "exynos4210-uart.2", "uclk2", "div_uart2",
-			0xc350, 8, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"),
+			SRC_MASK_PERIL0, 8, CLK_SET_RATE_PARENT,
+			0, "clk_uart_baud0"),
 	GATE_DA(sclk_uart3, "exynos4210-uart.3", "uclk3", "div_uart3",
-			0xc350, 12, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"),
+			SRC_MASK_PERIL0, 12, CLK_SET_RATE_PARENT,
+			0, "clk_uart_baud0"),
 	GATE_DA(sclk_uart4, "exynos4210-uart.4", "uclk4", "div_uart4",
-			0xc350, 16, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"),
-	GATE(sclk_audio2, "sclk_audio2", "div_audio2", 0xc354, 4,
+			SRC_MASK_PERIL0, 16, CLK_SET_RATE_PARENT,
+			0, "clk_uart_baud0"),
+	GATE(sclk_audio2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4,
 			CLK_SET_RATE_PARENT, 0),
 	GATE_DA(sclk_spi0, "exynos4210-spi.0", "sclk_spi0", "div_spi_pre0",
-			0xc354, 16, CLK_SET_RATE_PARENT, 0, "spi_busclk0"),
+			SRC_MASK_PERIL1, 16, CLK_SET_RATE_PARENT,
+			0, "spi_busclk0"),
 	GATE_DA(sclk_spi1, "exynos4210-spi.1", "sclk_spi1", "div_spi_pre1",
-			0xc354, 20, CLK_SET_RATE_PARENT, 0, "spi_busclk0"),
+			SRC_MASK_PERIL1, 20, CLK_SET_RATE_PARENT,
+			0, "spi_busclk0"),
 	GATE_DA(sclk_spi2, "exynos4210-spi.2", "sclk_spi2", "div_spi_pre2",
-			0xc354, 24, CLK_SET_RATE_PARENT, 0, "spi_busclk0"),
+			SRC_MASK_PERIL1, 24, CLK_SET_RATE_PARENT,
+			0, "spi_busclk0"),
 	GATE_DA(fimc0, "exynos4-fimc.0", "fimc0", "aclk160",
 			GATE_IP_CAM, 0, 0, 0, "fimc"),
 	GATE_DA(fimc1, "exynos4-fimc.1", "fimc1", "aclk160",
-- 
1.8.1.5

[PATCH 16/21] clk: samsung: exynos4: Remove SoC-specific registers from save list

[Tomasz Figa]

Current clock save list is shared for all Exynos4 SoCs, so it must
contain only registers present in all supported SoCs, because accessing
unavailable registers might have undefined effect.

This patch removes registers specific for particular SoCs from shared
save list, as they should be supported by separate SoC-specific lists.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 drivers/clk/samsung/clk-exynos4.c | 16 ----------------
 1 file changed, 16 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index e7c6acd..aa8e907 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -172,27 +172,21 @@ enum exynos4_clks {
  */
 static __initdata unsigned long exynos4_clk_regs[] = {
 	SRC_LEFTBUS,
-	E4X12_GATE_IP_IMAGE,
 	GATE_IP_RIGHTBUS,
-	E4X12_GATE_IP_PERIR,
 	SRC_TOP0,
 	SRC_TOP1,
 	SRC_CAM,
 	SRC_TV,
 	SRC_MFC,
 	SRC_G3D,
-	E4210_SRC_IMAGE,
 	SRC_LCD0,
-	SRC_LCD1,
 	SRC_MAUDIO,
 	SRC_FSYS,
 	SRC_PERIL0,
 	SRC_PERIL1,
-	E4X12_SRC_CAM1,
 	SRC_MASK_CAM,
 	SRC_MASK_TV,
 	SRC_MASK_LCD0,
-	SRC_MASK_LCD1,
 	SRC_MASK_MAUDIO,
 	SRC_MASK_FSYS,
 	SRC_MASK_PERIL0,
@@ -204,8 +198,6 @@ static __initdata unsigned long exynos4_clk_regs[] = {
 	DIV_G3D,
 	DIV_IMAGE,
 	DIV_LCD0,
-	E4210_DIV_LCD1,
-	E4X12_DIV_ISP,
 	DIV_MAUDIO,
 	DIV_FSYS0,
 	DIV_FSYS1,
@@ -217,24 +209,16 @@ static __initdata unsigned long exynos4_clk_regs[] = {
 	DIV_PERIL3,
 	DIV_PERIL4,
 	DIV_PERIL5,
-	E4X12_DIV_CAM1,
 	GATE_SCLK_CAM,
 	GATE_IP_CAM,
 	GATE_IP_TV,
 	GATE_IP_MFC,
 	GATE_IP_G3D,
-	E4210_GATE_IP_IMAGE,
 	GATE_IP_LCD0,
-	GATE_IP_LCD1,
-	E4X12_GATE_IP_MAUDIO,
 	GATE_IP_FSYS,
 	GATE_IP_GPS,
 	GATE_IP_PERIL,
-	GATE_IP_PERIR,
-	E4X12_MPLL_CON0,
-	E4X12_SRC_DMC,
 	APLL_CON0,
-	E4210_MPLL_CON0,
 	SRC_CPU,
 	DIV_CPU0,
 };
-- 
1.8.1.5

[PATCH 17/21] clk: samsung: exynos4: Add E4210 prefix to LCD1 clock registers

[Tomasz Figa]

This patch adds E4210 prefix to all registers related to LCD1 clock
domain, because they are present only on Exynos4210.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 drivers/clk/samsung/clk-exynos4.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index aa8e907..c84dbc9 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -41,7 +41,7 @@
 #define SRC_G3D			0xc22c
 #define E4210_SRC_IMAGE		0xc230
 #define SRC_LCD0		0xc234
-#define SRC_LCD1		0xc238
+#define E4210_SRC_LCD1		0xc238
 #define E4X12_SRC_ISP		0xc238
 #define SRC_MAUDIO		0xc23c
 #define SRC_FSYS		0xc240
@@ -51,7 +51,7 @@
 #define SRC_MASK_CAM		0xc320
 #define SRC_MASK_TV		0xc324
 #define SRC_MASK_LCD0		0xc334
-#define SRC_MASK_LCD1		0xc338
+#define E4210_SRC_MASK_LCD1	0xc338
 #define E4X12_SRC_MASK_ISP	0xc338
 #define SRC_MASK_MAUDIO		0xc33c
 #define SRC_MASK_FSYS		0xc340
@@ -85,7 +85,7 @@
 #define GATE_IP_G3D		0xc92c
 #define E4210_GATE_IP_IMAGE	0xc930
 #define GATE_IP_LCD0		0xc934
-#define GATE_IP_LCD1		0xc938
+#define E4210_GATE_IP_LCD1	0xc938
 #define E4X12_GATE_IP_ISP	0xc938
 #define E4X12_GATE_IP_MAUDIO	0xc93c
 #define GATE_IP_FSYS		0xc940
@@ -326,8 +326,8 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
 	MUX(none, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1),
 	MUX(none, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1),
 	MUX(none, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1),
-	MUX(none, "mout_fimd1", group1_p4210, SRC_LCD1, 0, 4),
-	MUX(none, "mout_mipi1", group1_p4210, SRC_LCD1, 12, 4),
+	MUX(none, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4),
+	MUX(none, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
 	MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "sclk_mpll"),
 	MUX_A(mout_core, "mout_core", mout_core_p4210, SRC_CPU, 16, 1, "mout_core"),
 	MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210,
@@ -537,10 +537,10 @@ struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
 	GATE(jpeg, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0),
 	GATE(mie0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0),
 	GATE(dsim0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0),
-	GATE(fimd1, "fimd1", "aclk160", GATE_IP_LCD1, 0, 0, 0),
-	GATE(mie1, "mie1", "aclk160", GATE_IP_LCD1, 1, 0, 0),
-	GATE(dsim1, "dsim1", "aclk160", GATE_IP_LCD1, 3, 0, 0),
-	GATE(smmu_fimd1, "smmu_fimd1", "aclk160", GATE_IP_LCD1, 4, 0, 0),
+	GATE(fimd1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0),
+	GATE(mie1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0),
+	GATE(dsim1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0),
+	GATE(smmu_fimd1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0, 0),
 	GATE(tsi, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0),
 	GATE(sromc, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
 	GATE(sclk_g3d, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0,
@@ -737,7 +737,7 @@ struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
 	GATE(smmu_rotator, "smmu_rotator", "aclk200",
 			E4210_GATE_IP_IMAGE, 4, 0, 0),
 	GATE(sclk_mipi1, "sclk_mipi1", "div_mipi_pre1",
-			SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0),
+			E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0),
 	GATE(sclk_sata, "sclk_sata", "div_sata",
 			SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
 	GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
@@ -748,7 +748,7 @@ struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
 	GATE_A(rtc, "rtc", "aclk100", GATE_IP_PERIR, 15, 0, 0, "rtc"),
 	GATE_A(keyif, "keyif", "aclk100", GATE_IP_PERIR, 16, 0, 0, "keypad"),
 	GATE_DA(sclk_fimd1, "exynos4-fb.1", "sclk_fimd1", "div_fimd1",
-			SRC_MASK_LCD1, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"),
+			E4210_SRC_MASK_LCD1, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"),
 };
 
 /* list of gate clocks supported in exynos4x12 soc */
-- 
1.8.1.5

[PATCH 18/21] clk: samsung: exynos4: Add E4210 prefix to GATE_IP_PERIR register

[Tomasz Figa]

This definition is specific for Exynos4210 (which has another location
than the same register on Exynos4x12 SoCs) and so needs appropriate
prefix.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 drivers/clk/samsung/clk-exynos4.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index c84dbc9..a89cac9 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -91,7 +91,7 @@
 #define GATE_IP_FSYS		0xc940
 #define GATE_IP_GPS		0xc94c
 #define GATE_IP_PERIL		0xc950
-#define GATE_IP_PERIR		0xc960
+#define E4210_GATE_IP_PERIR	0xc960
 #define E4X12_MPLL_CON0		0x10108
 #define E4X12_SRC_DMC		0x10200
 #define APLL_CON0		0x14100
@@ -731,9 +731,9 @@ struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
 	GATE(pcie, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0),
 	GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
 	GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
-	GATE(chipid, "chipid", "aclk100", GATE_IP_PERIR, 0, 0, 0),
-	GATE(sysreg, "sysreg", "aclk100", GATE_IP_PERIR, 0, 0, 0),
-	GATE(hdmi_cec, "hdmi_cec", "aclk100", GATE_IP_PERIR, 11, 0, 0),
+	GATE(chipid, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
+	GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
+	GATE(hdmi_cec, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, 0),
 	GATE(smmu_rotator, "smmu_rotator", "aclk200",
 			E4210_GATE_IP_IMAGE, 4, 0, 0),
 	GATE(sclk_mipi1, "sclk_mipi1", "div_mipi_pre1",
@@ -743,10 +743,10 @@ struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
 	GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
 	GATE(sclk_dac, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
 	GATE_A(tsadc, "tsadc", "aclk100", GATE_IP_PERIL, 15, 0, 0, "adc"),
-	GATE_A(mct, "mct", "aclk100", GATE_IP_PERIR, 13, 0, 0, "mct"),
-	GATE_A(wdt, "watchdog", "aclk100", GATE_IP_PERIR, 14, 0, 0, "watchdog"),
-	GATE_A(rtc, "rtc", "aclk100", GATE_IP_PERIR, 15, 0, 0, "rtc"),
-	GATE_A(keyif, "keyif", "aclk100", GATE_IP_PERIR, 16, 0, 0, "keypad"),
+	GATE_A(mct, "mct", "aclk100", E4210_GATE_IP_PERIR, 13, 0, 0, "mct"),
+	GATE_A(wdt, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14, 0, 0, "watchdog"),
+	GATE_A(rtc, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15, 0, 0, "rtc"),
+	GATE_A(keyif, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16, 0, 0, "keypad"),
 	GATE_DA(sclk_fimd1, "exynos4-fb.1", "sclk_fimd1", "div_fimd1",
 			E4210_SRC_MASK_LCD1, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"),
 };
-- 
1.8.1.5

[PATCH 19/21] clk: samsung: exynos4: Remove E4X12 prefix from SRC_DMC register

[Tomasz Figa]

This register is present on all Exynos4 SoCs and so the prefix is
misleading.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 drivers/clk/samsung/clk-exynos4.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index a89cac9..571b7e3 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -93,7 +93,7 @@
 #define GATE_IP_PERIL		0xc950
 #define E4210_GATE_IP_PERIR	0xc960
 #define E4X12_MPLL_CON0		0x10108
-#define E4X12_SRC_DMC		0x10200
+#define SRC_DMC			0x10200
 #define APLL_CON0		0x14100
 #define E4210_MPLL_CON0		0x14108
 #define SRC_CPU			0x14200
@@ -388,7 +388,7 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
 	MUX(none, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1),
 	MUX(none, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
 	MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p,
-			E4X12_SRC_DMC, 12, 1, "sclk_mpll"),
+			SRC_DMC, 12, 1, "sclk_mpll"),
 	MUX_A(sclk_vpll, "sclk_vpll", mout_vpll_p,
 			SRC_TOP0, 8, 1, "sclk_vpll"),
 	MUX(mout_core, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
-- 
1.8.1.5

[PATCH 20/21] clk: samsung: exynos4: Add missing registers to suspend save list

[Tomasz Figa]

This patch adds missing clock control registers to the list of registers
that should be saved across system suspend.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 drivers/clk/samsung/clk-exynos4.c | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 571b7e3..279c435 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -22,7 +22,11 @@
 
 /* Exynos4 clock controller register offsets */
 #define SRC_LEFTBUS		0x4200
+#define DIV_LEFTBUS		0x4500
+#define GATE_IP_LEFTBUS		0x4800
 #define E4X12_GATE_IP_IMAGE	0x4930
+#define SRC_RIGHTBUS		0x8200
+#define DIV_RIGHTBUS		0x8500
 #define GATE_IP_RIGHTBUS	0x8800
 #define E4X12_GATE_IP_PERIR	0x8960
 #define EPLL_LOCK		0xc010
@@ -48,6 +52,7 @@
 #define SRC_PERIL0		0xc250
 #define SRC_PERIL1		0xc254
 #define E4X12_SRC_CAM1		0xc258
+#define SRC_MASK_TOP		0xc310
 #define SRC_MASK_CAM		0xc320
 #define SRC_MASK_TV		0xc324
 #define SRC_MASK_LCD0		0xc334
@@ -92,12 +97,20 @@
 #define GATE_IP_GPS		0xc94c
 #define GATE_IP_PERIL		0xc950
 #define E4210_GATE_IP_PERIR	0xc960
+#define GATE_BLOCK		0xc970
 #define E4X12_MPLL_CON0		0x10108
 #define SRC_DMC			0x10200
+#define SRC_MASK_DMC		0x10300
+#define DIV_DMC0		0x10500
+#define DIV_DMC1		0x10504
+#define GATE_IP_DMC		0x10900
 #define APLL_CON0		0x14100
 #define E4210_MPLL_CON0		0x14108
 #define SRC_CPU			0x14200
 #define DIV_CPU0		0x14500
+#define DIV_CPU1		0x14504
+#define GATE_SCLK_CPU		0x14800
+#define GATE_IP_CPU		0x14900
 #define E4X12_DIV_ISP0		0x18300
 #define E4X12_DIV_ISP1		0x18304
 #define E4X12_GATE_ISP0		0x18800
@@ -172,7 +185,17 @@ enum exynos4_clks {
  */
 static __initdata unsigned long exynos4_clk_regs[] = {
 	SRC_LEFTBUS,
+	DIV_LEFTBUS,
+	GATE_IP_LEFTBUS,
+	SRC_RIGHTBUS,
+	DIV_RIGHTBUS,
 	GATE_IP_RIGHTBUS,
+	EPLL_CON0,
+	EPLL_CON1,
+	EPLL_CON2,
+	VPLL_CON0,
+	VPLL_CON1,
+	VPLL_CON2,
 	SRC_TOP0,
 	SRC_TOP1,
 	SRC_CAM,
@@ -184,6 +207,7 @@ static __initdata unsigned long exynos4_clk_regs[] = {
 	SRC_FSYS,
 	SRC_PERIL0,
 	SRC_PERIL1,
+	SRC_MASK_TOP,
 	SRC_MASK_CAM,
 	SRC_MASK_TV,
 	SRC_MASK_LCD0,
@@ -218,9 +242,18 @@ static __initdata unsigned long exynos4_clk_regs[] = {
 	GATE_IP_FSYS,
 	GATE_IP_GPS,
 	GATE_IP_PERIL,
+	GATE_BLOCK,
+	SRC_MASK_DMC,
+	SRC_DMC,
+	DIV_DMC0,
+	DIV_DMC1,
+	GATE_IP_DMC,
 	APLL_CON0,
 	SRC_CPU,
 	DIV_CPU0,
+	DIV_CPU1,
+	GATE_SCLK_CPU,
+	GATE_IP_CPU,
 };
 
 /* list of all parent clock list */
-- 
1.8.1.5

[PATCH 21/21] clk: samsung: exynos4: Add support for SoC-specific register save list

[Tomasz Figa]

This patch extends suspend/resume support for SoC-specific registers to
handle differences in register sets on particular SoCs.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 drivers/clk/samsung/clk-exynos4.c    | 30 ++++++++++++++++++++++++++++--
 drivers/clk/samsung/clk-exynos5250.c |  3 ++-
 drivers/clk/samsung/clk-exynos5440.c |  2 +-
 drivers/clk/samsung/clk.c            |  9 ++++++---
 drivers/clk/samsung/clk.h            |  3 ++-
 5 files changed, 39 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 279c435..607ff3a 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -183,6 +183,26 @@ enum exynos4_clks {
  * list of controller registers to be saved and restored during a
  * suspend/resume cycle.
  */
+static __initdata unsigned long exynos4210_clk_save[] = {
+	E4210_SRC_IMAGE,
+	E4210_SRC_LCD1,
+	E4210_SRC_MASK_LCD1,
+	E4210_DIV_LCD1,
+	E4210_GATE_IP_IMAGE,
+	E4210_GATE_IP_LCD1,
+	E4210_GATE_IP_PERIR,
+	E4210_MPLL_CON0,
+};
+
+static __initdata unsigned long exynos4x12_clk_save[] = {
+	E4X12_GATE_IP_IMAGE,
+	E4X12_GATE_IP_PERIR,
+	E4X12_SRC_CAM1,
+	E4X12_DIV_ISP,
+	E4X12_DIV_CAM1,
+	E4X12_MPLL_CON0,
+};
+
 static __initdata unsigned long exynos4_clk_regs[] = {
 	SRC_LEFTBUS,
 	DIV_LEFTBUS,
@@ -985,8 +1005,14 @@ void __init exynos4_clk_init(struct device_node *np)
 			panic("%s: unable to determine soc\n", __func__);
 	}
 
-	samsung_clk_init(np, reg_base, nr_clks,
-		exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs));
+	if (exynos4_soc == EXYNOS4210)
+		samsung_clk_init(np, reg_base, nr_clks,
+			exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
+			exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save));
+	else
+		samsung_clk_init(np, reg_base, nr_clks,
+			exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
+			exynos4x12_clk_save, ARRAY_SIZE(exynos4x12_clk_save));
 
 	if (np)
 		samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks,
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 1152125..5cd9a0c 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -477,7 +477,8 @@ void __init exynos5250_clk_init(struct device_node *np)
 	}
 
 	samsung_clk_init(np, reg_base, nr_clks,
-			exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs));
+			exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs),
+			NULL, 0);
 	samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks,
 			ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
 			ext_clk_match);
diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c
index d588e93..a0a094c 100644
--- a/drivers/clk/samsung/clk-exynos5440.c
+++ b/drivers/clk/samsung/clk-exynos5440.c
@@ -115,7 +115,7 @@ void __init exynos5440_clk_init(struct device_node *np)
 		return;
 	}
 
-	samsung_clk_init(np, reg_base, nr_clks, NULL, 0);
+	samsung_clk_init(np, reg_base, nr_clks, NULL, 0, NULL, 0);
 	samsung_clk_of_register_fixed_ext(exynos5440_fixed_rate_ext_clks,
 		ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match);
 
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index 82f27f6..3a50d4f 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -54,7 +54,8 @@ static struct syscore_ops samsung_clk_syscore_ops = {
 /* setup the essentials required to support clock lookup using ccf */
 void __init samsung_clk_init(struct device_node *np, void __iomem *base,
 		unsigned long nr_clks, unsigned long *rdump,
-		unsigned long nr_rdump)
+		unsigned long nr_rdump, unsigned long *soc_rdump,
+		unsigned long nr_soc_rdump)
 {
 	reg_base = base;
 
@@ -62,7 +63,7 @@ void __init samsung_clk_init(struct device_node *np, void __iomem *base,
 	if (rdump && nr_rdump) {
 		unsigned int idx;
 		reg_dump = kzalloc(sizeof(struct samsung_clk_reg_dump)
-					* nr_rdump, GFP_KERNEL);
+				* (nr_rdump + nr_soc_rdump), GFP_KERNEL);
 		if (!reg_dump) {
 			pr_err("%s: memory alloc for register dump failed\n",
 					__func__);
@@ -71,7 +72,9 @@ void __init samsung_clk_init(struct device_node *np, void __iomem *base,
 
 		for (idx = 0; idx < nr_rdump; idx++)
 			reg_dump[idx].offset = rdump[idx];
-		nr_reg_dump = nr_rdump;
+		for (idx = 0; idx < nr_soc_rdump; idx++)
+			reg_dump[nr_rdump + idx].offset = soc_rdump[idx];
+		nr_reg_dump = nr_rdump + nr_soc_rdump;
 		register_syscore_ops(&samsung_clk_syscore_ops);
 	}
 #endif
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index 6bacd6f..10b2111 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -262,7 +262,8 @@ struct samsung_clk_reg_dump {
 
 extern void __init samsung_clk_init(struct device_node *np, void __iomem *base,
 		unsigned long nr_clks, unsigned long *rdump,
-		unsigned long nr_rdump);
+		unsigned long nr_rdump, unsigned long *soc_rdump,
+		unsigned long nr_soc_rdump);
 extern void __init samsung_clk_of_register_fixed_ext(
 		struct samsung_fixed_rate_clock *fixed_rate_clk,
 		unsigned int nr_fixed_rate_clk,
-- 
1.8.1.5

[PATCH 00/21] Various fixes and extensions to Exynos4 clock driver

[Thomas Abraham]

Hi Tomasz,

On 27 March 2013 16:32, Tomasz Figa <t.figa@samsung.com> wrote:
> This series is a collection of various fixes and extensions to Exynos4
> clock driver, which improve coverage of clocks present on Exynos4 SoCs
> and fix problems discovered during our internal work and testing.

Nice series. Thanks for the improvements and fixes. Looking at the
second patch in this series, I crossed checked again with the
Exynos4412 user manual that I have. Your modifications are different
from what the manual has listed. I suspect, you have a newer copy of
the manual.

For this series:
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>

Thanks,
Thomas.

>
> Andrzej Hajda (1):
>   clk: samsung: exynos4: Add missing CMU_TOP and ISP clocks
>
> Lukasz Majewski (1):
>   clk: samsung: exynos4: Export clocks used by exynos cpufreq drivers
>
> Sylwester Nawrocki (2):
>   clk: samsung: exynos4: Correct sclk_mfc clock definition
>   clk: samsung: exynos4: Add camera related clock definitions
>
> Tomasz Figa (17):
>   clk: samsung: exynos4: Use mout_mpll_user_* on Exynos4x12
>   clk: samsung: exynos4: Add missing mout_mipihsi clock
>   clk: samsung: exynos4: Add missing sclk_audio0 clock
>   clk: samsung: exynos4: Export sclk_pcm0
>   clk: samsung: exynos4: Move dac and mixer to Exynos4210-specific
>     clocks
>   clk: samsung: pll: Remove unimplemented ops
>   clk: samsung: exynos4: Export mout_core clock of Exynos4210
>   clk: samsung: exynos4: Add G3D clocks
>   clk: samsung: exynos4: Add missing mout_sata on Exynos4210
>   clk: samsung: exynos4: Define {E,V}PLL registers
>   clk: samsung: exynos4: Use SRC_MASK_PERIL{0,1} definitions
>   clk: samsung: exynos4: Remove SoC-specific registers from save list
>   clk: samsung: exynos4: Add E4210 prefix to LCD1 clock registers
>   clk: samsung: exynos4: Add E4210 prefix to GATE_IP_PERIR register
>   clk: samsung: exynos4: Remove E4X12 prefix from SRC_DMC register
>   clk: samsung: exynos4: Add missing registers to suspend save list
>   clk: samsung: exynos4: Add support for SoC-specific register save list
>
>  .../devicetree/bindings/clock/exynos4-clock.txt    |  61 ++-
>  drivers/clk/samsung/clk-exynos4.c                  | 491 +++++++++++++++------
>  drivers/clk/samsung/clk-exynos5250.c               |   3 +-
>  drivers/clk/samsung/clk-exynos5440.c               |   2 +-
>  drivers/clk/samsung/clk-pll.c                      |  80 ----
>  drivers/clk/samsung/clk.c                          |   9 +-
>  drivers/clk/samsung/clk.h                          |   3 +-
>  7 files changed, 437 insertions(+), 212 deletions(-)
>
> --
> 1.8.1.5
>

[PATCH 00/21] Various fixes and extensions to Exynos4 clock driver

[Tomasz Figa]

On Saturday 30 of March 2013 15:33:00 Thomas Abraham wrote:
> Hi Tomasz,
> 
> On 27 March 2013 16:32, Tomasz Figa <t.figa@samsung.com> wrote:
> > This series is a collection of various fixes and extensions to Exynos4
> > clock driver, which improve coverage of clocks present on Exynos4 SoCs
> > and fix problems discovered during our internal work and testing.
> 
> Nice series. Thanks for the improvements and fixes. Looking at the
> second patch in this series, I crossed checked again with the
> Exynos4412 user manual that I have. Your modifications are different
> from what the manual has listed. I suspect, you have a newer copy of
> the manual.

Right. I have checked revisions 0.0, 0.1 and 1.1 of the manual and indeed 
there are differences in clock layout between 0.1 and 1.1. My patches are 
based on revision 1.1.

> For this series:
> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>

Thanks.

Best regards,
Tomasz

> Thanks,
> Thomas.
> 
> > Andrzej Hajda (1):
> >   clk: samsung: exynos4: Add missing CMU_TOP and ISP clocks
> > 
> > Lukasz Majewski (1):
> >   clk: samsung: exynos4: Export clocks used by exynos cpufreq drivers
> > 
> > Sylwester Nawrocki (2):
> >   clk: samsung: exynos4: Correct sclk_mfc clock definition
> >   clk: samsung: exynos4: Add camera related clock definitions
> > 
> > Tomasz Figa (17):
> >   clk: samsung: exynos4: Use mout_mpll_user_* on Exynos4x12
> >   clk: samsung: exynos4: Add missing mout_mipihsi clock
> >   clk: samsung: exynos4: Add missing sclk_audio0 clock
> >   clk: samsung: exynos4: Export sclk_pcm0
> >   clk: samsung: exynos4: Move dac and mixer to Exynos4210-specific
> >   
> >     clocks
> >   
> >   clk: samsung: pll: Remove unimplemented ops
> >   clk: samsung: exynos4: Export mout_core clock of Exynos4210
> >   clk: samsung: exynos4: Add G3D clocks
> >   clk: samsung: exynos4: Add missing mout_sata on Exynos4210
> >   clk: samsung: exynos4: Define {E,V}PLL registers
> >   clk: samsung: exynos4: Use SRC_MASK_PERIL{0,1} definitions
> >   clk: samsung: exynos4: Remove SoC-specific registers from save list
> >   clk: samsung: exynos4: Add E4210 prefix to LCD1 clock registers
> >   clk: samsung: exynos4: Add E4210 prefix to GATE_IP_PERIR register
> >   clk: samsung: exynos4: Remove E4X12 prefix from SRC_DMC register
> >   clk: samsung: exynos4: Add missing registers to suspend save list
> >   clk: samsung: exynos4: Add support for SoC-specific register save
> >   list
> >  
> >  .../devicetree/bindings/clock/exynos4-clock.txt    |  61 ++-
> >  drivers/clk/samsung/clk-exynos4.c                  | 491
> >  +++++++++++++++------ drivers/clk/samsung/clk-exynos5250.c          
> >      |   3 +-
> >  drivers/clk/samsung/clk-exynos5440.c               |   2 +-
> >  drivers/clk/samsung/clk-pll.c                      |  80 ----
> >  drivers/clk/samsung/clk.c                          |   9 +-
> >  drivers/clk/samsung/clk.h                          |   3 +-
> >  7 files changed, 437 insertions(+), 212 deletions(-)
> > 
> > --
> > 1.8.1.5
> 
> --
> To unsubscribe from this list: send the line "unsubscribe
> linux-samsung-soc" in the body of a message to
> majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 00/21] Various fixes and extensions to Exynos4 clock driver

[Kukjin Kim]

Tomasz Figa wrote:
> 
> On Saturday 30 of March 2013 15:33:00 Thomas Abraham wrote:
> > Hi Tomasz,
> >
> > On 27 March 2013 16:32, Tomasz Figa <t.figa@samsung.com> wrote:
> > > This series is a collection of various fixes and extensions to Exynos4
> > > clock driver, which improve coverage of clocks present on Exynos4 SoCs
> > > and fix problems discovered during our internal work and testing.
> >
> > Nice series. Thanks for the improvements and fixes. Looking at the
> > second patch in this series, I crossed checked again with the
> > Exynos4412 user manual that I have. Your modifications are different
> > from what the manual has listed. I suspect, you have a newer copy of
> > the manual.
> 
> Right. I have checked revisions 0.0, 0.1 and 1.1 of the manual and indeed
> there are differences in clock layout between 0.1 and 1.1. My patches are
> based on revision 1.1.
> 
Correct...hmm...

> > For this series:
> > Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
> 
Yes, looks good to me but would be better if I could get Mike's ack on this
series.

Thanks.

- Kukjin

[PATCH 00/21] Various fixes and extensions to Exynos4 clock driver

[Mike Turquette]

Quoting Kukjin Kim (2013-04-02 01:30:39)
> Tomasz Figa wrote:
> > 
> > On Saturday 30 of March 2013 15:33:00 Thomas Abraham wrote:
> > > Hi Tomasz,
> > >
> > > On 27 March 2013 16:32, Tomasz Figa <t.figa@samsung.com> wrote:
> > > > This series is a collection of various fixes and extensions to Exynos4
> > > > clock driver, which improve coverage of clocks present on Exynos4 SoCs
> > > > and fix problems discovered during our internal work and testing.
> > >
> > > Nice series. Thanks for the improvements and fixes. Looking at the
> > > second patch in this series, I crossed checked again with the
> > > Exynos4412 user manual that I have. Your modifications are different
> > > from what the manual has listed. I suspect, you have a newer copy of
> > > the manual.
> > 
> > Right. I have checked revisions 0.0, 0.1 and 1.1 of the manual and indeed
> > there are differences in clock layout between 0.1 and 1.1. My patches are
> > based on revision 1.1.
> > 
> Correct...hmm...
> 
> > > For this series:
> > > Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
> > 
> Yes, looks good to me but would be better if I could get Mike's ack on this
> series.
> 

Acked-by: Mike Turquette <mturquette@linaro.org>

> Thanks.
> 
> - Kukjin

[PATCH 00/21] Various fixes and extensions to Exynos4 clock driver

[Kukjin Kim]

Mike Turquette wrote:
> 
> Quoting Kukjin Kim (2013-04-02 01:30:39)
> > Tomasz Figa wrote:
> > >
> > > On Saturday 30 of March 2013 15:33:00 Thomas Abraham wrote:
> > > > Hi Tomasz,
> > > >
> > > > On 27 March 2013 16:32, Tomasz Figa <t.figa@samsung.com> wrote:
> > > > > This series is a collection of various fixes and extensions to
> Exynos4
> > > > > clock driver, which improve coverage of clocks present on Exynos4
> SoCs
> > > > > and fix problems discovered during our internal work and testing.
> > > >
> > > > Nice series. Thanks for the improvements and fixes. Looking at the
> > > > second patch in this series, I crossed checked again with the
> > > > Exynos4412 user manual that I have. Your modifications are different
> > > > from what the manual has listed. I suspect, you have a newer copy of
> > > > the manual.
> > >
> > > Right. I have checked revisions 0.0, 0.1 and 1.1 of the manual and
> indeed
> > > there are differences in clock layout between 0.1 and 1.1. My patches
> are
> > > based on revision 1.1.
> > >
> > Correct...hmm...
> >
> > > > For this series:
> > > > Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
> > >
> > Yes, looks good to me but would be better if I could get Mike's ack on
> this
> > series.
> >
> 
> Acked-by: Mike Turquette <mturquette@linaro.org>
> 
Thanks, applied.

- Kukjin