[PATCH 00/17] coresight: next v4.12-rc4

[PATCH 00/17] coresight: next v4.12-rc4

[Mathieu Poirier]

Hi Greg,

Please consider for inclusion in the 4.13 cycle.  Of particular interest is
patch 15/17, which adds a new driver under the CoreSight umbrella.
Everything applies cleanly on today's char-misc-next branch (73726380a26f).

Regards,
Mathieu

Leo Yan (10):
  coresight: tmc: minor fix for output log
  coresight: use const for device_node structures
  coresight: bindings for CPU debug module
  doc: Add documentation for Coresight CPU debug
  doc: Add coresight_cpu_debug.enable to kernel-parameters.txt
  MAINTAINERS: update file entries for Coresight subsystem
  coresight: refactor with function of_coresight_get_cpu
  coresight: add support for CPU debug module
  arm64: dts: hi6220: register debug module
  arm64: dts: qcom: msm8916: Add debug unit

Markus Elfring (2):
  coresight: etb10: Delete an error message for a failed memory
    allocation in etb_probe()
  coresight: etb10: Fix a typo in a comment line

Robin Murphy (1):
  coresight: tmc: Configure DMA mask appropriately

Suzuki K Poulose (4):
  coresight: Disable the path only when the source is disabled
  coresight: Fix reference count for software sources
  coresight: etm_perf: Fix using uninitialised work
  coresight: of_get_coresight_platform_data: Add missing of_node_put

 Documentation/admin-guide/kernel-parameters.txt    |   7 +
 .../bindings/arm/coresight-cpu-debug.txt           |  49 ++
 Documentation/trace/coresight-cpu-debug.txt        | 175 ++++++
 MAINTAINERS                                        |   2 +
 arch/arm64/boot/dts/hisilicon/hi6220.dtsi          |  64 ++
 arch/arm64/boot/dts/qcom/msm8916.dtsi              |  32 +
 drivers/hwtracing/coresight/Kconfig                |  14 +
 drivers/hwtracing/coresight/Makefile               |   1 +
 drivers/hwtracing/coresight/coresight-cpu-debug.c  | 700 +++++++++++++++++++++
 drivers/hwtracing/coresight/coresight-etb10.c      |   7 +-
 drivers/hwtracing/coresight/coresight-etm-perf.c   |   3 +-
 drivers/hwtracing/coresight/coresight-tmc-etf.c    |  25 +-
 drivers/hwtracing/coresight/coresight-tmc.c        |   7 +
 drivers/hwtracing/coresight/coresight.c            |  34 +-
 drivers/hwtracing/coresight/of_coresight.c         |  47 +-
 include/linux/coresight.h                          |  10 +-
 16 files changed, 1136 insertions(+), 41 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
 create mode 100644 Documentation/trace/coresight-cpu-debug.txt
 create mode 100644 drivers/hwtracing/coresight/coresight-cpu-debug.c

-- 
2.7.4

[PATCH 01/17] coresight: Disable the path only when the source is disabled

[Mathieu Poirier]

From: Suzuki K Poulose <suzuki.poulose@arm.com>

With a coresight tracing session, the components along the path
from the source to sink are disabled after the source is disabled.
However, if the source was not actually disabled due to active
users, we should not disable the components in the path.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/hwtracing/coresight/coresight.c | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c
index 0c37356e417c..532a2acfa8cc 100644
--- a/drivers/hwtracing/coresight/coresight.c
+++ b/drivers/hwtracing/coresight/coresight.c
@@ -253,14 +253,22 @@ static int coresight_enable_source(struct coresight_device *csdev, u32 mode)
 	return 0;
 }
 
-static void coresight_disable_source(struct coresight_device *csdev)
+/**
+ *  coresight_disable_source - Drop the reference count by 1 and disable
+ *  the device if there are no users left.
+ *
+ *  @csdev - The coresight device to disable
+ *
+ *  Returns true if the device has been disabled.
+ */
+static bool coresight_disable_source(struct coresight_device *csdev)
 {
 	if (atomic_dec_return(csdev->refcnt) == 0) {
-		if (source_ops(csdev)->disable) {
+		if (source_ops(csdev)->disable)
 			source_ops(csdev)->disable(csdev, NULL);
-			csdev->enable = false;
-		}
+		csdev->enable = false;
 	}
+	return !csdev->enable;
 }
 
 void coresight_disable_path(struct list_head *path)
@@ -629,7 +637,7 @@ void coresight_disable(struct coresight_device *csdev)
 	if (ret)
 		goto out;
 
-	if (!csdev->enable)
+	if (!csdev->enable || !coresight_disable_source(csdev))
 		goto out;
 
 	switch (csdev->subtype.source_subtype) {
@@ -647,7 +655,6 @@ void coresight_disable(struct coresight_device *csdev)
 		break;
 	}
 
-	coresight_disable_source(csdev);
 	coresight_disable_path(path);
 	coresight_release_path(path);
 
-- 
2.7.4

[PATCH 02/17] coresight: Fix reference count for software sources

[Mathieu Poirier]

From: Suzuki K Poulose <suzuki.poulose@arm.com>

For software sources (i.e STM), there could be multiple agents
generating the trace data, unlike the ETMs. So we need to
properly do the accounting for the active number of users
to disable the device when the last user goes away. Right
now, the reference counting is broken for sources as we skip
the actions when we detect that the source is enabled.

This patch fixes the problem by adding the refcounting for
software sources, even when they are enabled.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Reported-by: Robert Walker <robert.walker@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/hwtracing/coresight/coresight.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c
index 532a2acfa8cc..6a0202b7384f 100644
--- a/drivers/hwtracing/coresight/coresight.c
+++ b/drivers/hwtracing/coresight/coresight.c
@@ -558,6 +558,9 @@ int coresight_enable(struct coresight_device *csdev)
 	int cpu, ret = 0;
 	struct coresight_device *sink;
 	struct list_head *path;
+	enum coresight_dev_subtype_source subtype;
+
+	subtype = csdev->subtype.source_subtype;
 
 	mutex_lock(&coresight_mutex);
 
@@ -565,8 +568,16 @@ int coresight_enable(struct coresight_device *csdev)
 	if (ret)
 		goto out;
 
-	if (csdev->enable)
+	if (csdev->enable) {
+		/*
+		 * There could be multiple applications driving the software
+		 * source. So keep the refcount for each such user when the
+		 * source is already enabled.
+		 */
+		if (subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE)
+			atomic_inc(csdev->refcnt);
 		goto out;
+	}
 
 	/*
 	 * Search for a valid sink for this session but don't reset the
@@ -593,7 +604,7 @@ int coresight_enable(struct coresight_device *csdev)
 	if (ret)
 		goto err_source;
 
-	switch (csdev->subtype.source_subtype) {
+	switch (subtype) {
 	case CORESIGHT_DEV_SUBTYPE_SOURCE_PROC:
 		/*
 		 * When working from sysFS it is important to keep track
-- 
2.7.4

[PATCH 03/17] coresight: etm_perf: Fix using uninitialised work

[Mathieu Poirier]

From: Suzuki K Poulose <suzuki.poulose@arm.com>

With 4.11-rc4, the following command triggers a WARN_ON,
when a sink is not enabled.

 perf record -e cs_etm/@20010000.etf/

 [88286.547741] ------------[ cut here ]------------
 [88286.552332] WARNING: CPU: 3 PID: 2156 at kernel/workqueue.c:1442 __queue_work+0x29c/0x3b8
 [88286.560427] Modules linked in:
 [88286.563451]
 [88286.564928] CPU: 3 PID: 2156 Comm: perf_v4.11 Not tainted 4.11.0-rc4 #217
 [88286.573453] Hardware name: ARM LTD ARM Juno Development Platform/ARM Juno Development Platform, BIOS EDK II Aug 15
  2016
 [88286.584128] task: ffff80097597c200 task.stack: ffff8009768b0000
 [88286.589990] PC is at __queue_work+0x29c/0x3b8
 [88286.594303] LR is at __queue_work+0x104/0x3b8
 [88286.598614] pc : [<ffff0000080d8c7c>] lr : [<ffff0000080d8ae4>] pstate: a00001c5
 [88286.605934] sp : ffff8009768b3aa0
 [88286.609212] x29: ffff8009768b3aa0 x28: ffff80097ff3da00
 [88286.614477] x27: ffff80097ff89c00 x26: ffff8009751b0e00
 [88286.619741] x25: ffff000008c9f000 x24: 0000000000000003
 [88286.625004] x23: 0000000000000040 x22: ffff000008d3dab8
 [88286.630268] x21: ffff800977804400 x20: 0000000000000007
 [88286.635532] x19: ffff000008c54000 x18: 0000fffff9185160
 [88286.640795] x17: 0000ffffb33d9a38 x16: ffff000008088270
 [88286.646059] x15: 0000ffffb345b590 x14: 0000000000000000
 [88286.651322] x13: 0000000000000004 x12: 0000000000000040
 [88286.656586] x11: 0000000000000068 x10: 0000000000000000
 [88286.661849] x9 : ffff800977400028 x8 : 0000000000000000
 [88286.667113] x7 : 0000000000000000 x6 : ffff0000080d8ae4
 [88286.672376] x5 : 0000000000000000 x4 : 0000000000000080
 [88286.677639] x3 : 0000000000000000 x2 : 0000000000000000
 [88286.682903] x1 : 0000000000000000 x0 : ffff8009751b0e08
 [88286.688166]
 [88286.689638] ---[ end trace 31633f18fd33d4cb ]---
 [88286.694206] Call trace:
 [88286.696627] Exception stack(0xffff8009768b38d0 to 0xffff8009768b3a00)
 [88286.703004] 38c0:                                   ffff000008c54000 0001000000000000
 [88286.710757] 38e0: ffff8009768b3aa0 ffff0000080d8c7c ffff8009768b3b50 ffff80097ff8a5b0
 [88286.718511] 3900: 0000800977325000 0000000000000000 0000000000000040 ffff80097ffc6180
 [88286.726264] 3920: ffff8009768b3940 ffff0000088a8694 ffff80097ffc5800 0000000000000000
 [88286.734017] 3940: ffff8009768b3960 ffff0000081919c0 ffff80097ffc5280 0000000000000001
 [88286.741771] 3960: ffff8009768b3a50 ffff00000819206c ffff8009751b0e08 0000000000000000
 [88286.749523] 3980: 0000000000000000 0000000000000000 0000000000000080 0000000000000000
 [88286.757277] 39a0: ffff0000080d8ae4 0000000000000000 0000000000000000 ffff800977400028
 [88286.765029] 39c0: 0000000000000000 0000000000000068 0000000000000040 0000000000000004
 [88286.772783] 39e0: 0000000000000000 0000ffffb345b590 ffff000008088270 0000ffffb33d9a38
 [88286.780537] [<ffff0000080d8c7c>] __queue_work+0x29c/0x3b8
 [88286.785883] [<ffff0000080d8df8>] queue_work_on+0x60/0x78
 [88286.791146] [<ffff000008764c68>] etm_setup_aux+0x178/0x238
 [88286.796578] [<ffff000008183600>] rb_alloc_aux+0x228/0x310
 [88286.801925] [<ffff00000817e564>] perf_mmap+0x404/0x5a8
 [88286.807015] [<ffff0000081c60cc>] mmap_region+0x394/0x5c0
 [88286.812276] [<ffff0000081c654c>] do_mmap+0x254/0x388
 [88286.817191] [<ffff0000081a989c>] vm_mmap_pgoff+0xbc/0xe0
 [88286.822452] [<ffff0000081c3ffc>] SyS_mmap_pgoff+0xac/0x228
 [88286.827884] [<ffff000008088288>] sys_mmap+0x18/0x28
 [88286.832714] [<ffff000008082f30>] el0_svc_naked+0x24/0x28

The patch makes sure that the event_data->work is initialised
properly before we could possibly use it.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Tested-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/hwtracing/coresight/coresight-etm-perf.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c
index 288a423c1b27..8f546f59a3fd 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -201,6 +201,7 @@ static void *etm_setup_aux(int event_cpu, void **pages,
 	event_data = alloc_event_data(event_cpu);
 	if (!event_data)
 		return NULL;
+	INIT_WORK(&event_data->work, free_event_data);
 
 	/*
 	 * In theory nothing prevent tracers in a trace session from being
@@ -217,8 +218,6 @@ static void *etm_setup_aux(int event_cpu, void **pages,
 	if (!sink)
 		goto err;
 
-	INIT_WORK(&event_data->work, free_event_data);
-
 	mask = &event_data->mask;
 
 	/* Setup the path for each CPU in a trace session */
-- 
2.7.4

[PATCH 03/17] coresight: etm_perf: Fix using uninitialised work

[Kim Phillips]

On Mon,  5 Jun 2017 14:15:04 -0600
Mathieu Poirier <mathieu.poirier@linaro.org> wrote:

> From: Suzuki K Poulose <suzuki.poulose@arm.com>
> 
> With 4.11-rc4, the following command triggers a WARN_ON,
> when a sink is not enabled.
> 
>  perf record -e cs_etm/@20010000.etf/
> 
>  [88286.547741] ------------[ cut here ]------------
>  [88286.552332] WARNING: CPU: 3 PID: 2156 at kernel/workqueue.c:1442 __queue_work+0x29c/0x3b8
>  [88286.560427] Modules linked in:
>  [88286.563451]
>  [88286.564928] CPU: 3 PID: 2156 Comm: perf_v4.11 Not tainted 4.11.0-rc4 #217
>  [88286.573453] Hardware name: ARM LTD ARM Juno Development Platform/ARM Juno Development Platform, BIOS EDK II Aug 15
>   2016
>  [88286.584128] task: ffff80097597c200 task.stack: ffff8009768b0000
>  [88286.589990] PC is at __queue_work+0x29c/0x3b8
>  [88286.594303] LR is at __queue_work+0x104/0x3b8
>  [88286.598614] pc : [<ffff0000080d8c7c>] lr : [<ffff0000080d8ae4>] pstate: a00001c5
>  [88286.605934] sp : ffff8009768b3aa0
>  [88286.609212] x29: ffff8009768b3aa0 x28: ffff80097ff3da00
>  [88286.614477] x27: ffff80097ff89c00 x26: ffff8009751b0e00
>  [88286.619741] x25: ffff000008c9f000 x24: 0000000000000003
>  [88286.625004] x23: 0000000000000040 x22: ffff000008d3dab8
>  [88286.630268] x21: ffff800977804400 x20: 0000000000000007
>  [88286.635532] x19: ffff000008c54000 x18: 0000fffff9185160
>  [88286.640795] x17: 0000ffffb33d9a38 x16: ffff000008088270
>  [88286.646059] x15: 0000ffffb345b590 x14: 0000000000000000
>  [88286.651322] x13: 0000000000000004 x12: 0000000000000040
>  [88286.656586] x11: 0000000000000068 x10: 0000000000000000
>  [88286.661849] x9 : ffff800977400028 x8 : 0000000000000000
>  [88286.667113] x7 : 0000000000000000 x6 : ffff0000080d8ae4
>  [88286.672376] x5 : 0000000000000000 x4 : 0000000000000080
>  [88286.677639] x3 : 0000000000000000 x2 : 0000000000000000
>  [88286.682903] x1 : 0000000000000000 x0 : ffff8009751b0e08
>  [88286.688166]
>  [88286.689638] ---[ end trace 31633f18fd33d4cb ]---
>  [88286.694206] Call trace:
>  [88286.696627] Exception stack(0xffff8009768b38d0 to 0xffff8009768b3a00)
>  [88286.703004] 38c0:                                   ffff000008c54000 0001000000000000
>  [88286.710757] 38e0: ffff8009768b3aa0 ffff0000080d8c7c ffff8009768b3b50 ffff80097ff8a5b0
>  [88286.718511] 3900: 0000800977325000 0000000000000000 0000000000000040 ffff80097ffc6180
>  [88286.726264] 3920: ffff8009768b3940 ffff0000088a8694 ffff80097ffc5800 0000000000000000
>  [88286.734017] 3940: ffff8009768b3960 ffff0000081919c0 ffff80097ffc5280 0000000000000001
>  [88286.741771] 3960: ffff8009768b3a50 ffff00000819206c ffff8009751b0e08 0000000000000000
>  [88286.749523] 3980: 0000000000000000 0000000000000000 0000000000000080 0000000000000000
>  [88286.757277] 39a0: ffff0000080d8ae4 0000000000000000 0000000000000000 ffff800977400028
>  [88286.765029] 39c0: 0000000000000000 0000000000000068 0000000000000040 0000000000000004
>  [88286.772783] 39e0: 0000000000000000 0000ffffb345b590 ffff000008088270 0000ffffb33d9a38
>  [88286.780537] [<ffff0000080d8c7c>] __queue_work+0x29c/0x3b8
>  [88286.785883] [<ffff0000080d8df8>] queue_work_on+0x60/0x78
>  [88286.791146] [<ffff000008764c68>] etm_setup_aux+0x178/0x238
>  [88286.796578] [<ffff000008183600>] rb_alloc_aux+0x228/0x310
>  [88286.801925] [<ffff00000817e564>] perf_mmap+0x404/0x5a8
>  [88286.807015] [<ffff0000081c60cc>] mmap_region+0x394/0x5c0
>  [88286.812276] [<ffff0000081c654c>] do_mmap+0x254/0x388
>  [88286.817191] [<ffff0000081a989c>] vm_mmap_pgoff+0xbc/0xe0
>  [88286.822452] [<ffff0000081c3ffc>] SyS_mmap_pgoff+0xac/0x228
>  [88286.827884] [<ffff000008088288>] sys_mmap+0x18/0x28
>  [88286.832714] [<ffff000008082f30>] el0_svc_naked+0x24/0x28
> 
> The patch makes sure that the event_data->work is initialised
> properly before we could possibly use it.
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Tested-by: Mike Leach <mike.leach@linaro.org>
> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

[Reported-and-]Tested-by: Kim Phillips <kim.phillips@arm.com>

Kim

[PATCH 04/17] coresight: tmc: minor fix for output log

[Mathieu Poirier]

From: Leo Yan <leo.yan@linaro.org>

In current code the output logs are not well symmetric for sink and link
enabling and disabling. This patch is to fix that so can output paired
logs.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/hwtracing/coresight/coresight-tmc-etf.c | 25 +++++++++++++++++--------
 1 file changed, 17 insertions(+), 8 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index aec61a6d5c63..e3b9fb82eb8d 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -166,9 +166,6 @@ static int tmc_enable_etf_sink_sysfs(struct coresight_device *csdev)
 	if (!used)
 		kfree(buf);
 
-	if (!ret)
-		dev_info(drvdata->dev, "TMC-ETB/ETF enabled\n");
-
 	return ret;
 }
 
@@ -204,15 +201,27 @@ static int tmc_enable_etf_sink_perf(struct coresight_device *csdev)
 
 static int tmc_enable_etf_sink(struct coresight_device *csdev, u32 mode)
 {
+	int ret;
+	struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
 	switch (mode) {
 	case CS_MODE_SYSFS:
-		return tmc_enable_etf_sink_sysfs(csdev);
+		ret = tmc_enable_etf_sink_sysfs(csdev);
+		break;
 	case CS_MODE_PERF:
-		return tmc_enable_etf_sink_perf(csdev);
+		ret = tmc_enable_etf_sink_perf(csdev);
+		break;
+	/* We shouldn't be here */
+	default:
+		ret = -EINVAL;
+		break;
 	}
 
-	/* We shouldn't be here */
-	return -EINVAL;
+	if (ret)
+		return ret;
+
+	dev_info(drvdata->dev, "TMC-ETB/ETF enabled\n");
+	return 0;
 }
 
 static void tmc_disable_etf_sink(struct coresight_device *csdev)
@@ -273,7 +282,7 @@ static void tmc_disable_etf_link(struct coresight_device *csdev,
 	drvdata->mode = CS_MODE_DISABLED;
 	spin_unlock_irqrestore(&drvdata->spinlock, flags);
 
-	dev_info(drvdata->dev, "TMC disabled\n");
+	dev_info(drvdata->dev, "TMC-ETF disabled\n");
 }
 
 static void *tmc_alloc_etf_buffer(struct coresight_device *csdev, int cpu,
-- 
2.7.4

[PATCH 05/17] coresight: use const for device_node structures

[Mathieu Poirier]

From: Leo Yan <leo.yan@linaro.org>

Almost low level functions from open firmware have used const to
qualify device_node structures, so add const for device_node
parameters in of_coresight related functions.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/hwtracing/coresight/of_coresight.c | 7 ++++---
 include/linux/coresight.h                  | 7 ++++---
 2 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/hwtracing/coresight/of_coresight.c b/drivers/hwtracing/coresight/of_coresight.c
index 09142e99e915..2749853b9010 100644
--- a/drivers/hwtracing/coresight/of_coresight.c
+++ b/drivers/hwtracing/coresight/of_coresight.c
@@ -52,7 +52,7 @@ of_coresight_get_endpoint_device(struct device_node *endpoint)
 			       endpoint, of_dev_node_match);
 }
 
-static void of_coresight_get_ports(struct device_node *node,
+static void of_coresight_get_ports(const struct device_node *node,
 				   int *nr_inport, int *nr_outport)
 {
 	struct device_node *ep = NULL;
@@ -101,8 +101,9 @@ static int of_coresight_alloc_memory(struct device *dev,
 	return 0;
 }
 
-struct coresight_platform_data *of_get_coresight_platform_data(
-				struct device *dev, struct device_node *node)
+struct coresight_platform_data *
+of_get_coresight_platform_data(struct device *dev,
+			       const struct device_node *node)
 {
 	int i = 0, ret = 0, cpu;
 	struct coresight_platform_data *pdata;
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index 035c16c9a505..bf0aa50880be 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -263,11 +263,12 @@ static inline int coresight_timeout(void __iomem *addr, u32 offset,
 #endif
 
 #ifdef CONFIG_OF
-extern struct coresight_platform_data *of_get_coresight_platform_data(
-				struct device *dev, struct device_node *node);
+extern struct coresight_platform_data *
+of_get_coresight_platform_data(struct device *dev,
+			       const struct device_node *node);
 #else
 static inline struct coresight_platform_data *of_get_coresight_platform_data(
-	struct device *dev, struct device_node *node) { return NULL; }
+	struct device *dev, const struct device_node *node) { return NULL; }
 #endif
 
 #ifdef CONFIG_PID_NS
-- 
2.7.4

[PATCH 06/17] coresight: etb10: Delete an error message for a failed memory allocation in etb_probe()

[Mathieu Poirier]

From: Markus Elfring <elfring@users.sourceforge.net>

Omit an extra message for a memory allocation failure in this function.

This issue was detected by using the Coccinelle software.

Link: http://events.linuxfoundation.org/sites/events/files/slides/LCJ16-Refactor_Strings-WSang_0.pdf
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/hwtracing/coresight/coresight-etb10.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c
index 979ea6ec7902..837aebf22c45 100644
--- a/drivers/hwtracing/coresight/coresight-etb10.c
+++ b/drivers/hwtracing/coresight/coresight-etb10.c
@@ -675,11 +675,8 @@ static int etb_probe(struct amba_device *adev, const struct amba_id *id)
 
 	drvdata->buf = devm_kzalloc(dev,
 				    drvdata->buffer_depth * 4, GFP_KERNEL);
-	if (!drvdata->buf) {
-		dev_err(dev, "Failed to allocate %u bytes for buffer data\n",
-			drvdata->buffer_depth * 4);
+	if (!drvdata->buf)
 		return -ENOMEM;
-	}
 
 	desc.type = CORESIGHT_DEV_TYPE_SINK;
 	desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
-- 
2.7.4

[PATCH 07/17] coresight: etb10: Fix a typo in a comment line

[Mathieu Poirier]

From: Markus Elfring <elfring@users.sourceforge.net>

Delete a character in this description for a condition check.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/hwtracing/coresight/coresight-etb10.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c
index 837aebf22c45..d5b96423e1a5 100644
--- a/drivers/hwtracing/coresight/coresight-etb10.c
+++ b/drivers/hwtracing/coresight/coresight-etb10.c
@@ -375,7 +375,7 @@ static void etb_update_buffer(struct coresight_device *csdev,
 
 	/*
 	 * Entries should be aligned to the frame size.  If they are not
-	 * go back to the last alignement point to give decoding tools a
+	 * go back to the last alignment point to give decoding tools a
 	 * chance to fix things.
 	 */
 	if (write_ptr % ETB_FRAME_SIZE_WORDS) {
-- 
2.7.4

[PATCH 08/17] coresight: tmc: Configure DMA mask appropriately

[Mathieu Poirier]

From: Robin Murphy <robin.murphy@arm.com>

Before making any DMA API calls, the ETR driver should really be setting
its masks to ensure that DMA is possible. Especially since it can
address more than the 32-bit default mask set by the AMBA bus code.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Tested-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/hwtracing/coresight/coresight-tmc.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index d8517d2a968c..864488793f09 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -362,6 +362,13 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
 		desc.type = CORESIGHT_DEV_TYPE_SINK;
 		desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
 		desc.ops = &tmc_etr_cs_ops;
+		/*
+		 * ETR configuration uses a 40-bit AXI master in place of
+		 * the embedded SRAM of ETB/ETF.
+		 */
+		ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
+		if (ret)
+			goto out;
 	} else {
 		desc.type = CORESIGHT_DEV_TYPE_LINKSINK;
 		desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
-- 
2.7.4

[PATCH 09/17] coresight: bindings for CPU debug module

[Mathieu Poirier]

From: Leo Yan <leo.yan@linaro.org>

According to ARMv8 architecture reference manual (ARM DDI 0487A.k)
Chapter 'Part H: External debug', the CPU can integrate debug module
and it can support self-hosted debug and external debug. Especially
for supporting self-hosted debug, this means the program can access
the debug module from mmio region; and usually the mmio region is
integrated with coresight.

So add document for binding debug component, includes binding to APB
clock; and also need specify the CPU node which the debug module is
dedicated to specific CPU.

Suggested-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 .../bindings/arm/coresight-cpu-debug.txt           | 49 ++++++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt

diff --git a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
new file mode 100644
index 000000000000..298291211ea4
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
@@ -0,0 +1,49 @@
+* CoreSight CPU Debug Component:
+
+CoreSight CPU debug component are compliant with the ARMv8 architecture
+reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The
+external debug module is mainly used for two modes: self-hosted debug and
+external debug, and it can be accessed from mmio region from Coresight
+and eventually the debug module connects with CPU for debugging. And the
+debug module provides sample-based profiling extension, which can be used
+to sample CPU program counter, secure state and exception level, etc;
+usually every CPU has one dedicated debug module to be connected.
+
+Required properties:
+
+- compatible : should be "arm,coresight-cpu-debug"; supplemented with
+               "arm,primecell" since this driver is using the AMBA bus
+	       interface.
+
+- reg : physical base address and length of the register set.
+
+- clocks : the clock associated to this component.
+
+- clock-names : the name of the clock referenced by the code. Since we are
+                using the AMBA framework, the name of the clock providing
+		the interconnect should be "apb_pclk" and the clock is
+		mandatory. The interface between the debug logic and the
+		processor core is clocked by the internal CPU clock, so it
+		is enabled with CPU clock by default.
+
+- cpu : the CPU phandle the debug module is affined to. When omitted
+	the module is considered to belong to CPU0.
+
+Optional properties:
+
+- power-domains: a phandle to the debug power domain. We use "power-domains"
+                 binding to turn on the debug logic if it has own dedicated
+		 power domain and if necessary to use "cpuidle.off=1" or
+		 "nohlt" in the kernel command line or sysfs node to
+		 constrain idle states to ensure registers in the CPU power
+		 domain are accessible.
+
+Example:
+
+	debug at f6590000 {
+		compatible = "arm,coresight-cpu-debug","arm,primecell";
+		reg = <0 0xf6590000 0 0x1000>;
+		clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+		clock-names = "apb_pclk";
+		cpu = <&cpu0>;
+	};
-- 
2.7.4

[PATCH 10/17] doc: Add documentation for Coresight CPU debug

[Mathieu Poirier]

From: Leo Yan <leo.yan@linaro.org>

Add detailed documentation for Coresight CPU debug driver, which
contains the info for driver implementation, Mike Leach excellent
summary for "clock and power domain". At the end some examples on how
to enable the debugging functionality are provided.

Suggested-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 Documentation/trace/coresight-cpu-debug.txt | 175 ++++++++++++++++++++++++++++
 1 file changed, 175 insertions(+)
 create mode 100644 Documentation/trace/coresight-cpu-debug.txt

diff --git a/Documentation/trace/coresight-cpu-debug.txt b/Documentation/trace/coresight-cpu-debug.txt
new file mode 100644
index 000000000000..b3da1f90b861
--- /dev/null
+++ b/Documentation/trace/coresight-cpu-debug.txt
@@ -0,0 +1,175 @@
+		Coresight CPU Debug Module
+		==========================
+
+   Author:   Leo Yan <leo.yan@linaro.org>
+   Date:     April 5th, 2017
+
+Introduction
+------------
+
+Coresight CPU debug module is defined in ARMv8-a architecture reference manual
+(ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate
+debug module and it is mainly used for two modes: self-hosted debug and
+external debug. Usually the external debug mode is well known as the external
+debugger connects with SoC from JTAG port; on the other hand the program can
+explore debugging method which rely on self-hosted debug mode, this document
+is to focus on this part.
+
+The debug module provides sample-based profiling extension, which can be used
+to sample CPU program counter, secure state and exception level, etc; usually
+every CPU has one dedicated debug module to be connected. Based on self-hosted
+debug mechanism, Linux kernel can access these related registers from mmio
+region when the kernel panic happens. The callback notifier for kernel panic
+will dump related registers for every CPU; finally this is good for assistant
+analysis for panic.
+
+
+Implementation
+--------------
+
+- During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
+  registers to decide if sample-based profiling is implemented or not. On some
+  platforms this hardware feature is fully or partially implemented; and if
+  this feature is not supported then registration will fail.
+
+- At the time this documentation was written, the debug driver mainly relies on
+  information gathered by the kernel panic callback notifier from three
+  sampling registers: EDPCSR, EDVIDSR and EDCIDSR: from EDPCSR we can get
+  program counter; EDVIDSR has information for secure state, exception level,
+  bit width, etc; EDCIDSR is context ID value which contains the sampled value
+  of CONTEXTIDR_EL1.
+
+- The driver supports a CPU running in either AArch64 or AArch32 mode. The
+  registers naming convention is a bit different between them, AArch64 uses
+  'ED' for register prefix (ARM DDI 0487A.k, chapter H9.1) and AArch32 uses
+  'DBG' as prefix (ARM DDI 0487A.k, chapter G5.1). The driver is unified to
+  use AArch64 naming convention.
+
+- ARMv8-a (ARM DDI 0487A.k) and ARMv7-a (ARM DDI 0406C.b) have different
+  register bits definition. So the driver consolidates two difference:
+
+  If PCSROffset=0b0000, on ARMv8-a the feature of EDPCSR is not implemented;
+  but ARMv7-a defines "PCSR samples are offset by a value that depends on the
+  instruction set state". For ARMv7-a, the driver checks furthermore if CPU
+  runs with ARM or thumb instruction set and calibrate PCSR value, the
+  detailed description for offset is in ARMv7-a ARM (ARM DDI 0406C.b) chapter
+  C11.11.34 "DBGPCSR, Program Counter Sampling Register".
+
+  If PCSROffset=0b0010, ARMv8-a defines "EDPCSR implemented, and samples have
+  no offset applied and do not sample the instruction set state in AArch32
+  state". So on ARMv8 if EDDEVID1.PCSROffset is 0b0010 and the CPU operates
+  in AArch32 state, EDPCSR is not sampled; when the CPU operates in AArch64
+  state EDPCSR is sampled and no offset are applied.
+
+
+Clock and power domain
+----------------------
+
+Before accessing debug registers, we should ensure the clock and power domain
+have been enabled properly. In ARMv8-a ARM (ARM DDI 0487A.k) chapter 'H9.1
+Debug registers', the debug registers are spread into two domains: the debug
+domain and the CPU domain.
+
+                                +---------------+
+                                |               |
+                                |               |
+                     +----------+--+            |
+        dbg_clock -->|          |**|            |<-- cpu_clock
+                     |    Debug |**|   CPU      |
+ dbg_power_domain -->|          |**|            |<-- cpu_power_domain
+                     +----------+--+            |
+                                |               |
+                                |               |
+                                +---------------+
+
+For debug domain, the user uses DT binding "clocks" and "power-domains" to
+specify the corresponding clock source and power supply for the debug logic.
+The driver calls the pm_runtime_{put|get} operations as needed to handle the
+debug power domain.
+
+For CPU domain, the different SoC designs have different power management
+schemes and finally this heavily impacts external debug module. So we can
+divide into below cases:
+
+- On systems with a sane power controller which can behave correctly with
+  respect to CPU power domain, the CPU power domain can be controlled by
+  register EDPRCR in driver. The driver firstly writes bit EDPRCR.COREPURQ
+  to power up the CPU, and then writes bit EDPRCR.CORENPDRQ for emulation
+  of CPU power down. As result, this can ensure the CPU power domain is
+  powered on properly during the period when access debug related registers;
+
+- Some designs will power down an entire cluster if all CPUs on the cluster
+  are powered down - including the parts of the debug registers that should
+  remain powered in the debug power domain. The bits in EDPRCR are not
+  respected in these cases, so these designs do not support debug over
+  power down in the way that the CoreSight / Debug designers anticipated.
+  This means that even checking EDPRSR has the potential to cause a bus hang
+  if the target register is unpowered.
+
+  In this case, accessing to the debug registers while they are not powered
+  is a recipe for disaster; so we need preventing CPU low power states at boot
+  time or when user enable module at the run time. Please see chapter
+  "How to use the module" for detailed usage info for this.
+
+
+Device Tree Bindings
+--------------------
+
+See Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt for details.
+
+
+How to use the module
+---------------------
+
+If you want to enable debugging functionality@boot time, you can add
+"coresight_cpu_debug.enable=1" to the kernel command line parameter.
+
+The driver also can work as module, so can enable the debugging when insmod
+module:
+# insmod coresight_cpu_debug.ko debug=1
+
+When boot time or insmod module you have not enabled the debugging, the driver
+uses the debugfs file system to provide a knob to dynamically enable or disable
+debugging:
+
+To enable it, write a '1' into /sys/kernel/debug/coresight_cpu_debug/enable:
+# echo 1 > /sys/kernel/debug/coresight_cpu_debug/enable
+
+To disable it, write a '0' into /sys/kernel/debug/coresight_cpu_debug/enable:
+# echo 0 > /sys/kernel/debug/coresight_cpu_debug/enable
+
+As explained in chapter "Clock and power domain", if you are working on one
+platform which has idle states to power off debug logic and the power
+controller cannot work well for the request from EDPRCR, then you should
+firstly constraint CPU idle states before enable CPU debugging feature; so can
+ensure the accessing to debug logic.
+
+If you want to limit idle states at boot time, you can use "nohlt" or
+"cpuidle.off=1" in the kernel command line.
+
+At the runtime you can disable idle states with below methods:
+
+Set latency request to /dev/cpu_dma_latency to disable all CPUs specific idle
+states (if latency = 0uS then disable all idle states):
+# echo "what_ever_latency_you_need_in_uS" > /dev/cpu_dma_latency
+
+Disable specific CPU's specific idle state:
+# echo 1 > /sys/devices/system/cpu/cpu$cpu/cpuidle/state$state/disable
+
+
+Output format
+-------------
+
+Here is an example of the debugging output format:
+
+ARM external debug module:
+coresight-cpu-debug 850000.debug: CPU[0]:
+coresight-cpu-debug 850000.debug:  EDPRSR:  00000001 (Power:On DLK:Unlock)
+coresight-cpu-debug 850000.debug:  EDPCSR:  [<ffff00000808e9bc>] handle_IPI+0x174/0x1d8
+coresight-cpu-debug 850000.debug:  EDCIDSR: 00000000
+coresight-cpu-debug 850000.debug:  EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
+coresight-cpu-debug 852000.debug: CPU[1]:
+coresight-cpu-debug 852000.debug:  EDPRSR:  00000001 (Power:On DLK:Unlock)
+coresight-cpu-debug 852000.debug:  EDPCSR:  [<ffff0000087fab34>] debug_notifier_call+0x23c/0x358
+coresight-cpu-debug 852000.debug:  EDCIDSR: 00000000
+coresight-cpu-debug 852000.debug:  EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
-- 
2.7.4

[PATCH 11/17] doc: Add coresight_cpu_debug.enable to kernel-parameters.txt

[Mathieu Poirier]

From: Leo Yan <leo.yan@linaro.org>

Add coresight_cpu_debug.enable to kernel-parameters.txt, this flag is
used to enable/disable the CPU sampling based debugging.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 Documentation/admin-guide/kernel-parameters.txt | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 15f79c27748d..ff67ad7d2c55 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -649,6 +649,13 @@
 			/proc/<pid>/coredump_filter.
 			See also Documentation/filesystems/proc.txt.
 
+	coresight_cpu_debug.enable
+			[ARM,ARM64]
+			Format: <bool>
+			Enable/disable the CPU sampling based debugging.
+			0: default value, disable debugging
+			1: enable debugging at boot time
+
 	cpuidle.off=1	[CPU_IDLE]
 			disable the cpuidle sub-system
 
-- 
2.7.4

[PATCH 12/17] MAINTAINERS: update file entries for Coresight subsystem

[Mathieu Poirier]

From: Leo Yan <leo.yan@linaro.org>

Update document file entries for Coresight debug module.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 MAINTAINERS | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index f7d568b8f133..d443258e3283 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1208,7 +1208,9 @@ L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
 S:	Maintained
 F:	drivers/hwtracing/coresight/*
 F:	Documentation/trace/coresight.txt
+F:	Documentation/trace/coresight-cpu-debug.txt
 F:	Documentation/devicetree/bindings/arm/coresight.txt
+F:	Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
 F:	Documentation/ABI/testing/sysfs-bus-coresight-devices-*
 F:	tools/perf/arch/arm/util/pmu.c
 F:	tools/perf/arch/arm/util/auxtrace.c
-- 
2.7.4

[PATCH 13/17] coresight: of_get_coresight_platform_data: Add missing of_node_put

[Mathieu Poirier]

From: Suzuki K Poulose <suzuki.poulose@arm.com>

The of_get_coresight_platform_data iterates over the possible CPU nodes
to find a given cpu phandle. However it does not drop the reference
to the node pointer returned by the of_get_coresight_platform_data.

This patch also introduces another minor fix is to use
of_cpu_device_node_get() to replace of_get_cpu_node().

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
[Leo: minor tweaks for of_get_coresight_platform_data]
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/hwtracing/coresight/of_coresight.c | 17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/drivers/hwtracing/coresight/of_coresight.c b/drivers/hwtracing/coresight/of_coresight.c
index 2749853b9010..225b2dd5970c 100644
--- a/drivers/hwtracing/coresight/of_coresight.c
+++ b/drivers/hwtracing/coresight/of_coresight.c
@@ -109,7 +109,8 @@ of_get_coresight_platform_data(struct device *dev,
 	struct coresight_platform_data *pdata;
 	struct of_endpoint endpoint, rendpoint;
 	struct device *rdev;
-	struct device_node *dn;
+	bool found;
+	struct device_node *dn, *np;
 	struct device_node *ep = NULL;
 	struct device_node *rparent = NULL;
 	struct device_node *rport = NULL;
@@ -176,17 +177,19 @@ of_get_coresight_platform_data(struct device *dev,
 		} while (ep);
 	}
 
-	/* Affinity defaults to CPU0 */
-	pdata->cpu = 0;
 	dn = of_parse_phandle(node, "cpu", 0);
-	for (cpu = 0; dn && cpu < nr_cpu_ids; cpu++) {
-		if (dn == of_get_cpu_node(cpu, NULL)) {
-			pdata->cpu = cpu;
+	for_each_possible_cpu(cpu) {
+		np = of_cpu_device_node_get(cpu);
+		found = (dn == np);
+		of_node_put(np);
+		if (found)
 			break;
-		}
 	}
 	of_node_put(dn);
 
+	/* Affinity to CPU0 if no cpu nodes are found */
+	pdata->cpu = found ? cpu : 0;
+
 	return pdata;
 }
 EXPORT_SYMBOL_GPL(of_get_coresight_platform_data);
-- 
2.7.4

[PATCH 14/17] coresight: refactor with function of_coresight_get_cpu

[Mathieu Poirier]

From: Leo Yan <leo.yan@linaro.org>

This is refactor to add function of_coresight_get_cpu(), so it's used to
retrieve CPU id for coresight component. Finally can use it as a common
function for multiple places.

Suggested-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/hwtracing/coresight/of_coresight.c | 43 +++++++++++++++++++-----------
 include/linux/coresight.h                  |  3 +++
 2 files changed, 31 insertions(+), 15 deletions(-)

diff --git a/drivers/hwtracing/coresight/of_coresight.c b/drivers/hwtracing/coresight/of_coresight.c
index 225b2dd5970c..a18794128bf8 100644
--- a/drivers/hwtracing/coresight/of_coresight.c
+++ b/drivers/hwtracing/coresight/of_coresight.c
@@ -101,16 +101,40 @@ static int of_coresight_alloc_memory(struct device *dev,
 	return 0;
 }
 
+int of_coresight_get_cpu(const struct device_node *node)
+{
+	int cpu;
+	bool found;
+	struct device_node *dn, *np;
+
+	dn = of_parse_phandle(node, "cpu", 0);
+
+	/* Affinity defaults to CPU0 */
+	if (!dn)
+		return 0;
+
+	for_each_possible_cpu(cpu) {
+		np = of_cpu_device_node_get(cpu);
+		found = (dn == np);
+		of_node_put(np);
+		if (found)
+			break;
+	}
+	of_node_put(dn);
+
+	/* Affinity to CPU0 if no cpu nodes are found */
+	return found ? cpu : 0;
+}
+EXPORT_SYMBOL_GPL(of_coresight_get_cpu);
+
 struct coresight_platform_data *
 of_get_coresight_platform_data(struct device *dev,
 			       const struct device_node *node)
 {
-	int i = 0, ret = 0, cpu;
+	int i = 0, ret = 0;
 	struct coresight_platform_data *pdata;
 	struct of_endpoint endpoint, rendpoint;
 	struct device *rdev;
-	bool found;
-	struct device_node *dn, *np;
 	struct device_node *ep = NULL;
 	struct device_node *rparent = NULL;
 	struct device_node *rport = NULL;
@@ -177,18 +201,7 @@ of_get_coresight_platform_data(struct device *dev,
 		} while (ep);
 	}
 
-	dn = of_parse_phandle(node, "cpu", 0);
-	for_each_possible_cpu(cpu) {
-		np = of_cpu_device_node_get(cpu);
-		found = (dn == np);
-		of_node_put(np);
-		if (found)
-			break;
-	}
-	of_node_put(dn);
-
-	/* Affinity to CPU0 if no cpu nodes are found */
-	pdata->cpu = found ? cpu : 0;
+	pdata->cpu = of_coresight_get_cpu(node);
 
 	return pdata;
 }
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index bf0aa50880be..d950dad5056a 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -263,10 +263,13 @@ static inline int coresight_timeout(void __iomem *addr, u32 offset,
 #endif
 
 #ifdef CONFIG_OF
+extern int of_coresight_get_cpu(const struct device_node *node);
 extern struct coresight_platform_data *
 of_get_coresight_platform_data(struct device *dev,
 			       const struct device_node *node);
 #else
+static inline int of_coresight_get_cpu(const struct device_node *node)
+{ return 0; }
 static inline struct coresight_platform_data *of_get_coresight_platform_data(
 	struct device *dev, const struct device_node *node) { return NULL; }
 #endif
-- 
2.7.4

[PATCH 15/17] coresight: add support for CPU debug module

[Mathieu Poirier]

From: Leo Yan <leo.yan@linaro.org>

Coresight includes debug module and usually the module connects with CPU
debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has
description for related info in "Part H: External Debug".

Chapter H7 "The Sample-based Profiling Extension" introduces several
sampling registers, e.g. we can check program counter value with
combined CPU exception level, secure state, etc. So this is helpful for
analysis CPU lockup scenarios, e.g. if one CPU has run into infinite
loop with IRQ disabled. In this case the CPU cannot switch context and
handle any interrupt (including IPIs), as the result it cannot handle
SMP call for stack dump.

This patch is to enable coresight debug module, so firstly this driver
is to bind apb clock for debug module and this is to ensure the debug
module can be accessed from program or external debugger. And the driver
uses sample-based registers for debug purpose, e.g. when system triggers
panic, the driver will dump program counter and combined context
registers (EDCIDSR, EDVIDSR); by parsing context registers so can
quickly get to know CPU secure state, exception level, etc.

Some of the debug module registers are located in CPU power domain, so
this requires the CPU power domain stays on when access related debug
registers, but the power management for CPU power domain is quite
dependent on SoC integration for power management. For the platforms
which with sane power controller implementations, this driver follows
the method to set EDPRCR to try to pull the CPU out of low power state
and then set 'no power down request' bit so the CPU has no chance to
lose power.

If the SoC has not followed up this design well for power management
controller, the user should use the command line parameter or sysfs
to constrain all or partial idle states to ensure the CPU power
domain is enabled and access coresight CPU debug component safely.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/hwtracing/coresight/Kconfig               |  14 +
 drivers/hwtracing/coresight/Makefile              |   1 +
 drivers/hwtracing/coresight/coresight-cpu-debug.c | 700 ++++++++++++++++++++++
 3 files changed, 715 insertions(+)
 create mode 100644 drivers/hwtracing/coresight/coresight-cpu-debug.c

diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
index 130cb2114059..8d55d6d79015 100644
--- a/drivers/hwtracing/coresight/Kconfig
+++ b/drivers/hwtracing/coresight/Kconfig
@@ -89,4 +89,18 @@ config CORESIGHT_STM
 	  logging useful software events or data coming from various entities
 	  in the system, possibly running different OSs
 
+config CORESIGHT_CPU_DEBUG
+	tristate "CoreSight CPU Debug driver"
+	depends on ARM || ARM64
+	depends on DEBUG_FS
+	help
+	  This driver provides support for coresight debugging module. This
+	  is primarily used to dump sample-based profiling registers when
+	  system triggers panic, the driver will parse context registers so
+	  can quickly get to know program counter (PC), secure state,
+	  exception level, etc. Before use debugging functionality, platform
+	  needs to ensure the clock domain and power domain are enabled
+	  properly, please refer Documentation/trace/coresight-cpu-debug.txt
+	  for detailed description and the example for usage.
+
 endif
diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
index af480d9c1441..433d59025eb6 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -16,3 +16,4 @@ obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o \
 					coresight-etm4x-sysfs.o
 obj-$(CONFIG_CORESIGHT_QCOM_REPLICATOR) += coresight-replicator-qcom.o
 obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
+obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
diff --git a/drivers/hwtracing/coresight/coresight-cpu-debug.c b/drivers/hwtracing/coresight/coresight-cpu-debug.c
new file mode 100644
index 000000000000..64a77e00eaa6
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-cpu-debug.c
@@ -0,0 +1,700 @@
+/*
+ * Copyright (c) 2017 Linaro Limited. All rights reserved.
+ *
+ * Author: Leo Yan <leo.yan@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#include <linux/amba/bus.h>
+#include <linux/coresight.h>
+#include <linux/cpu.h>
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/pm_qos.h>
+#include <linux/slab.h>
+#include <linux/smp.h>
+#include <linux/types.h>
+#include <linux/uaccess.h>
+
+#include "coresight-priv.h"
+
+#define EDPCSR				0x0A0
+#define EDCIDSR				0x0A4
+#define EDVIDSR				0x0A8
+#define EDPCSR_HI			0x0AC
+#define EDOSLAR				0x300
+#define EDPRCR				0x310
+#define EDPRSR				0x314
+#define EDDEVID1			0xFC4
+#define EDDEVID				0xFC8
+
+#define EDPCSR_PROHIBITED		0xFFFFFFFF
+
+/* bits definition for EDPCSR */
+#define EDPCSR_THUMB			BIT(0)
+#define EDPCSR_ARM_INST_MASK		GENMASK(31, 2)
+#define EDPCSR_THUMB_INST_MASK		GENMASK(31, 1)
+
+/* bits definition for EDPRCR */
+#define EDPRCR_COREPURQ			BIT(3)
+#define EDPRCR_CORENPDRQ		BIT(0)
+
+/* bits definition for EDPRSR */
+#define EDPRSR_DLK			BIT(6)
+#define EDPRSR_PU			BIT(0)
+
+/* bits definition for EDVIDSR */
+#define EDVIDSR_NS			BIT(31)
+#define EDVIDSR_E2			BIT(30)
+#define EDVIDSR_E3			BIT(29)
+#define EDVIDSR_HV			BIT(28)
+#define EDVIDSR_VMID			GENMASK(7, 0)
+
+/*
+ * bits definition for EDDEVID1:PSCROffset
+ *
+ * NOTE: armv8 and armv7 have different definition for the register,
+ * so consolidate the bits definition as below:
+ *
+ * 0b0000 - Sample offset applies based on the instruction state, we
+ *          rely on EDDEVID to check if EDPCSR is implemented or not
+ * 0b0001 - No offset applies.
+ * 0b0010 - No offset applies, but do not use in AArch32 mode
+ *
+ */
+#define EDDEVID1_PCSR_OFFSET_MASK	GENMASK(3, 0)
+#define EDDEVID1_PCSR_OFFSET_INS_SET	(0x0)
+#define EDDEVID1_PCSR_NO_OFFSET_DIS_AARCH32	(0x2)
+
+/* bits definition for EDDEVID */
+#define EDDEVID_PCSAMPLE_MODE		GENMASK(3, 0)
+#define EDDEVID_IMPL_EDPCSR		(0x1)
+#define EDDEVID_IMPL_EDPCSR_EDCIDSR	(0x2)
+#define EDDEVID_IMPL_FULL		(0x3)
+
+#define DEBUG_WAIT_SLEEP		1000
+#define DEBUG_WAIT_TIMEOUT		32000
+
+struct debug_drvdata {
+	void __iomem	*base;
+	struct device	*dev;
+	int		cpu;
+
+	bool		edpcsr_present;
+	bool		edcidsr_present;
+	bool		edvidsr_present;
+	bool		pc_has_offset;
+
+	u32		edpcsr;
+	u32		edpcsr_hi;
+	u32		edprsr;
+	u32		edvidsr;
+	u32		edcidsr;
+};
+
+static DEFINE_MUTEX(debug_lock);
+static DEFINE_PER_CPU(struct debug_drvdata *, debug_drvdata);
+static int debug_count;
+static struct dentry *debug_debugfs_dir;
+
+static bool debug_enable;
+module_param_named(enable, debug_enable, bool, 0600);
+MODULE_PARM_DESC(enable, "Control to enable coresight CPU debug functionality");
+
+static void debug_os_unlock(struct debug_drvdata *drvdata)
+{
+	/* Unlocks the debug registers */
+	writel_relaxed(0x0, drvdata->base + EDOSLAR);
+
+	/* Make sure the registers are unlocked before accessing */
+	wmb();
+}
+
+/*
+ * According to ARM DDI 0487A.k, before access external debug
+ * registers should firstly check the access permission; if any
+ * below condition has been met then cannot access debug
+ * registers to avoid lockup issue:
+ *
+ * - CPU power domain is powered off;
+ * - The OS Double Lock is locked;
+ *
+ * By checking EDPRSR can get to know if meet these conditions.
+ */
+static bool debug_access_permitted(struct debug_drvdata *drvdata)
+{
+	/* CPU is powered off */
+	if (!(drvdata->edprsr & EDPRSR_PU))
+		return false;
+
+	/* The OS Double Lock is locked */
+	if (drvdata->edprsr & EDPRSR_DLK)
+		return false;
+
+	return true;
+}
+
+static void debug_force_cpu_powered_up(struct debug_drvdata *drvdata)
+{
+	u32 edprcr;
+
+try_again:
+
+	/*
+	 * Send request to power management controller and assert
+	 * DBGPWRUPREQ signal; if power management controller has
+	 * sane implementation, it should enable CPU power domain
+	 * in case CPU is in low power state.
+	 */
+	edprcr = readl_relaxed(drvdata->base + EDPRCR);
+	edprcr |= EDPRCR_COREPURQ;
+	writel_relaxed(edprcr, drvdata->base + EDPRCR);
+
+	/* Wait for CPU to be powered up (timeout~=32ms) */
+	if (readx_poll_timeout_atomic(readl_relaxed, drvdata->base + EDPRSR,
+			drvdata->edprsr, (drvdata->edprsr & EDPRSR_PU),
+			DEBUG_WAIT_SLEEP, DEBUG_WAIT_TIMEOUT)) {
+		/*
+		 * Unfortunately the CPU cannot be powered up, so return
+		 * back and later has no permission to access other
+		 * registers. For this case, should disable CPU low power
+		 * states to ensure CPU power domain is enabled!
+		 */
+		dev_err(drvdata->dev, "%s: power up request for CPU%d failed\n",
+			__func__, drvdata->cpu);
+		return;
+	}
+
+	/*
+	 * At this point the CPU is powered up, so set the no powerdown
+	 * request bit so we don't lose power and emulate power down.
+	 */
+	edprcr = readl_relaxed(drvdata->base + EDPRCR);
+	edprcr |= EDPRCR_COREPURQ | EDPRCR_CORENPDRQ;
+	writel_relaxed(edprcr, drvdata->base + EDPRCR);
+
+	drvdata->edprsr = readl_relaxed(drvdata->base + EDPRSR);
+
+	/* The core power domain got switched off on use, try again */
+	if (unlikely(!(drvdata->edprsr & EDPRSR_PU)))
+		goto try_again;
+}
+
+static void debug_read_regs(struct debug_drvdata *drvdata)
+{
+	u32 save_edprcr;
+
+	CS_UNLOCK(drvdata->base);
+
+	/* Unlock os lock */
+	debug_os_unlock(drvdata);
+
+	/* Save EDPRCR register */
+	save_edprcr = readl_relaxed(drvdata->base + EDPRCR);
+
+	/*
+	 * Ensure CPU power domain is enabled to let registers
+	 * are accessiable.
+	 */
+	debug_force_cpu_powered_up(drvdata);
+
+	if (!debug_access_permitted(drvdata))
+		goto out;
+
+	drvdata->edpcsr = readl_relaxed(drvdata->base + EDPCSR);
+
+	/*
+	 * As described in ARM DDI 0487A.k, if the processing
+	 * element (PE) is in debug state, or sample-based
+	 * profiling is prohibited, EDPCSR reads as 0xFFFFFFFF;
+	 * EDCIDSR, EDVIDSR and EDPCSR_HI registers also become
+	 * UNKNOWN state. So directly bail out for this case.
+	 */
+	if (drvdata->edpcsr == EDPCSR_PROHIBITED)
+		goto out;
+
+	/*
+	 * A read of the EDPCSR normally has the side-effect of
+	 * indirectly writing to EDCIDSR, EDVIDSR and EDPCSR_HI;
+	 * at this point it's safe to read value from them.
+	 */
+	if (IS_ENABLED(CONFIG_64BIT))
+		drvdata->edpcsr_hi = readl_relaxed(drvdata->base + EDPCSR_HI);
+
+	if (drvdata->edcidsr_present)
+		drvdata->edcidsr = readl_relaxed(drvdata->base + EDCIDSR);
+
+	if (drvdata->edvidsr_present)
+		drvdata->edvidsr = readl_relaxed(drvdata->base + EDVIDSR);
+
+out:
+	/* Restore EDPRCR register */
+	writel_relaxed(save_edprcr, drvdata->base + EDPRCR);
+
+	CS_LOCK(drvdata->base);
+}
+
+#ifdef CONFIG_64BIT
+static unsigned long debug_adjust_pc(struct debug_drvdata *drvdata)
+{
+	return (unsigned long)drvdata->edpcsr_hi << 32 |
+	       (unsigned long)drvdata->edpcsr;
+}
+#else
+static unsigned long debug_adjust_pc(struct debug_drvdata *drvdata)
+{
+	unsigned long arm_inst_offset = 0, thumb_inst_offset = 0;
+	unsigned long pc;
+
+	pc = (unsigned long)drvdata->edpcsr;
+
+	if (drvdata->pc_has_offset) {
+		arm_inst_offset = 8;
+		thumb_inst_offset = 4;
+	}
+
+	/* Handle thumb instruction */
+	if (pc & EDPCSR_THUMB) {
+		pc = (pc & EDPCSR_THUMB_INST_MASK) - thumb_inst_offset;
+		return pc;
+	}
+
+	/*
+	 * Handle arm instruction offset, if the arm instruction
+	 * is not 4 byte alignment then it's possible the case
+	 * for implementation defined; keep original value for this
+	 * case and print info for notice.
+	 */
+	if (pc & BIT(1))
+		dev_emerg(drvdata->dev,
+			  "Instruction offset is implementation defined\n");
+	else
+		pc = (pc & EDPCSR_ARM_INST_MASK) - arm_inst_offset;
+
+	return pc;
+}
+#endif
+
+static void debug_dump_regs(struct debug_drvdata *drvdata)
+{
+	struct device *dev = drvdata->dev;
+	unsigned long pc;
+
+	dev_emerg(dev, " EDPRSR:  %08x (Power:%s DLK:%s)\n",
+		  drvdata->edprsr,
+		  drvdata->edprsr & EDPRSR_PU ? "On" : "Off",
+		  drvdata->edprsr & EDPRSR_DLK ? "Lock" : "Unlock");
+
+	if (!debug_access_permitted(drvdata)) {
+		dev_emerg(dev, "No permission to access debug registers!\n");
+		return;
+	}
+
+	if (drvdata->edpcsr == EDPCSR_PROHIBITED) {
+		dev_emerg(dev, "CPU is in Debug state or profiling is prohibited!\n");
+		return;
+	}
+
+	pc = debug_adjust_pc(drvdata);
+	dev_emerg(dev, " EDPCSR:  [<%p>] %pS\n", (void *)pc, (void *)pc);
+
+	if (drvdata->edcidsr_present)
+		dev_emerg(dev, " EDCIDSR: %08x\n", drvdata->edcidsr);
+
+	if (drvdata->edvidsr_present)
+		dev_emerg(dev, " EDVIDSR: %08x (State:%s Mode:%s Width:%dbits VMID:%x)\n",
+			  drvdata->edvidsr,
+			  drvdata->edvidsr & EDVIDSR_NS ?
+			  "Non-secure" : "Secure",
+			  drvdata->edvidsr & EDVIDSR_E3 ? "EL3" :
+				(drvdata->edvidsr & EDVIDSR_E2 ?
+				 "EL2" : "EL1/0"),
+			  drvdata->edvidsr & EDVIDSR_HV ? 64 : 32,
+			  drvdata->edvidsr & (u32)EDVIDSR_VMID);
+}
+
+static void debug_init_arch_data(void *info)
+{
+	struct debug_drvdata *drvdata = info;
+	u32 mode, pcsr_offset;
+	u32 eddevid, eddevid1;
+
+	CS_UNLOCK(drvdata->base);
+
+	/* Read device info */
+	eddevid  = readl_relaxed(drvdata->base + EDDEVID);
+	eddevid1 = readl_relaxed(drvdata->base + EDDEVID1);
+
+	CS_LOCK(drvdata->base);
+
+	/* Parse implementation feature */
+	mode = eddevid & EDDEVID_PCSAMPLE_MODE;
+	pcsr_offset = eddevid1 & EDDEVID1_PCSR_OFFSET_MASK;
+
+	drvdata->edpcsr_present  = false;
+	drvdata->edcidsr_present = false;
+	drvdata->edvidsr_present = false;
+	drvdata->pc_has_offset   = false;
+
+	switch (mode) {
+	case EDDEVID_IMPL_FULL:
+		drvdata->edvidsr_present = true;
+		/* Fall through */
+	case EDDEVID_IMPL_EDPCSR_EDCIDSR:
+		drvdata->edcidsr_present = true;
+		/* Fall through */
+	case EDDEVID_IMPL_EDPCSR:
+		/*
+		 * In ARM DDI 0487A.k, the EDDEVID1.PCSROffset is used to
+		 * define if has the offset for PC sampling value; if read
+		 * back EDDEVID1.PCSROffset == 0x2, then this means the debug
+		 * module does not sample the instruction set state when
+		 * armv8 CPU in AArch32 state.
+		 */
+		drvdata->edpcsr_present =
+			((IS_ENABLED(CONFIG_64BIT) && pcsr_offset != 0) ||
+			 (pcsr_offset != EDDEVID1_PCSR_NO_OFFSET_DIS_AARCH32));
+
+		drvdata->pc_has_offset =
+			(pcsr_offset == EDDEVID1_PCSR_OFFSET_INS_SET);
+		break;
+	default:
+		break;
+	}
+}
+
+/*
+ * Dump out information on panic.
+ */
+static int debug_notifier_call(struct notifier_block *self,
+			       unsigned long v, void *p)
+{
+	int cpu;
+	struct debug_drvdata *drvdata;
+
+	mutex_lock(&debug_lock);
+
+	/* Bail out if the functionality is disabled */
+	if (!debug_enable)
+		goto skip_dump;
+
+	pr_emerg("ARM external debug module:\n");
+
+	for_each_possible_cpu(cpu) {
+		drvdata = per_cpu(debug_drvdata, cpu);
+		if (!drvdata)
+			continue;
+
+		dev_emerg(drvdata->dev, "CPU[%d]:\n", drvdata->cpu);
+
+		debug_read_regs(drvdata);
+		debug_dump_regs(drvdata);
+	}
+
+skip_dump:
+	mutex_unlock(&debug_lock);
+	return 0;
+}
+
+static struct notifier_block debug_notifier = {
+	.notifier_call = debug_notifier_call,
+};
+
+static int debug_enable_func(void)
+{
+	struct debug_drvdata *drvdata;
+	int cpu, ret = 0;
+	cpumask_t mask;
+
+	/*
+	 * Use cpumask to track which debug power domains have
+	 * been powered on and use it to handle failure case.
+	 */
+	cpumask_clear(&mask);
+
+	for_each_possible_cpu(cpu) {
+		drvdata = per_cpu(debug_drvdata, cpu);
+		if (!drvdata)
+			continue;
+
+		ret = pm_runtime_get_sync(drvdata->dev);
+		if (ret < 0)
+			goto err;
+		else
+			cpumask_set_cpu(cpu, &mask);
+	}
+
+	return 0;
+
+err:
+	/*
+	 * If pm_runtime_get_sync() has failed, need rollback on
+	 * all the other CPUs that have been enabled before that.
+	 */
+	for_each_cpu(cpu, &mask) {
+		drvdata = per_cpu(debug_drvdata, cpu);
+		pm_runtime_put_noidle(drvdata->dev);
+	}
+
+	return ret;
+}
+
+static int debug_disable_func(void)
+{
+	struct debug_drvdata *drvdata;
+	int cpu, ret, err = 0;
+
+	/*
+	 * Disable debug power domains, records the error and keep
+	 * circling through all other CPUs when an error has been
+	 * encountered.
+	 */
+	for_each_possible_cpu(cpu) {
+		drvdata = per_cpu(debug_drvdata, cpu);
+		if (!drvdata)
+			continue;
+
+		ret = pm_runtime_put(drvdata->dev);
+		if (ret < 0)
+			err = ret;
+	}
+
+	return err;
+}
+
+static ssize_t debug_func_knob_write(struct file *f,
+		const char __user *buf, size_t count, loff_t *ppos)
+{
+	u8 val;
+	int ret;
+
+	ret = kstrtou8_from_user(buf, count, 2, &val);
+	if (ret)
+		return ret;
+
+	mutex_lock(&debug_lock);
+
+	if (val == debug_enable)
+		goto out;
+
+	if (val)
+		ret = debug_enable_func();
+	else
+		ret = debug_disable_func();
+
+	if (ret) {
+		pr_err("%s: unable to %s debug function: %d\n",
+		       __func__, val ? "enable" : "disable", ret);
+		goto err;
+	}
+
+	debug_enable = val;
+out:
+	ret = count;
+err:
+	mutex_unlock(&debug_lock);
+	return ret;
+}
+
+static ssize_t debug_func_knob_read(struct file *f,
+		char __user *ubuf, size_t count, loff_t *ppos)
+{
+	ssize_t ret;
+	char buf[3];
+
+	mutex_lock(&debug_lock);
+	snprintf(buf, sizeof(buf), "%d\n", debug_enable);
+	mutex_unlock(&debug_lock);
+
+	ret = simple_read_from_buffer(ubuf, count, ppos, buf, sizeof(buf));
+	return ret;
+}
+
+static const struct file_operations debug_func_knob_fops = {
+	.open	= simple_open,
+	.read	= debug_func_knob_read,
+	.write	= debug_func_knob_write,
+};
+
+static int debug_func_init(void)
+{
+	struct dentry *file;
+	int ret;
+
+	/* Create debugfs node */
+	debug_debugfs_dir = debugfs_create_dir("coresight_cpu_debug", NULL);
+	if (!debug_debugfs_dir) {
+		pr_err("%s: unable to create debugfs directory\n", __func__);
+		return -ENOMEM;
+	}
+
+	file = debugfs_create_file("enable", 0644, debug_debugfs_dir, NULL,
+				   &debug_func_knob_fops);
+	if (!file) {
+		pr_err("%s: unable to create enable knob file\n", __func__);
+		ret = -ENOMEM;
+		goto err;
+	}
+
+	/* Register function to be called for panic */
+	ret = atomic_notifier_chain_register(&panic_notifier_list,
+					     &debug_notifier);
+	if (ret) {
+		pr_err("%s: unable to register notifier: %d\n",
+		       __func__, ret);
+		goto err;
+	}
+
+	return 0;
+
+err:
+	debugfs_remove_recursive(debug_debugfs_dir);
+	return ret;
+}
+
+static void debug_func_exit(void)
+{
+	atomic_notifier_chain_unregister(&panic_notifier_list,
+					 &debug_notifier);
+	debugfs_remove_recursive(debug_debugfs_dir);
+}
+
+static int debug_probe(struct amba_device *adev, const struct amba_id *id)
+{
+	void __iomem *base;
+	struct device *dev = &adev->dev;
+	struct debug_drvdata *drvdata;
+	struct resource *res = &adev->res;
+	struct device_node *np = adev->dev.of_node;
+	int ret;
+
+	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
+	if (!drvdata)
+		return -ENOMEM;
+
+	drvdata->cpu = np ? of_coresight_get_cpu(np) : 0;
+	if (per_cpu(debug_drvdata, drvdata->cpu)) {
+		dev_err(dev, "CPU%d drvdata has already been initialized\n",
+			drvdata->cpu);
+		return -EBUSY;
+	}
+
+	drvdata->dev = &adev->dev;
+	amba_set_drvdata(adev, drvdata);
+
+	/* Validity for the resource is already checked by the AMBA core */
+	base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	drvdata->base = base;
+
+	get_online_cpus();
+	per_cpu(debug_drvdata, drvdata->cpu) = drvdata;
+	ret = smp_call_function_single(drvdata->cpu, debug_init_arch_data,
+				       drvdata, 1);
+	put_online_cpus();
+
+	if (ret) {
+		dev_err(dev, "CPU%d debug arch init failed\n", drvdata->cpu);
+		goto err;
+	}
+
+	if (!drvdata->edpcsr_present) {
+		dev_err(dev, "CPU%d sample-based profiling isn't implemented\n",
+			drvdata->cpu);
+		ret = -ENXIO;
+		goto err;
+	}
+
+	if (!debug_count++) {
+		ret = debug_func_init();
+		if (ret)
+			goto err_func_init;
+	}
+
+	mutex_lock(&debug_lock);
+	/* Turn off debug power domain if debugging is disabled */
+	if (!debug_enable)
+		pm_runtime_put(dev);
+	mutex_unlock(&debug_lock);
+
+	dev_info(dev, "Coresight debug-CPU%d initialized\n", drvdata->cpu);
+	return 0;
+
+err_func_init:
+	debug_count--;
+err:
+	per_cpu(debug_drvdata, drvdata->cpu) = NULL;
+	return ret;
+}
+
+static int debug_remove(struct amba_device *adev)
+{
+	struct device *dev = &adev->dev;
+	struct debug_drvdata *drvdata = amba_get_drvdata(adev);
+
+	per_cpu(debug_drvdata, drvdata->cpu) = NULL;
+
+	mutex_lock(&debug_lock);
+	/* Turn off debug power domain before rmmod the module */
+	if (debug_enable)
+		pm_runtime_put(dev);
+	mutex_unlock(&debug_lock);
+
+	if (!--debug_count)
+		debug_func_exit();
+
+	return 0;
+}
+
+static struct amba_id debug_ids[] = {
+	{       /* Debug for Cortex-A53 */
+		.id	= 0x000bbd03,
+		.mask	= 0x000fffff,
+	},
+	{       /* Debug for Cortex-A57 */
+		.id	= 0x000bbd07,
+		.mask	= 0x000fffff,
+	},
+	{       /* Debug for Cortex-A72 */
+		.id	= 0x000bbd08,
+		.mask	= 0x000fffff,
+	},
+	{ 0, 0 },
+};
+
+static struct amba_driver debug_driver = {
+	.drv = {
+		.name   = "coresight-cpu-debug",
+		.suppress_bind_attrs = true,
+	},
+	.probe		= debug_probe,
+	.remove		= debug_remove,
+	.id_table	= debug_ids,
+};
+
+module_amba_driver(debug_driver);
+
+MODULE_AUTHOR("Leo Yan <leo.yan@linaro.org>");
+MODULE_DESCRIPTION("ARM Coresight CPU Debug Driver");
+MODULE_LICENSE("GPL");
-- 
2.7.4

[PATCH 16/17] arm64: dts: hi6220: register debug module

[Mathieu Poirier]

From: Leo Yan <leo.yan@linaro.org>

Bind debug module driver for Hi6220.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Wei Xu <xuwei5@hisilicon.com>
---
 arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 64 +++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 1e5129b19280..21805b9786c7 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -916,5 +916,69 @@
 				};
 			};
 		};
+
+		debug at f6590000 {
+			compatible = "arm,coresight-cpu-debug","arm,primecell";
+			reg = <0 0xf6590000 0 0x1000>;
+			clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+			clock-names = "apb_pclk";
+			cpu = <&cpu0>;
+		};
+
+		debug at f6592000 {
+			compatible = "arm,coresight-cpu-debug","arm,primecell";
+			reg = <0 0xf6592000 0 0x1000>;
+			clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+			clock-names = "apb_pclk";
+			cpu = <&cpu1>;
+		};
+
+		debug at f6594000 {
+			compatible = "arm,coresight-cpu-debug","arm,primecell";
+			reg = <0 0xf6594000 0 0x1000>;
+			clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+			clock-names = "apb_pclk";
+			cpu = <&cpu2>;
+		};
+
+		debug at f6596000 {
+			compatible = "arm,coresight-cpu-debug","arm,primecell";
+			reg = <0 0xf6596000 0 0x1000>;
+			clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+			clock-names = "apb_pclk";
+			cpu = <&cpu3>;
+		};
+
+		debug at f65d0000 {
+			compatible = "arm,coresight-cpu-debug","arm,primecell";
+			reg = <0 0xf65d0000 0 0x1000>;
+			clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+			clock-names = "apb_pclk";
+			cpu = <&cpu4>;
+		};
+
+		debug at f65d2000 {
+			compatible = "arm,coresight-cpu-debug","arm,primecell";
+			reg = <0 0xf65d2000 0 0x1000>;
+			clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+			clock-names = "apb_pclk";
+			cpu = <&cpu5>;
+		};
+
+		debug at f65d4000 {
+			compatible = "arm,coresight-cpu-debug","arm,primecell";
+			reg = <0 0xf65d4000 0 0x1000>;
+			clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+			clock-names = "apb_pclk";
+			cpu = <&cpu6>;
+		};
+
+		debug at f65d6000 {
+			compatible = "arm,coresight-cpu-debug","arm,primecell";
+			reg = <0 0xf65d6000 0 0x1000>;
+			clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+			clock-names = "apb_pclk";
+			cpu = <&cpu7>;
+		};
 	};
 };
-- 
2.7.4

[PATCH 17/17] arm64: dts: qcom: msm8916: Add debug unit

[Mathieu Poirier]

From: Leo Yan <leo.yan@linaro.org>

Add debug unit on Qualcomm msm8916 based platforms, including the
DragonBoard 410c board.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Andy Gross <andy.gross@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index ab3093995ded..17691abea608 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -1116,6 +1116,38 @@
 			};
 		};
 
+		debug at 850000 {
+			compatible = "arm,coresight-cpu-debug","arm,primecell";
+			reg = <0x850000 0x1000>;
+			clocks = <&rpmcc RPM_QDSS_CLK>;
+			clock-names = "apb_pclk";
+			cpu = <&CPU0>;
+		};
+
+		debug at 852000 {
+			compatible = "arm,coresight-cpu-debug","arm,primecell";
+			reg = <0x852000 0x1000>;
+			clocks = <&rpmcc RPM_QDSS_CLK>;
+			clock-names = "apb_pclk";
+			cpu = <&CPU1>;
+		};
+
+		debug at 854000 {
+			compatible = "arm,coresight-cpu-debug","arm,primecell";
+			reg = <0x854000 0x1000>;
+			clocks = <&rpmcc RPM_QDSS_CLK>;
+			clock-names = "apb_pclk";
+			cpu = <&CPU2>;
+		};
+
+		debug at 856000 {
+			compatible = "arm,coresight-cpu-debug","arm,primecell";
+			reg = <0x856000 0x1000>;
+			clocks = <&rpmcc RPM_QDSS_CLK>;
+			clock-names = "apb_pclk";
+			cpu = <&CPU3>;
+		};
+
 		etm at 85c000 {
 			compatible = "arm,coresight-etm4x", "arm,primecell";
 			reg = <0x85c000 0x1000>;
-- 
2.7.4

[PATCH 00/17] coresight: next v4.12-rc4

[Kim Phillips]

On Mon,  5 Jun 2017 14:15:01 -0600
Mathieu Poirier <mathieu.poirier@linaro.org> wrote:

Hi Mathieu,

> Please consider for inclusion in the 4.13 cycle.  Of particular interest is
> patch 15/17, which adds a new driver under the CoreSight umbrella.

After applying the patchseries, the devices now have self-named
subdirectories under them:

$ find /sys/devices/ -name \*sink\*
/sys/devices/platform/20140000.etf/20140000.etf/enable_sink
/sys/devices/platform/20070000.etr/20070000.etr/enable_sink
/sys/devices/platform/20030000.tpiu/20030000.tpiu/enable_sink
/sys/devices/platform/20010000.etf/20010000.etf/enable_sink
$ 

Which doesn't match the coresight.txt usage documentation...

Also, do the current juno platforms not have CPU debug modules?  I'd
like to test the new driver.

Thanks,

Kim

[PATCH 00/17] coresight: next v4.12-rc4

[Leo Yan]

Hi Kim,

On Fri, Jun 09, 2017 at 05:53:39PM -0500, Kim Phillips wrote:
> On Mon,  5 Jun 2017 14:15:01 -0600
> Mathieu Poirier <mathieu.poirier@linaro.org> wrote:
> 
> Hi Mathieu,
> 
> > Please consider for inclusion in the 4.13 cycle.  Of particular interest is
> > patch 15/17, which adds a new driver under the CoreSight umbrella.
> 
> After applying the patchseries, the devices now have self-named
> subdirectories under them:
> 
> $ find /sys/devices/ -name \*sink\*
> /sys/devices/platform/20140000.etf/20140000.etf/enable_sink
> /sys/devices/platform/20070000.etr/20070000.etr/enable_sink
> /sys/devices/platform/20030000.tpiu/20030000.tpiu/enable_sink
> /sys/devices/platform/20010000.etf/20010000.etf/enable_sink
> $ 
> 
> Which doesn't match the coresight.txt usage documentation...

I am worry if my patches do some bad thing, so I did a quick test with
mainline kernel on Hikey, if without this patch series I still can see
self-named subdirectories in '/sys/devices/platform/':

root at linaro-developer:~# find /sys/devices/ -name \*sink\*
/sys/devices/platform/amba/f6404000.etr/f6404000.etr/enable_sink
/sys/devices/platform/amba/f6402000.etf/f6402000.etf/enable_sink

But if search '/sys/bus/coresight/devices/', we can get below info:
root at linaro-developer:~# ls /sys/bus/coresight/devices/*/*sink* -l
-rw-r--r-- 1 root root 4096 Nov 18 08:04 /sys/bus/coresight/devices/f6402000.etf/enable_sink
-rw-r--r-- 1 root root 4096 Nov 18 08:07 /sys/bus/coresight/devices/f6404000.etr/enable_sink

I checked coresight.txt and it uses folder
'/sys/bus/coresight/devices/' as example but not '/sys/devices/'.

> Also, do the current juno platforms not have CPU debug modules?  I'd
> like to test the new driver.

Suzuki's Juno patch has been picked from ARM tree:
http://archive.armlinux.org.uk/lurker/message/20170519.042557.c8b56c20.en.html

Thanks,
Leo Yan

[PATCH 00/17] coresight: next v4.12-rc4

[Kim Phillips]

On Mon, 12 Jun 2017 10:50:43 -0600
Mathieu Poirier <mathieu.poirier@linaro.org> wrote:

Hi Mathieu,

> On 9 June 2017 at 16:53, Kim Phillips <kim.phillips@arm.com> wrote:
> 
> > On Mon,  5 Jun 2017 14:15:01 -0600
> > Mathieu Poirier <mathieu.poirier@linaro.org> wrote:
> >
> > Hi Mathieu,
> >
> > > Please consider for inclusion in the 4.13 cycle.  Of particular interest
> > is
> > > patch 15/17, which adds a new driver under the CoreSight umbrella.
> >
> > After applying the patchseries, the devices now have self-named
> > subdirectories under them:
> >
> > $ find /sys/devices/ -name \*sink\*
> > /sys/devices/platform/20140000.etf/20140000.etf/enable_sink
> > /sys/devices/platform/20070000.etr/20070000.etr/enable_sink
> > /sys/devices/platform/20030000.tpiu/20030000.tpiu/enable_sink
> > /sys/devices/platform/20010000.etf/20010000.etf/enable_sink
> > $
> >
> 
> This is the expected behaviour.  CoreSight devices are found on the AMBA
> bus and like other AMBA devices they will show up under
> /sys/devices/platform/.

right, but there are subdevices of themselves, e.g.,
20010000.etf/20010000.etf:

kim at juno platform$ find /sys/devices/ -name \*etf\*
/sys/devices/platform/20140000.etf
/sys/devices/platform/20140000.etf/20140000.etf    <- THIS
/sys/devices/platform/20010000.etf
/sys/devices/platform/20010000.etf/20010000.etf    <- and this
/sys/devices/virtual/misc/20140000.etf
/sys/devices/virtual/misc/20010000.etf

'tree' output:

??? 20010000.etf
??? ??? 20010000.etf
??? ??? ??? enable_sink
??? ??? ??? mgmt
??? ??? ??? ??? ctl
??? ??? ??? ??? devid
??? ??? ??? ??? ffcr
??? ??? ??? ??? ffsr
??? ??? ??? ??? mode
??? ??? ??? ??? pscr
??? ??? ??? ??? rrp
??? ??? ??? ??? rsz
??? ??? ??? ??? rwp
??? ??? ??? ??? sts
??? ??? ??? ??? trg
??? ??? ??? power
??? ??? ??? ??? autosuspend_delay_ms
??? ??? ??? ??? control
??? ??? ??? ??? runtime_active_time
??? ??? ??? ??? runtime_status
??? ??? ??? ??? runtime_suspended_time
??? ??? ??? subsystem -> ../../../../bus/coresight
??? ??? ??? trigger_cntr
??? ??? ??? uevent
??? ??? driver -> ../../../bus/amba/drivers/coresight-tmc
??? ??? driver_override
??? ??? id
??? ??? of_node -> ../../../firmware/devicetree/base/etf at 20010000
??? ??? power
??? ??? ??? autosuspend_delay_ms
??? ??? ??? control
??? ??? ??? runtime_active_time
??? ??? ??? runtime_status
??? ??? ??? runtime_suspended_time
??? ??? resource
??? ??? subsystem -> ../../../bus/amba
??? ??? uevent

so things like power/ are duplicated, driver pointers missing from the
sub-node, etc.  I tried reading the documentation to find the reasoning
behind it, and didn't see any, but I may have missed it.  Normally each
platform device gets its own single node, and doesn't create a node
under itself with the same name.

If the subsystem pointer is of use, then I would have
thought 'bus/coresight' would have registered itself as a 'bus/amba'
node? 

> > Which doesn't match the coresight.txt usage documentation...
> 
> When operating CoreSight from the sysFS interface there is nothing
> preventing people from using the entries under /sys/devices/platform should
> they wish to.  It is simply easier to use /sys/bus/coresight/devices/, and
> that is well documented in coresight.txt.
> 
> > Also, do the current juno platforms not have CPU debug modules?  I'd
> > like to test the new driver.
> 
> By all means - Leo pointed out the patch adding the CPU debug entries in
> the DT  file for Juno.

Thanks, I applied it, was able to
toggle /sys/kernel/debug/coresight_cpu_debug/enable, but wasn't sure
how to trigger the cpu debug output...

Thanks,

Kim

[PATCH 00/17] coresight: next v4.12-rc4

[Leo Yan]

Hi Kim,

On Tue, Jun 13, 2017 at 04:17:12PM -0500, Kim Phillips wrote:

[...]

> > > Also, do the current juno platforms not have CPU debug modules?  I'd
> > > like to test the new driver.
> > 
> > By all means - Leo pointed out the patch adding the CPU debug entries in
> > the DT  file for Juno.
> 
> Thanks, I applied it, was able to
> toggle /sys/kernel/debug/coresight_cpu_debug/enable, but wasn't sure
> how to trigger the cpu debug output...

You could trigger panic flow with command, then can see CPU debug output:
echo c > /proc/sysrq-trigger

Thanks,
Leo Yan

[PATCH 00/17] coresight: next v4.12-rc4

[Kim Phillips]

On Wed, 14 Jun 2017 14:22:29 +0800
Leo Yan <leo.yan@linaro.org> wrote:

> Hi Kim,
> 
> On Tue, Jun 13, 2017 at 04:17:12PM -0500, Kim Phillips wrote:
> 
> [...]
> 
> > > > Also, do the current juno platforms not have CPU debug modules?  I'd
> > > > like to test the new driver.
> > > 
> > > By all means - Leo pointed out the patch adding the CPU debug entries in
> > > the DT  file for Juno.
> > 
> > Thanks, I applied it, was able to
> > toggle /sys/kernel/debug/coresight_cpu_debug/enable, but wasn't sure
> > how to trigger the cpu debug output...
> 
> You could trigger panic flow with command, then can see CPU debug output:
> echo c > /proc/sysrq-trigger

That worked, thanks.

The coresight CPU debug documentation states:

> At the runtime you can disable idle states with below methods:
> 
> Set latency request to /dev/cpu_dma_latency to disable all CPUs specific idle
> states (if latency = 0uS then disable all idle states):
> # echo "what_ever_latency_you_need_in_uS" > /dev/cpu_dma_latency
> 
> Disable specific CPU's specific idle state:
> # echo 1 > /sys/devices/system/cpu/cpu$cpu/cpuidle/state$state/disable

So I tried two values in /dev/cpu_dma_latency and expected a difference
in the per-cpu latency files, but didn't observe it:

root at juno:~# echo 0 > /dev/cpu_dma_latency
root at juno:~# more /sys/devices/system/cpu/cpu2/cpuidle*/state*/*laten*
::::::::::::::
/sys/devices/system/cpu/cpu2/cpuidle/state0/latency
::::::::::::::
1
::::::::::::::
/sys/devices/system/cpu/cpu2/cpuidle/state1/latency
::::::::::::::
1500
::::::::::::::
/sys/devices/system/cpu/cpu2/cpuidle/state2/latency
::::::::::::::
1600
root at juno:~# echo 1500 > /dev/cpu_dma_latency
root at juno:~# more /sys/devices/system/cpu/cpu2/cpuidle*/state*/*laten*
::::::::::::::
/sys/devices/system/cpu/cpu2/cpuidle/state0/latency
::::::::::::::
1
::::::::::::::
/sys/devices/system/cpu/cpu2/cpuidle/state1/latency
::::::::::::::
1500
::::::::::::::
/sys/devices/system/cpu/cpu2/cpuidle/state2/latency
::::::::::::::
1600
root at juno:~# cat /sys/kernel/debug/coresight_cpu_debug/enable
1

How does one tell whether writes to /dev/cpu_dma_latency are effective?

Thanks,

Kim

[PATCH 00/17] coresight: next v4.12-rc4

[Sudeep Holla]

On 15/06/17 04:34, Kim Phillips wrote:
[...]

> 
> How does one tell whether writes to /dev/cpu_dma_latency are effective?
> 
Watch /sys/devices/system/cpu/cpu*/cpuidle/state*/{usage,time}, they
shouldn't tick based on the value set to cpu_dma_latency.

E.g. a value of 0 should stop entering all the idle states.

-- 
Regards,
Sudeep

[PATCH 00/17] coresight: next v4.12-rc4

[Kim Phillips]

On Thu, 15 Jun 2017 09:41:22 +0100
Sudeep Holla <sudeep.holla@arm.com> wrote:

> On 15/06/17 04:34, Kim Phillips wrote:
> [...]
> > How does one tell whether writes to /dev/cpu_dma_latency are effective?
> > 
> Watch /sys/devices/system/cpu/cpu*/cpuidle/state*/{usage,time}, they
> shouldn't tick based on the value set to cpu_dma_latency.
> 
> E.g. a value of 0 should stop entering all the idle states.

I see all states following the same pattern whether 0 or not:

root at juno:~# cat show2.sh 
show()
{
	echo $1 > /dev/cpu_dma_latency
	echo === $1:
	cat /sys/devices/system/cpu/cpu2/cpuidle/state*/{usage,time}
	echo ---
	sleep 10
	cat /sys/devices/system/cpu/cpu2/cpuidle/state*/{usage,time}
}

show 0
show 1500
show 0
root at juno:~# taskset -c 2 bash ./show2.sh
=== 0:
1893
894
5417
1398675
65997648
3818880750
---
1895
905
5434
1401721
68076867
3826795502
=== 1500:
1895
905
5434
1401721
68076867
3826795502
---
1895
918
5447
1401721
69403510
3835466081
=== 0:
1895
918
5447
1401721
69403510
3835466081
---
1896
929
5463
1403577
71454839
3843409979

googling suggests the /dev/cpu_dma_latency file should be *kept* open,
and written a 32-bit binary number:

https://access.redhat.com/articles/65410

If so (I don't have time to test), this cpu debug documentation is very
deceptive.

Kim

[PATCH 00/17] coresight: next v4.12-rc4

[Leo Yan]

Hi Kim,

On Thu, Jun 15, 2017 at 09:22:46AM -0500, Kim Phillips wrote:
> On Thu, 15 Jun 2017 09:41:22 +0100
> Sudeep Holla <sudeep.holla@arm.com> wrote:
> 
> > On 15/06/17 04:34, Kim Phillips wrote:
> > [...]
> > > How does one tell whether writes to /dev/cpu_dma_latency are effective?
> > > 
> > Watch /sys/devices/system/cpu/cpu*/cpuidle/state*/{usage,time}, they
> > shouldn't tick based on the value set to cpu_dma_latency.
> > 
> > E.g. a value of 0 should stop entering all the idle states.
> 
> I see all states following the same pattern whether 0 or not:
> 
> root at juno:~# cat show2.sh 
> show()
> {
> 	echo $1 > /dev/cpu_dma_latency
> 	echo === $1:
> 	cat /sys/devices/system/cpu/cpu2/cpuidle/state*/{usage,time}
> 	echo ---
> 	sleep 10
> 	cat /sys/devices/system/cpu/cpu2/cpuidle/state*/{usage,time}
> }
> 
> show 0
> show 1500
> show 0
> root at juno:~# taskset -c 2 bash ./show2.sh
> === 0:
> 1893
> 894
> 5417
> 1398675
> 65997648
> 3818880750
> ---
> 1895
> 905
> 5434
> 1401721
> 68076867
> 3826795502
> === 1500:
> 1895
> 905
> 5434
> 1401721
> 68076867
> 3826795502
> ---
> 1895
> 918
> 5447
> 1401721
> 69403510
> 3835466081
> === 0:
> 1895
> 918
> 5447
> 1401721
> 69403510
> 3835466081
> ---
> 1896
> 929
> 5463
> 1403577
> 71454839
> 3843409979
> 
> googling suggests the /dev/cpu_dma_latency file should be *kept* open,
> and written a 32-bit binary number:
> 
> https://access.redhat.com/articles/65410
> 
> If so (I don't have time to test), this cpu debug documentation is very
> deceptive.

Looked into the code, and I must apologize I have not verified the
command when wrote the doc. As you pointed out, the closing file
operation releases the constraint for PM QoS.

Below command can work (I tested):
exec 3<> /dev/cpu_dma_latency; echo 0 >&3

Will commit one patch for this.

Thanks,
Leo Yan

[PATCH 00/17] coresight: next v4.12-rc4

[Kim Phillips]

On Thu, 15 Jun 2017 23:50:54 +0800
Leo Yan <leo.yan@linaro.org> wrote:

> Looked into the code, and I must apologize I have not verified the
> command when wrote the doc. As you pointed out, the closing file
> operation releases the constraint for PM QoS.
> 
> Below command can work (I tested):
> exec 3<> /dev/cpu_dma_latency; echo 0 >&3
> 
> Will commit one patch for this.

Did I miss this?  Where was it posted?

Thanks,

Kim

[PATCH 00/17] coresight: next v4.12-rc4

[Leo Yan]

Hi Kim,

On Mon, Aug 21, 2017 at 06:31:39PM -0500, Kim Phillips wrote:
> On Thu, 15 Jun 2017 23:50:54 +0800
> Leo Yan <leo.yan@linaro.org> wrote:
> 
> > Looked into the code, and I must apologize I have not verified the
> > command when wrote the doc. As you pointed out, the closing file
> > operation releases the constraint for PM QoS.
> > 
> > Below command can work (I tested):
> > exec 3<> /dev/cpu_dma_latency; echo 0 >&3
> > 
> > Will commit one patch for this.
> 
> Did I miss this?  Where was it posted?

Thanks for reminding, please review the patch:
http://archive.armlinux.org.uk/lurker/message/20170823.072318.6c34761c.en.html

Thanks,
Leo Yan

[PATCH 00/17] coresight: next v4.12-rc4

[Suzuki K Poulose]

On 14/06/17 07:22, Leo Yan wrote:
> Hi Kim,
>
> On Tue, Jun 13, 2017 at 04:17:12PM -0500, Kim Phillips wrote:
>
> [...]
>
>>>> Also, do the current juno platforms not have CPU debug modules?  I'd
>>>> like to test the new driver.
>>>
>>> By all means - Leo pointed out the patch adding the CPU debug entries in
>>> the DT  file for Juno.
>>
>> Thanks, I applied it, was able to
>> toggle /sys/kernel/debug/coresight_cpu_debug/enable, but wasn't sure
>> how to trigger the cpu debug output...
>
> You could trigger panic flow with command, then can see CPU debug output:
> echo c > /proc/sysrq-trigger

I think, may be we should provide a handle to trigger the CPU debug dump
manually, rather than using it only for panic. Something like :

echo 1 > /sys/kernel/debug/coresight_cpu_debug/trigger

Thoughts ?

Suzuki

[PATCH 00/17] coresight: next v4.12-rc4

[Kim Phillips]

On Thu, 15 Jun 2017 14:08:09 +0100
Suzuki K Poulose <Suzuki.Poulose@arm.com> wrote:

> On 14/06/17 07:22, Leo Yan wrote:
> > Hi Kim,
> >
> > On Tue, Jun 13, 2017 at 04:17:12PM -0500, Kim Phillips wrote:
> >
> > [...]
> >
> >>>> Also, do the current juno platforms not have CPU debug modules?  I'd
> >>>> like to test the new driver.
> >>>
> >>> By all means - Leo pointed out the patch adding the CPU debug entries in
> >>> the DT  file for Juno.
> >>
> >> Thanks, I applied it, was able to
> >> toggle /sys/kernel/debug/coresight_cpu_debug/enable, but wasn't sure
> >> how to trigger the cpu debug output...
> >
> > You could trigger panic flow with command, then can see CPU debug output:
> > echo c > /proc/sysrq-trigger
> 
> I think, may be we should provide a handle to trigger the CPU debug dump
> manually, rather than using it only for panic. Something like :
> 
> echo 1 > /sys/kernel/debug/coresight_cpu_debug/trigger
> 
> Thoughts ?

what's the use-case?  I just wanted to do a simple test, and although
it halted my machine, the sysrq-trigger switch did the job.

I'm personally not a huge fan of adding more switches, rather for doing
the right thing on behalf of the user in the first place.  E.g., in the
case of cpu debug, if configured =y, I don't think it would necessarily
harm the simple user to have it always be enabled, at boot time and
beyond, thereby doing away with the .../coresight_cpu_debug/enable
switch and kernel command line option.  If there are users that want to
turn it on and off dynamically, that can be done by loading and
unloading the module.

Kim

[PATCH 00/17] coresight: next v4.12-rc4

[Suzuki K Poulose]

On 15/06/17 14:40, Kim Phillips wrote:
> On Thu, 15 Jun 2017 14:08:09 +0100
> Suzuki K Poulose <Suzuki.Poulose@arm.com> wrote:
>
>> On 14/06/17 07:22, Leo Yan wrote:
>>> Hi Kim,
>>>
>>> On Tue, Jun 13, 2017 at 04:17:12PM -0500, Kim Phillips wrote:
>>>
>>> [...]
>>>
>>>>>> Also, do the current juno platforms not have CPU debug modules?  I'd
>>>>>> like to test the new driver.
>>>>>
>>>>> By all means - Leo pointed out the patch adding the CPU debug entries in
>>>>> the DT  file for Juno.
>>>>
>>>> Thanks, I applied it, was able to
>>>> toggle /sys/kernel/debug/coresight_cpu_debug/enable, but wasn't sure
>>>> how to trigger the cpu debug output...
>>>
>>> You could trigger panic flow with command, then can see CPU debug output:
>>> echo c > /proc/sysrq-trigger
>>
>> I think, may be we should provide a handle to trigger the CPU debug dump
>> manually, rather than using it only for panic. Something like :
>>
>> echo 1 > /sys/kernel/debug/coresight_cpu_debug/trigger
>>
>> Thoughts ?
>
> what's the use-case?  I just wanted to do a simple test, and although
> it halted my machine, the sysrq-trigger switch did the job.

Get the CPU dump without crashing the system, when the CPU is looping
indefinitely (with interrupts disabled) ? sysrq-t doesn't tell you where
the task/CPU is at if it is in running state. This can augment the details
by providing the PC. Sure, you can also do this by crashing the system
as above. But it doesn't hurt to provide the same without the crash.


>
> I'm personally not a huge fan of adding more switches, rather for doing
> the right thing on behalf of the user in the first place.  E.g., in the
> case of cpu debug, if configured =y, I don't think it would necessarily
> harm the simple user to have it always be enabled, at boot time and
> beyond, thereby doing away with the .../coresight_cpu_debug/enable

The reasoning behind this is to avoid keeping the debug power domain on
until someone really wants it enabled, so that one can use a single kernel
image in production/development and be able to switch things on at runtime.

> switch and kernel command line option.  If there are users that want to
> turn it on and off dynamically, that can be done by loading and
> unloading the module.

Sure, if someone is building it as a module, they have the luxury. But
this may not be always useful, e.g, crashes at early boot.

Suzuki

[PATCH 00/17] coresight: next v4.12-rc4

[Kim Phillips]

On Thu, 15 Jun 2017 15:02:21 +0100
Suzuki K Poulose <Suzuki.Poulose@arm.com> wrote:

> On 15/06/17 14:40, Kim Phillips wrote:
> > On Thu, 15 Jun 2017 14:08:09 +0100
> > Suzuki K Poulose <Suzuki.Poulose@arm.com> wrote:
> >
> >> On 14/06/17 07:22, Leo Yan wrote:
> >>> Hi Kim,
> >>>
> >>> On Tue, Jun 13, 2017 at 04:17:12PM -0500, Kim Phillips wrote:
> >>>
> >>> [...]
> >>>
> >>>>>> Also, do the current juno platforms not have CPU debug modules?  I'd
> >>>>>> like to test the new driver.
> >>>>>
> >>>>> By all means - Leo pointed out the patch adding the CPU debug entries in
> >>>>> the DT  file for Juno.
> >>>>
> >>>> Thanks, I applied it, was able to
> >>>> toggle /sys/kernel/debug/coresight_cpu_debug/enable, but wasn't sure
> >>>> how to trigger the cpu debug output...
> >>>
> >>> You could trigger panic flow with command, then can see CPU debug output:
> >>> echo c > /proc/sysrq-trigger
> >>
> >> I think, may be we should provide a handle to trigger the CPU debug dump
> >> manually, rather than using it only for panic. Something like :
> >>
> >> echo 1 > /sys/kernel/debug/coresight_cpu_debug/trigger
> >>
> >> Thoughts ?
> >
> > what's the use-case?  I just wanted to do a simple test, and although
> > it halted my machine, the sysrq-trigger switch did the job.
> 
> Get the CPU dump without crashing the system, when the CPU is looping
> indefinitely (with interrupts disabled) ? sysrq-t doesn't tell you where
> the task/CPU is at if it is in running state. This can augment the details
> by providing the PC. Sure, you can also do this by crashing the system
> as above. But it doesn't hurt to provide the same without the crash.

Can sysrq-t be amended, or another sysrq- dump mechanism - like 'v'
which apparently causes an ETM buffer dump [ARM-specific] - be used
instead?

> > I'm personally not a huge fan of adding more switches, rather for doing
> > the right thing on behalf of the user in the first place.  E.g., in the
> > case of cpu debug, if configured =y, I don't think it would necessarily
> > harm the simple user to have it always be enabled, at boot time and
> > beyond, thereby doing away with the .../coresight_cpu_debug/enable
> 
> The reasoning behind this is to avoid keeping the debug power domain on
> until someone really wants it enabled, so that one can use a single kernel
> image in production/development and be able to switch things on at runtime.

OK, thanks for explaining the trade-off.

> > switch and kernel command line option.  If there are users that want to
> > turn it on and off dynamically, that can be done by loading and
> > unloading the module.
> 
> Sure, if someone is building it as a module, they have the luxury. But
> this may not be always useful, e.g, crashes at early boot.

the thinking was that one could set it to =y at that point, but, yes,
point taken.

Kim