[RFC PATCH 0/7] EDAC drivers for Armada XP L2 and DDR

[jlu@pengutronix.de (Jan Lübbe)]

Hi Borislav,

On Fr, 2017-06-09 at 11:36 +0200, Borislav Petkov wrote:
> Before we go any further, pls put all the Marvell RAS functionality
> into a single file - I don't want a separate compilation unit per an
> IP block.
The L2 cache and DDR RAM controller are completely separate IP cores,
with separate register spaces, interrupts and so on. The cache is an ARM
design (some L2x0) extended by Marvell, while the DDR controller seems
to be unique to Marvell. It wouldn't surprise me if Marvell would decide
to reuse the DDR controller in another SoC using newer ARM cores with a
different cache.

> Also, some of your commit messages are empty and I'm sure they could
> use some text.
Sure, I mainly wanted to start the discussion with Chris. :-)

> And yes, it'd be very productive not to get conflicting submissions
> from you and Chris. :-)
Of course!

Regards,
Jan
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