* [PATCH 1/5] coresight: Correct buffer lost increment
2017-06-30 17:41 [PATCH 0/5] coresight: Miscellaneous fixes Mathieu Poirier
@ 2017-06-30 17:41 ` Mathieu Poirier
2017-06-30 17:41 ` [PATCH 2/5] coresight: etb10: Remove useless conversion to LE Mathieu Poirier
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Mathieu Poirier @ 2017-06-30 17:41 UTC (permalink / raw)
To: linux-arm-kernel
Many conditions may cause synchronisation to be lost when updating
the perf ring buffer but the end result is still the same: synchronisation
is lost. As such there is no need to increment the lost count for each
condition, just once will suffice.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-etb10.c | 10 +++++++---
drivers/hwtracing/coresight/coresight-tmc-etf.c | 8 ++++++--
2 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c
index d5b96423e1a5..d9c233135d6d 100644
--- a/drivers/hwtracing/coresight/coresight-etb10.c
+++ b/drivers/hwtracing/coresight/coresight-etb10.c
@@ -353,6 +353,7 @@ static void etb_update_buffer(struct coresight_device *csdev,
struct perf_output_handle *handle,
void *sink_config)
{
+ bool lost = false;
int i, cur;
u8 *buf_ptr;
u32 read_ptr, write_ptr, capacity;
@@ -384,7 +385,7 @@ static void etb_update_buffer(struct coresight_device *csdev,
(unsigned long)write_ptr);
write_ptr &= ~(ETB_FRAME_SIZE_WORDS - 1);
- perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
+ lost = true;
}
/*
@@ -395,7 +396,7 @@ static void etb_update_buffer(struct coresight_device *csdev,
*/
status = readl_relaxed(drvdata->base + ETB_STATUS_REG);
if (status & ETB_STATUS_RAM_FULL) {
- perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
+ lost = true;
to_read = capacity;
read_ptr = write_ptr;
} else {
@@ -428,9 +429,12 @@ static void etb_update_buffer(struct coresight_device *csdev,
if (read_ptr > (drvdata->buffer_depth - 1))
read_ptr -= drvdata->buffer_depth;
/* let the decoder know we've skipped ahead */
- perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
+ lost = true;
}
+ if (lost)
+ perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
+
/* finally tell HW where we want to start reading from */
writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER);
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index e3b9fb82eb8d..2e0fb5b9372c 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -369,6 +369,7 @@ static void tmc_update_etf_buffer(struct coresight_device *csdev,
struct perf_output_handle *handle,
void *sink_config)
{
+ bool lost = false;
int i, cur;
u32 *buf_ptr;
u32 read_ptr, write_ptr;
@@ -397,7 +398,7 @@ static void tmc_update_etf_buffer(struct coresight_device *csdev,
*/
status = readl_relaxed(drvdata->base + TMC_STS);
if (status & TMC_STS_FULL) {
- perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
+ lost = true;
to_read = drvdata->size;
} else {
to_read = CIRC_CNT(write_ptr, read_ptr, drvdata->size);
@@ -442,9 +443,12 @@ static void tmc_update_etf_buffer(struct coresight_device *csdev,
read_ptr -= drvdata->size;
/* Tell the HW */
writel_relaxed(read_ptr, drvdata->base + TMC_RRP);
- perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
+ lost = true;
}
+ if (lost)
+ perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
+
cur = buf->cur;
offset = buf->offset;
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/5] coresight: etb10: Remove useless conversion to LE
2017-06-30 17:41 [PATCH 0/5] coresight: Miscellaneous fixes Mathieu Poirier
2017-06-30 17:41 ` [PATCH 1/5] coresight: Correct buffer lost increment Mathieu Poirier
@ 2017-06-30 17:41 ` Mathieu Poirier
2017-06-30 17:41 ` [PATCH 3/5] coresight: Add barrier packet for synchronisation Mathieu Poirier
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Mathieu Poirier @ 2017-06-30 17:41 UTC (permalink / raw)
To: linux-arm-kernel
Internal CoreSight components are rendering trace data in little-endian
format. As such there is no need to convert the data once more, hence
removing the extra step.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-etb10.c | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c
index d9c233135d6d..50f4846e6271 100644
--- a/drivers/hwtracing/coresight/coresight-etb10.c
+++ b/drivers/hwtracing/coresight/coresight-etb10.c
@@ -233,10 +233,8 @@ static void etb_dump_hw(struct etb_drvdata *drvdata)
for (i = 0; i < depth; i++) {
read_data = readl_relaxed(drvdata->base +
ETB_RAM_READ_DATA_REG);
- *buf_ptr++ = read_data >> 0;
- *buf_ptr++ = read_data >> 8;
- *buf_ptr++ = read_data >> 16;
- *buf_ptr++ = read_data >> 24;
+ *(u32 *)buf_ptr = read_data;
+ buf_ptr += 4;
}
if (frame_off) {
@@ -444,10 +442,8 @@ static void etb_update_buffer(struct coresight_device *csdev,
buf_ptr = buf->data_pages[cur] + offset;
read_data = readl_relaxed(drvdata->base +
ETB_RAM_READ_DATA_REG);
- *buf_ptr++ = read_data >> 0;
- *buf_ptr++ = read_data >> 8;
- *buf_ptr++ = read_data >> 16;
- *buf_ptr++ = read_data >> 24;
+ *(u32 *)buf_ptr = read_data;
+ buf_ptr += 4;
offset += 4;
if (offset >= PAGE_SIZE) {
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 3/5] coresight: Add barrier packet for synchronisation
2017-06-30 17:41 [PATCH 0/5] coresight: Miscellaneous fixes Mathieu Poirier
2017-06-30 17:41 ` [PATCH 1/5] coresight: Correct buffer lost increment Mathieu Poirier
2017-06-30 17:41 ` [PATCH 2/5] coresight: etb10: Remove useless conversion to LE Mathieu Poirier
@ 2017-06-30 17:41 ` Mathieu Poirier
2017-06-30 17:41 ` [PATCH 4/5] coresight: etb10: Move etb_disable_hw() outside of lock Mathieu Poirier
2017-06-30 17:41 ` [PATCH 5/5] coresight: etm3x: Set synchronisation frequencty to TRM default Mathieu Poirier
4 siblings, 0 replies; 6+ messages in thread
From: Mathieu Poirier @ 2017-06-30 17:41 UTC (permalink / raw)
To: linux-arm-kernel
When a buffer overflow happens the synchronisation patckets usually
present at the beginning of the buffer are lost, a situation that
prevents the decoder from knowing the context of the traces being
decoded.
This patch adds a barrier packet to be used by sink IPs when a buffer
overflow condition is detected. These barrier packets are then used
by the decoding library as markers to force re-synchronisation.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-etb10.c | 22 +++++++++++++++++++--
drivers/hwtracing/coresight/coresight-priv.h | 2 ++
drivers/hwtracing/coresight/coresight-tmc-etf.c | 26 ++++++++++++++++++++++++-
drivers/hwtracing/coresight/coresight-tmc-etr.c | 12 ++++++++++++
drivers/hwtracing/coresight/coresight.c | 8 ++++++++
5 files changed, 67 insertions(+), 3 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c
index 50f4846e6271..42360306f049 100644
--- a/drivers/hwtracing/coresight/coresight-etb10.c
+++ b/drivers/hwtracing/coresight/coresight-etb10.c
@@ -200,8 +200,10 @@ static void etb_disable_hw(struct etb_drvdata *drvdata)
static void etb_dump_hw(struct etb_drvdata *drvdata)
{
+ bool lost = false;
int i;
u8 *buf_ptr;
+ const u32 *barrier;
u32 read_data, depth;
u32 read_ptr, write_ptr;
u32 frame_off, frame_endoff;
@@ -223,16 +225,24 @@ static void etb_dump_hw(struct etb_drvdata *drvdata)
}
if ((readl_relaxed(drvdata->base + ETB_STATUS_REG)
- & ETB_STATUS_RAM_FULL) == 0)
+ & ETB_STATUS_RAM_FULL) == 0) {
writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
- else
+ } else {
writel_relaxed(write_ptr, drvdata->base + ETB_RAM_READ_POINTER);
+ lost = true;
+ }
depth = drvdata->buffer_depth;
buf_ptr = drvdata->buf;
+ barrier = barrier_pkt;
for (i = 0; i < depth; i++) {
read_data = readl_relaxed(drvdata->base +
ETB_RAM_READ_DATA_REG);
+ if (lost && *barrier) {
+ read_data = *barrier;
+ barrier++;
+ }
+
*(u32 *)buf_ptr = read_data;
buf_ptr += 4;
}
@@ -354,6 +364,7 @@ static void etb_update_buffer(struct coresight_device *csdev,
bool lost = false;
int i, cur;
u8 *buf_ptr;
+ const u32 *barrier;
u32 read_ptr, write_ptr, capacity;
u32 status, read_data, to_read;
unsigned long offset;
@@ -438,10 +449,17 @@ static void etb_update_buffer(struct coresight_device *csdev,
cur = buf->cur;
offset = buf->offset;
+ barrier = barrier_pkt;
+
for (i = 0; i < to_read; i += 4) {
buf_ptr = buf->data_pages[cur] + offset;
read_data = readl_relaxed(drvdata->base +
ETB_RAM_READ_DATA_REG);
+ if (lost && *barrier) {
+ read_data = *barrier;
+ barrier++;
+ }
+
*(u32 *)buf_ptr = read_data;
buf_ptr += 4;
diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
index 5f662d82052c..3e25b1dd1a1a 100644
--- a/drivers/hwtracing/coresight/coresight-priv.h
+++ b/drivers/hwtracing/coresight/coresight-priv.h
@@ -56,6 +56,8 @@ static ssize_t name##_show(struct device *_dev, \
} \
static DEVICE_ATTR_RO(name)
+extern const u32 barrier_pkt[5];
+
enum etm_addr_type {
ETM_ADDR_TYPE_NONE,
ETM_ADDR_TYPE_SINGLE,
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index 2e0fb5b9372c..d189b28bd5c4 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -43,17 +43,34 @@ static void tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata)
{
+ bool lost = false;
char *bufp;
- u32 read_data;
+ const u32 *barrier;
+ u32 read_data, status;
int i;
+ /*
+ * Get a hold of the status register and see if a wrap around
+ * has occurred.
+ */
+ status = readl_relaxed(drvdata->base + TMC_STS);
+ if (status & TMC_STS_FULL)
+ lost = true;
+
bufp = drvdata->buf;
drvdata->len = 0;
+ barrier = barrier_pkt;
while (1) {
for (i = 0; i < drvdata->memwidth; i++) {
read_data = readl_relaxed(drvdata->base + TMC_RRD);
if (read_data == 0xFFFFFFFF)
return;
+
+ if (lost && *barrier) {
+ read_data = *barrier;
+ barrier++;
+ }
+
memcpy(bufp, &read_data, 4);
bufp += 4;
drvdata->len += 4;
@@ -371,6 +388,7 @@ static void tmc_update_etf_buffer(struct coresight_device *csdev,
{
bool lost = false;
int i, cur;
+ const u32 *barrier;
u32 *buf_ptr;
u32 read_ptr, write_ptr;
u32 status, to_read;
@@ -451,12 +469,18 @@ static void tmc_update_etf_buffer(struct coresight_device *csdev,
cur = buf->cur;
offset = buf->offset;
+ barrier = barrier_pkt;
/* for every byte to read */
for (i = 0; i < to_read; i += 4) {
buf_ptr = buf->data_pages[cur] + offset;
*buf_ptr = readl_relaxed(drvdata->base + TMC_RRD);
+ if (lost && *barrier) {
+ *buf_ptr = *barrier;
+ barrier++;
+ }
+
offset += 4;
if (offset >= PAGE_SIZE) {
offset = 0;
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 5d312699b3b9..b8fb981de7b6 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -59,6 +59,8 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
static void tmc_etr_dump_hw(struct tmc_drvdata *drvdata)
{
+ const u32 *barrier;
+ u32 *temp;
u32 rwp, val;
rwp = readl_relaxed(drvdata->base + TMC_RWP);
@@ -71,6 +73,16 @@ static void tmc_etr_dump_hw(struct tmc_drvdata *drvdata)
if (val & TMC_STS_FULL) {
drvdata->buf = drvdata->vaddr + rwp - drvdata->paddr;
drvdata->len = drvdata->size;
+
+ barrier = barrier_pkt;
+ temp = (u32 *)drvdata->buf;
+
+ while (*barrier) {
+ *temp = *barrier;
+ temp++;
+ barrier++;
+ }
+
} else {
drvdata->buf = drvdata->vaddr;
drvdata->len = rwp - drvdata->paddr;
diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c
index 6a0202b7384f..b8091bef21dc 100644
--- a/drivers/hwtracing/coresight/coresight.c
+++ b/drivers/hwtracing/coresight/coresight.c
@@ -53,6 +53,14 @@ static DEFINE_PER_CPU(struct list_head *, tracer_path);
*/
static struct list_head *stm_path;
+/*
+ * When losing synchronisation a new barrier packet needs to be inserted at the
+ * beginning of the data collected in a buffer. That way the decoder knows that
+ * it needs to look for another sync sequence.
+ */
+const u32 barrier_pkt[5] = {0x7fffffff, 0x7fffffff,
+ 0x7fffffff, 0x7fffffff, 0x0};
+
static int coresight_id_match(struct device *dev, void *data)
{
int trace_id, i_trace_id;
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 4/5] coresight: etb10: Move etb_disable_hw() outside of lock
2017-06-30 17:41 [PATCH 0/5] coresight: Miscellaneous fixes Mathieu Poirier
` (2 preceding siblings ...)
2017-06-30 17:41 ` [PATCH 3/5] coresight: Add barrier packet for synchronisation Mathieu Poirier
@ 2017-06-30 17:41 ` Mathieu Poirier
2017-06-30 17:41 ` [PATCH 5/5] coresight: etm3x: Set synchronisation frequencty to TRM default Mathieu Poirier
4 siblings, 0 replies; 6+ messages in thread
From: Mathieu Poirier @ 2017-06-30 17:41 UTC (permalink / raw)
To: linux-arm-kernel
Function etb_disable_hw() is already taking care of unlocking and locking
the coresight access register and as such doesn't need to be placed
within the unlock/lock of function etb_update_buffer().
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-etb10.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c
index 42360306f049..d0d186575c5d 100644
--- a/drivers/hwtracing/coresight/coresight-etb10.c
+++ b/drivers/hwtracing/coresight/coresight-etb10.c
@@ -376,8 +376,8 @@ static void etb_update_buffer(struct coresight_device *csdev,
capacity = drvdata->buffer_depth * ETB_FRAME_SIZE_WORDS;
- CS_UNLOCK(drvdata->base);
etb_disable_hw(drvdata);
+ CS_UNLOCK(drvdata->base);
/* unit is in words, not bytes */
read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER);
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 5/5] coresight: etm3x: Set synchronisation frequencty to TRM default
2017-06-30 17:41 [PATCH 0/5] coresight: Miscellaneous fixes Mathieu Poirier
` (3 preceding siblings ...)
2017-06-30 17:41 ` [PATCH 4/5] coresight: etb10: Move etb_disable_hw() outside of lock Mathieu Poirier
@ 2017-06-30 17:41 ` Mathieu Poirier
4 siblings, 0 replies; 6+ messages in thread
From: Mathieu Poirier @ 2017-06-30 17:41 UTC (permalink / raw)
To: linux-arm-kernel
Register ETMSYNCFR holds the number of by that need to be generated before
periodic synchronisation packets are inserted in the trace stream. By
zeroing out the config structure, the current code effectively disable
periodic synchronization.
This patch simply initialise the recommended value for this register as
specified in the technical reference manual.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-etm3x.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c
index a51b6b64ecdf..b67122acea7a 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x.c
@@ -243,6 +243,8 @@ void etm_set_default(struct etm_config *config)
}
config->ctxid_mask = 0x0;
+ /* Setting default to 1024 as per TRM recommendation */
+ config->sync_freq = 0x400;
}
void etm_config_trace_mode(struct etm_config *config)
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread