[PATCH RFC v4 0/4] Add Amlogic stateless H.264 video decoder for S4

[PATCH RFC v4 0/4] Add Amlogic stateless H.264 video decoder for S4

[Zhentao Guo via B4 Relay]

Introduce initial driver support for Amlogic's new video acceleration
hardware architecture, designed for video stream decoding.

Compared to the current Amlogic video decoder hardware architecture,
this new implementation eliminates the Esparser hardware component,
enabling direct vb2 buffer input. The driver is designed to support
the V4L2 M2M stateless decoder API. The initial phase includes support
for H.264 decoding on Amlogic S805X2 platform.

The driver is capable of:
- Supporting stateless H.264 decoding up to a resolution 1920x1088(on the S805X2 platform).
- Supporting I/P/B frame handling.
- Supporting vb2 mmap and dma-buf modes.
- Supporting frame-based decode mode. (Note that some H.264 bitstreams require
  DPB reordering to generate reference lists, the stateless decoder driver
  cannot access reordered reference lists in this mode, requiring the driver
  to perform reference list reordering itself)
- Supporting NV12/NV21 output.
- Supporting Annex B start codes.

This driver is tested with Gstreamer.
Example:
gst-launch-1.0 filesrc location=/tmp/video_640x360_mp4_hevc_450kbps_no_b.mp4 !
parsebin ! v4l2slh264dec ! filesink location=/tmp/output.yuv

Retry the compliance test based on kernel 6.19:
v4l2-compliance 1.30.1, 64 bits, 64-bit time_t

Compliance test for aml-vdec-drv device /dev/video0:

Driver Info:
        Driver name      : aml-vdec-drv
        Card type        : platform:aml-vdec-drv
        Bus info         : platform:fe320000.video-codec
        Driver version   : 6.19.0
        Capabilities     : 0x84204000
                Video Memory-to-Memory Multiplanar
                Streaming
                Extended Pix Format
                Device Capabilities
        Device Caps      : 0x04204000
                Video Memory-to-Memory Multiplanar
                Streaming
                Extended Pix Format
        Detected Stateless Decoder
Media Driver Info:
        Driver name      : aml-vdec-drv
        Model            : aml-vdec-drv
        Serial           :
        Bus info         : platform:fe320000.video-codec
        Media version    : 6.19.0
        Hardware revision: 0x00000000 (0)
        Driver version   : 6.19.0
Interface Info:
        ID               : 0x0300000c
        Type             : V4L Video
Entity Info:
        ID               : 0x00000001 (1)
        Name             : aml_dev_drv-source
        Function         : V4L2 I/O
        Pad 0x01000002   : 0: Source
          Link 0x02000008: to remote pad 0x1000004 of entity 'aml_dev_drv-proc' (Video Decoder): Data, Enabled, Immutable

Required ioctls:
        test MC information (see 'Media Driver Info' above): OK
        test VIDIOC_QUERYCAP: OK
        test invalid ioctls: OK

Allow for multiple opens:
        test second /dev/video0 open: OK
        test VIDIOC_QUERYCAP: OK
        test VIDIOC_G/S_PRIORITY: OK
        test for unlimited opens: OK

Debug ioctls:
        test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
        test VIDIOC_LOG_STATUS: OK (Not Supported)

Input ioctls:
        test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
        test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
        test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
        test VIDIOC_ENUMAUDIO: OK (Not Supported)
        test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
        test VIDIOC_G/S_AUDIO: OK (Not Supported)
        Inputs: 0 Audio Inputs: 0 Tuners: 0

Output ioctls:
        test VIDIOC_G/S_MODULATOR: OK (Not Supported)
        test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
        test VIDIOC_ENUMAUDOUT: OK (Not Supported)
        test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
        test VIDIOC_G/S_AUDOUT: OK (Not Supported)
        Outputs: 0 Audio Outputs: 0 Modulators: 0

Input/Output configuration ioctls:
        test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
        test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
        test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
        test VIDIOC_G/S_EDID: OK (Not Supported)

Control ioctls:
        test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
        test VIDIOC_QUERYCTRL: OK
        test VIDIOC_G/S_CTRL: OK
        test VIDIOC_G/S/TRY_EXT_CTRLS: OK
        test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
        test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
        Standard Controls: 6 Private Controls: 0
        Standard Compound Controls: 4 Private Compound Controls: 0

Format ioctls:
        test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
        test VIDIOC_G/S_PARM: OK (Not Supported)
        test VIDIOC_G_FBUF: OK (Not Supported)
        test VIDIOC_G_FMT: OK
        test VIDIOC_TRY_FMT: OK
        test VIDIOC_S_FMT: OK
        test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
        test Cropping: OK (Not Supported)
        test Composing: OK (Not Supported)
        test Scaling: OK (Not Supported)

Codec ioctls:
        test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
        test VIDIOC_G_ENC_INDEX: OK (Not Supported)
        test VIDIOC_(TRY_)DECODER_CMD: OK

Buffer ioctls:
        test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
        test CREATE_BUFS maximum buffers: OK
        test VIDIOC_REMOVE_BUFS: OK
        test VIDIOC_EXPBUF: OK
        test Requests: OK
        test blocking wait: OK

Total for aml-vdec-drv device /dev/video0: 49, Succeeded: 49, Failed: 0, Warnings: 0

Fluster test result of JVT-AVC_V1.
Result:
Ran 77/135 tests successfully

- 52 test vectors failed due to interlaced or mbaff clips: The Amlogic stateless
  decoder driver only support bitstreams with frame_mbs_only_flags == 1.
  Test Vectors:
        cabac_mot_fld0_full
        cabac_mot_mbaff0_full
        cabac_mot_picaff0_full
        CABREF3_Sand_D
        CAFI1_SVA_C
        CAMA1_Sony_C
        CAMA1_TOSHIBA_B
        cama1_vtc_c
        cama2_vtc_b
        CAMA3_Sand_E
        cama3_vtc_b
        CAMACI3_Sony_C
        CAMANL1_TOSHIBA_B
        CAMANL2_TOSHIBA_B
        CAMANL3_Sand_E
        CAMASL3_Sony_B
        CAMP_MOT_MBAFF_L30
        CAMP_MOT_MBAFF_L31
        CANLMA2_Sony_C
        CANLMA3_Sony_C
        CAPA1_TOSHIBA_B
        CAPAMA3_Sand_F
        cavlc_mot_fld0_full_B
        cavlc_mot_mbaff0_full_B
        cavlc_mot_picaff0_full_B
        CVCANLMA2_Sony_C
        CVFI1_Sony_D
        CVFI1_SVA_C
        CVFI2_Sony_H
        CVFI2_SVA_C
        CVMA1_Sony_D
        CVMA1_TOSHIBA_B
        CVMANL1_TOSHIBA_B
        CVMANL2_TOSHIBA_B
        CVMAPAQP3_Sony_E
        CVMAQP2_Sony_G
        CVMAQP3_Sony_D
        CVMP_MOT_FLD_L30_B
        CVNLFI1_Sony_C
        CVNLFI2_Sony_H
        CVPA1_TOSHIBA_B
        FI1_Sony_E
        MR6_BT_B
        MR7_BT_B
        MR8_BT_B
        MR9_BT_B
        Sharp_MP_Field_1_B
        Sharp_MP_Field_2_B
        Sharp_MP_Field_3_B
        Sharp_MP_PAFF_1r2
        Sharp_MP_PAFF_2r
        CVMP_MOT_FRM_L31_B
- 3 test vectors failed due to unsupported bitstream.
  num_slice_group_minus1 greater than zero is not supported by the
  hardware.
  Test Vectors:
        FM1_BT_B
        FM1_FT_E
        FM2_SVA_C
- 2 test vectors failed because SP_SLICE type is not supported by the
  hardware.
  Test Vectors:
        SP1_BT_A
        sp2_bt_b

One remain failure is CVFC1_Sony_C, which contains crop information. The md5sum of every decoded YUV indicates that original output from the decoder was correct. The YUV was cropped by gstreamer. The correct cropping method for this bitstream should be to crop 30*2 rows of pixels from both the top and bottom of the image, and 13*2 columns of pixels from both the left and right sides.However, gstreamer cropped 13*4 columns of pixels from the right side and 30*4 rows of pixels from the bottom. We are trying to find out the cause of this. Other failuers mentioned in V1 and V2 were resolved.

Changes in v4:
- Use %pad to print dma_addr_t type instead of using %llx.
- Add initial values to some local variables.
- Link to v3: https://lore.kernel.org/r/20260121-b4-s4-vdec-upstream-v3-0-4496aec3d79e@amlogic.com

Changes in v3:
- Fixed the DT check error:
  arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dtb: video-codec@fe320000 (amlogic,s4-vcodec-dec): 'amlogic,canvas' does not match any of the regexes: '^pinctrl-[0-9]+$' 
  from schema $id: http://devicetree.org/schemas/media/amlogic,vcodec-dec.yaml
- Added DOS reset lines to dtsi and dt-binding.
- Fixed the issue where some B-frames were not decoded correctly(The fluster failures mentioned in patch V1 and V2 were mostly caused by this).
- Fixed the issue where canvas_index leaks occurred during the decoding of some bitstreams.
- Rework the src/dst format storage. Use v4l2_pix_format_mplane to store formats that related to bitstreams into the context. Add the reset format function to reset all the formats to default value. 
- Store decoding parameters related to chip platforms, such as maximum width/height and alignment requirement, organized by chip platform.
- Link to v2: https://lore.kernel.org/r/20251124-b4-s4-vdec-upstream-v2-0-bdbbce3f11a6@amlogic.com

Changes in v2:
- Fixed incorrect generation of the reference lists for some B-frames.
- Rename or get rid of some properties in DTS and dt-binding.
- Remove some useless code or helper functions, (eg. clk helper functions, reg I/O macros, and some superfluous print messages) replace these functions with existing ones.
- Replace all the printk messages with dev_err/dev_info/dev_dbg
- Use the helper functions from the existing meson-canvas driver.
- Use clk_bulk_data to map clocks from DTS.
- Retry the V4L2 Compliance test on 6.18-rc6, fix a newly introduced bug.
- Link to v1: https://lore.kernel.org/r/20251027-b4-s4-vdec-upstream-v1-0-620401813b5d@amlogic.com

To: Mauro Carvalho Chehab <mchehab@kernel.org>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Neil Armstrong <neil.armstrong@linaro.org>
To: Kevin Hilman <khilman@baylibre.com>
To: Jerome Brunet <jbrunet@baylibre.com>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: linux-media@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-amlogic@lists.infradead.org

Signed-off-by: Zhentao Guo <zhentao.guo@amlogic.com>
---
Zhentao Guo (4):
      media: dt-bindings: Add Amlogic V4L2 video decoder
      decoder: Add V4L2 stateless H.264 decoder driver
      arm64: dts: amlogic: Add video decoder driver support for S4 SOCs
      arm64: defconfig: Enable VDEC driver for Amlogic SoCs

 .../bindings/media/amlogic,s4-vcodec-dec.yaml      |   96 +
 MAINTAINERS                                        |    7 +
 arch/arm64/boot/dts/amlogic/meson-s4.dtsi          |   28 +
 arch/arm64/configs/defconfig                       |    1 +
 drivers/media/platform/amlogic/Kconfig             |    1 +
 drivers/media/platform/amlogic/Makefile            |    1 +
 drivers/media/platform/amlogic/vdec/Kconfig        |   16 +
 drivers/media/platform/amlogic/vdec/Makefile       |    4 +
 drivers/media/platform/amlogic/vdec/TODO           |    7 +
 drivers/media/platform/amlogic/vdec/aml_vdec.c     |  734 +++++++
 drivers/media/platform/amlogic/vdec/aml_vdec.h     |   33 +
 drivers/media/platform/amlogic/vdec/aml_vdec_drv.c |  239 +++
 drivers/media/platform/amlogic/vdec/aml_vdec_drv.h |  172 ++
 drivers/media/platform/amlogic/vdec/aml_vdec_hw.c  |  596 ++++++
 drivers/media/platform/amlogic/vdec/aml_vdec_hw.h  |  158 ++
 .../platform/amlogic/vdec/aml_vdec_platform.c      |   85 +
 .../platform/amlogic/vdec/aml_vdec_platform.h      |   50 +
 drivers/media/platform/amlogic/vdec/h264.c         | 2129 ++++++++++++++++++++
 drivers/media/platform/amlogic/vdec/h264.h         |  299 +++
 drivers/media/platform/amlogic/vdec/reg_defines.h  |  177 ++
 20 files changed, 4833 insertions(+)
---
base-commit: 9845cf73f7db6094c0d8419d6adb848028f4a921
change-id: 20251027-b4-s4-vdec-upstream-0603c1a4c84a

Best regards,
-- 
Zhentao Guo <zhentao.guo@amlogic.com>

[PATCH RFC v4 1/4] media: dt-bindings: Add Amlogic V4L2 video decoder

[Zhentao Guo via B4 Relay]

From: Zhentao Guo <zhentao.guo@amlogic.com>

Describe the initial support for the V4L2 stateless video decoder
driver used with the Amlogic S4 (S805X2) platform.

Signed-off-by: Zhentao Guo <zhentao.guo@amlogic.com>
---
 .../bindings/media/amlogic,s4-vcodec-dec.yaml      | 96 ++++++++++++++++++++++
 1 file changed, 96 insertions(+)

diff --git a/Documentation/devicetree/bindings/media/amlogic,s4-vcodec-dec.yaml b/Documentation/devicetree/bindings/media/amlogic,s4-vcodec-dec.yaml
new file mode 100644
index 000000000000..88780514d06c
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/amlogic,s4-vcodec-dec.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2025 Amlogic, Inc. All rights reserved
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/amlogic,s4-vcodec-dec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic Video Decode Accelerator
+
+maintainers:
+  - Zhentao Guo <zhentao.guo@amlogic.com>
+
+description:
+  The Video Decoder Accelerator present on Amlogic SOCs.
+  It supports stateless h264 decoding.
+
+properties:
+  compatible:
+    const: amlogic,s4-vcodec-dec
+
+  reg:
+    maxItems: 2
+
+  reg-names:
+    items:
+      - const: dos
+      - const: dmc
+
+  interrupts:
+    maxItems: 3
+
+  clocks:
+    maxItems: 3
+
+  clock-names:
+    items:
+      - const: vdec
+      - const: clk_vdec_mux
+      - const: clk_hevcf_mux
+
+  power-domains:
+    maxItems: 2
+
+  power-domain-names:
+    items:
+      - const: vdec
+      - const: hevc
+
+  resets:
+    maxItems: 1
+
+  amlogic,canvas:
+    description: should point to a canvas provider node
+    $ref: /schemas/types.yaml#/definitions/phandle
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+  - clocks
+  - clock-names
+  - power-domains
+  - power-domain-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
+    #include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h>
+    #include <dt-bindings/power/meson-s4-power.h>
+    #include <dt-bindings/reset/amlogic,meson-s4-reset.h>
+    video-codec@fe320000 {
+      compatible = "amlogic,s4-vcodec-dec";
+      reg = <0xfe320000 0x10000>,
+            <0xfe036000 0x20>;
+      amlogic,canvas = <&canvas>;
+      reg-names = "dos",
+                  "dmc";
+      interrupts = <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
+      clocks = <&clkc_periphs CLKID_DOS>,
+               <&clkc_periphs CLKID_VDEC_SEL>,
+               <&clkc_periphs CLKID_HEVCF_SEL>;
+      clock-names = "vdec",
+                    "clk_vdec_mux",
+                    "clk_hevcf_mux";
+      power-domains = <&pwrc PWRC_S4_DOS_VDEC_ID>,
+                      <&pwrc PWRC_S4_DOS_HEVC_ID>;
+      power-domain-names = "vdec",
+                           "hevc";
+      resets = <&reset RESET_DOS>;
+    };

-- 
2.42.0

Re: [PATCH RFC v4 1/4] media: dt-bindings: Add Amlogic V4L2 video decoder

[Krzysztof Kozlowski]

On 13/02/2026 06:12, Zhentao Guo via B4 Relay wrote:
> From: Zhentao Guo <zhentao.guo@amlogic.com>
> 
> Describe the initial support for the V4L2 stateless video decoder
> driver used with the Amlogic S4 (S805X2) platform.
> 
> Signed-off-by: Zhentao Guo <zhentao.guo@amlogic.com>
> ---
>  .../bindings/media/amlogic,s4-vcodec-dec.yaml      | 96 ++++++++++++++++++++++
>  1 file changed, 96 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/media/amlogic,s4-vcodec-dec.yaml b/Documentation/devicetree/bindings/media/amlogic,s4-vcodec-dec.yaml
> new file mode 100644
> index 000000000000..88780514d06c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/amlogic,s4-vcodec-dec.yaml
> @@ -0,0 +1,96 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (C) 2025 Amlogic, Inc. All rights reserved
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/amlogic,s4-vcodec-dec.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Amlogic Video Decode Accelerator
> +
> +maintainers:
> +  - Zhentao Guo <zhentao.guo@amlogic.com>
> +
> +description:
> +  The Video Decoder Accelerator present on Amlogic SOCs.
> +  It supports stateless h264 decoding.
> +
> +properties:
> +  compatible:
> +    const: amlogic,s4-vcodec-dec

Why do you repeat "dec" twice? codec means decoder, so what is the last
"dec" about?

> +
> +  reg:
> +    maxItems: 2
> +
> +  reg-names:
> +    items:
> +      - const: dos
> +      - const: dmc
> +
> +  interrupts:
> +    maxItems: 3
> +
> +  clocks:
> +    maxItems: 3
> +
> +  clock-names:
> +    items:
> +      - const: vdec
> +      - const: clk_vdec_mux
> +      - const: clk_hevcf_mux

Name them based on their role/name in this device. Why this device would
care that it receives a mux? Not a div? or not a gate?

> +
> +  power-domains:
> +    maxItems: 2
> +
> +  power-domain-names:
> +    items:
> +      - const: vdec
> +      - const: hevc
> +
> +  resets:
> +    maxItems: 1
> +
> +  amlogic,canvas:
> +    description: should point to a canvas provider node

Why? What for?

What is canvas provider?


> +    $ref: /schemas/types.yaml#/definitions/phandle
> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - interrupts
> +  - clocks
> +  - clock-names
> +  - power-domains
> +  - power-domain-names
> +



Best regards,
Krzysztof

Re: [PATCH RFC v4 1/4] media: dt-bindings: Add Amlogic V4L2 video decoder

[Zhentao Guo]

在 2026/2/13 15:35, Krzysztof Kozlowski 写道:
> [ EXTERNAL EMAIL ]
>
> On 13/02/2026 06:12, Zhentao Guo via B4 Relay wrote:
>> From: Zhentao Guo <zhentao.guo@amlogic.com>
>>
>> Describe the initial support for the V4L2 stateless video decoder
>> driver used with the Amlogic S4 (S805X2) platform.
>>
>> Signed-off-by: Zhentao Guo <zhentao.guo@amlogic.com>
>> ---
>>   .../bindings/media/amlogic,s4-vcodec-dec.yaml      | 96 ++++++++++++++++++++++
>>   1 file changed, 96 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/media/amlogic,s4-vcodec-dec.yaml b/Documentation/devicetree/bindings/media/amlogic,s4-vcodec-dec.yaml
>> new file mode 100644
>> index 000000000000..88780514d06c
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/media/amlogic,s4-vcodec-dec.yaml
>> @@ -0,0 +1,96 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +# Copyright (C) 2025 Amlogic, Inc. All rights reserved
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/media/amlogic,s4-vcodec-dec.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Amlogic Video Decode Accelerator
>> +
>> +maintainers:
>> +  - Zhentao Guo <zhentao.guo@amlogic.com>
>> +
>> +description:
>> +  The Video Decoder Accelerator present on Amlogic SOCs.
>> +  It supports stateless h264 decoding.
>> +
>> +properties:
>> +  compatible:
>> +    const: amlogic,s4-vcodec-dec
> Why do you repeat "dec" twice? codec means decoder, so what is the last
> "dec" about?
In fact, codec means encoder+decoder, and dec is short for decoder.
>> +
>> +  reg:
>> +    maxItems: 2
>> +
>> +  reg-names:
>> +    items:
>> +      - const: dos
>> +      - const: dmc
>> +
>> +  interrupts:
>> +    maxItems: 3
>> +
>> +  clocks:
>> +    maxItems: 3
>> +
>> +  clock-names:
>> +    items:
>> +      - const: vdec
>> +      - const: clk_vdec_mux
>> +      - const: clk_hevcf_mux
> Name them based on their role/name in this device. Why this device would
> care that it receives a mux? Not a div? or not a gate?
Ok, previously we overlooked this. We will improve it in the next version.
>> +
>> +  power-domains:
>> +    maxItems: 2
>> +
>> +  power-domain-names:
>> +    items:
>> +      - const: vdec
>> +      - const: hevc
>> +
>> +  resets:
>> +    maxItems: 1
>> +
>> +  amlogic,canvas:
>> +    description: should point to a canvas provider node
> Why? What for?
>
> What is canvas provider?

The canvas provider is: drivers/soc/amlogic/meson-canvas.c

In short, canvas is a hardware IP inside the Amlogic SoC. The decoder IP 
needs to access DDR through canvas IP, so we need to reference the 
canvas driver.

>> +    $ref: /schemas/types.yaml#/definitions/phandle
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - reg-names
>> +  - interrupts
>> +  - clocks
>> +  - clock-names
>> +  - power-domains
>> +  - power-domain-names
>> +
> Best regards,
> Krzysztof

BRs

Zhentao

Re: [PATCH RFC v4 1/4] media: dt-bindings: Add Amlogic V4L2 video decoder

[Krzysztof Kozlowski]

On 13/02/2026 09:04, Zhentao Guo wrote:
> 
> 在 2026/2/13 15:35, Krzysztof Kozlowski 写道:
>> [ EXTERNAL EMAIL ]
>>

Do not send me such emails more than once. Also, drop the "EXTERNAL
EMAIL" markings.

Best regards,
Krzysztof

Re: [PATCH RFC v4 1/4] media: dt-bindings: Add Amlogic V4L2 video decoder

[Krzysztof Kozlowski]

On 13/02/2026 09:02, Zhentao Guo wrote:
> Hi Krzysztof,
> 
> 
> 在 2026/2/13 15:35, Krzysztof Kozlowski 写道:
>> [ EXTERNAL EMAIL ]
>>
>> On 13/02/2026 06:12, Zhentao Guo via B4 Relay wrote:
>>> From: Zhentao Guo<zhentao.guo@amlogic.com>
>>>
>>> Describe the initial support for the V4L2 stateless video decoder
>>> driver used with the Amlogic S4 (S805X2) platform.
>>>
>>> Signed-off-by: Zhentao Guo<zhentao.guo@amlogic.com>
>>> ---
>>>   .../bindings/media/amlogic,s4-vcodec-dec.yaml      | 96 ++++++++++++++++++++++
>>>   1 file changed, 96 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/media/amlogic,s4-vcodec-dec.yaml b/Documentation/devicetree/bindings/media/amlogic,s4-vcodec-dec.yaml
>>> new file mode 100644
>>> index 000000000000..88780514d06c
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/media/amlogic,s4-vcodec-dec.yaml
>>> @@ -0,0 +1,96 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +# Copyright (C) 2025 Amlogic, Inc. All rights reserved
>>> +%YAML 1.2
>>> +---
>>> +$id:http://devicetree.org/schemas/media/amlogic,s4-vcodec-dec.yaml#
>>> +$schema:http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Amlogic Video Decode Accelerator
>>> +
>>> +maintainers:
>>> +  - Zhentao Guo<zhentao.guo@amlogic.com>
>>> +
>>> +description:
>>> +  The Video Decoder Accelerator present on Amlogic SOCs.
>>> +  It supports stateless h264 decoding.
>>> +
>>> +properties:
>>> +  compatible:
>>> +    const: amlogic,s4-vcodec-dec
>> Why do you repeat "dec" twice? codec means decoder, so what is the last
>> "dec" about?
> In fact, codec means encoder+decoder, and dec is short for decoder.

Yes, that's what I meant, so why do you repeat decoder?

>>> +
>>> +  reg:
>>> +    maxItems: 2
>>> +
>>> +  reg-names:
>>> +    items:
>>> +      - const: dos
>>> +      - const: dmc
>>> +
>>> +  interrupts:
>>> +    maxItems: 3
>>> +
>>> +  clocks:
>>> +    maxItems: 3
>>> +
>>> +  clock-names:
>>> +    items:
>>> +      - const: vdec
>>> +      - const: clk_vdec_mux
>>> +      - const: clk_hevcf_mux
>> Name them based on their role/name in this device. Why this device would
>> care that it receives a mux? Not a div? or not a gate?
> Ok, previously we overlooked this. We will improve it in the next version.
>>> +
>>> +  power-domains:
>>> +    maxItems: 2
>>> +
>>> +  power-domain-names:
>>> +    items:
>>> +      - const: vdec
>>> +      - const: hevc
>>> +
>>> +  resets:
>>> +    maxItems: 1
>>> +
>>> +  amlogic,canvas:
>>> +    description: should point to a canvas provider node
>> Why? What for?
>>
>> What is canvas provider?
> 
> The canvas provider is: drivers/soc/amlogic/meson-canvas.c

What is this "canvas" device.

> 
> In short, canvas is a hardware IP inside the Amlogic SoC. The decoder IP 
> needs to access DDR through canvas IP, so we need to reference the 

Why decoder cannot access DDR directly?


Best regards,
Krzysztof

Re: [PATCH RFC v4 1/4] media: dt-bindings: Add Amlogic V4L2 video decoder

[Zhentao Guo]

Hi Krzysztof,

在 2026/2/13 16:16, Krzysztof Kozlowski 写道:
> On 13/02/2026 09:02, Zhentao Guo wrote:
>> Hi Krzysztof,
>>
>>
>> 在 2026/2/13 15:35, Krzysztof Kozlowski 写道:
>>
>>
>> On 13/02/2026 06:12, Zhentao Guo via B4 Relay wrote:
>>>> From: Zhentao Guo<zhentao.guo@amlogic.com>
>>>>
>>>> Describe the initial support for the V4L2 stateless video decoder
>>>> driver used with the Amlogic S4 (S805X2) platform.
>>>>
>>>> Signed-off-by: Zhentao Guo<zhentao.guo@amlogic.com>
>>>> ---
>>>>    .../bindings/media/amlogic,s4-vcodec-dec.yaml      | 96 ++++++++++++++++++++++
>>>>    1 file changed, 96 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/media/amlogic,s4-vcodec-dec.yaml b/Documentation/devicetree/bindings/media/amlogic,s4-vcodec-dec.yaml
>>>> new file mode 100644
>>>> index 000000000000..88780514d06c
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/media/amlogic,s4-vcodec-dec.yaml
>>>> @@ -0,0 +1,96 @@
>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>> +# Copyright (C) 2025 Amlogic, Inc. All rights reserved
>>>> +%YAML 1.2
>>>> +---
>>>> +$id:http://devicetree.org/schemas/media/amlogic,s4-vcodec-dec.yaml#
>>>> +$schema:http://devicetree.org/meta-schemas/core.yaml#
>>>> +
>>>> +title: Amlogic Video Decode Accelerator
>>>> +
>>>> +maintainers:
>>>> +  - Zhentao Guo<zhentao.guo@amlogic.com>
>>>> +
>>>> +description:
>>>> +  The Video Decoder Accelerator present on Amlogic SOCs.
>>>> +  It supports stateless h264 decoding.
>>>> +
>>>> +properties:
>>>> +  compatible:
>>>> +    const: amlogic,s4-vcodec-dec
>>> Why do you repeat "dec" twice? codec means decoder, so what is the last
>>> "dec" about?
>> In fact, codec means encoder+decoder, and dec is short for decoder.
> Yes, that's what I meant, so why do you repeat decoder?
Since this patch only involves the decoder, we want to highlight the 
decoder. We’ll consider a new node name, the current one is indeed 
redundant.
>>>> +
>>>> +  reg:
>>>> +    maxItems: 2
>>>> +
>>>> +  reg-names:
>>>> +    items:
>>>> +      - const: dos
>>>> +      - const: dmc
>>>> +
>>>> +  interrupts:
>>>> +    maxItems: 3
>>>> +
>>>> +  clocks:
>>>> +    maxItems: 3
>>>> +
>>>> +  clock-names:
>>>> +    items:
>>>> +      - const: vdec
>>>> +      - const: clk_vdec_mux
>>>> +      - const: clk_hevcf_mux
>>> Name them based on their role/name in this device. Why this device would
>>> care that it receives a mux? Not a div? or not a gate?
>> Ok, previously we overlooked this. We will improve it in the next version.
>>>> +
>>>> +  power-domains:
>>>> +    maxItems: 2
>>>> +
>>>> +  power-domain-names:
>>>> +    items:
>>>> +      - const: vdec
>>>> +      - const: hevc
>>>> +
>>>> +  resets:
>>>> +    maxItems: 1
>>>> +
>>>> +  amlogic,canvas:
>>>> +    description: should point to a canvas provider node
>>> Why? What for?
>>>
>>> What is canvas provider?
>> The canvas provider is: drivers/soc/amlogic/meson-canvas.c
> What is this "canvas" device.
You can think of canvas as the agent through which the decoder hardware 
accesses DDR.
>> In short, canvas is a hardware IP inside the Amlogic SoC. The decoder IP
>> needs to access DDR through canvas IP, so we need to reference the
> Why decoder cannot access DDR directly?
The internal topology of the S4 chip is designed this way, we don't know 
why our VLSI colleauges designed like this. But similar designs have 
been removed in subsequent chips, eliminating the need to rely on a 
common hardware IP.
> Best regards,
> Krzysztof

BRs

Zhentao

Re: [PATCH RFC v4 1/4] media: dt-bindings: Add Amlogic V4L2 video decoder

[Krzysztof Kozlowski]

On 13/02/2026 09:31, Zhentao Guo wrote:
>>>>> +  power-domains:
>>>>> +    maxItems: 2
>>>>> +
>>>>> +  power-domain-names:
>>>>> +    items:
>>>>> +      - const: vdec
>>>>> +      - const: hevc
>>>>> +
>>>>> +  resets:
>>>>> +    maxItems: 1
>>>>> +
>>>>> +  amlogic,canvas:
>>>>> +    description: should point to a canvas provider node
>>>> Why? What for?
>>>>
>>>> What is canvas provider?
>>> The canvas provider is: drivers/soc/amlogic/meson-canvas.c
>> What is this "canvas" device.
> You can think of canvas as the agent through which the decoder hardware 
> accesses DDR.

AGAIN:

What is the canvas device. Describe or point me to bindings describing
it. Your current bindings say that canvas is "a collection of metadata
that describes a pixel buffer" so there is no way it handles DDR access.

NAK

>>> In short, canvas is a hardware IP inside the Amlogic SoC. The decoder IP
>>> needs to access DDR through canvas IP, so we need to reference the
>> Why decoder cannot access DDR directly?
> The internal topology of the S4 chip is designed this way, we don't know 
> why our VLSI colleauges designed like this. But similar designs have 
> been removed in subsequent chips, eliminating the need to rely on a 
> common hardware IP.

Quite poor explanation. Based on this, this as well could be entry in
device reg lists.

Anyway, I am done guessing, explain properly the hardware instead of
answering with half-baked responses just so I will go away.


Best regards,
Krzysztof

Re: [PATCH RFC v4 1/4] media: dt-bindings: Add Amlogic V4L2 video decoder

[Zhentao Guo]

Hi

在 2026/2/13 16:55, Krzysztof Kozlowski 写道:
> On 13/02/2026 09:31, Zhentao Guo wrote:
>>>>>> +  power-domains:
>>>>>> +    maxItems: 2
>>>>>> +
>>>>>> +  power-domain-names:
>>>>>> +    items:
>>>>>> +      - const: vdec
>>>>>> +      - const: hevc
>>>>>> +
>>>>>> +  resets:
>>>>>> +    maxItems: 1
>>>>>> +
>>>>>> +  amlogic,canvas:
>>>>>> +    description: should point to a canvas provider node
>>>>> Why? What for?
>>>>>
>>>>> What is canvas provider?
>>>> The canvas provider is: drivers/soc/amlogic/meson-canvas.c
>>> What is this "canvas" device.
>> You can think of canvas as the agent through which the decoder hardware
>> accesses DDR.
> AGAIN:
>
> What is the canvas device. Describe or point me to bindings describing
> it. Your current bindings say that canvas is "a collection of metadata
> that describes a pixel buffer" so there is no way it handles DDR access.
>
> NAK
I will rewrite this description based on your feedback after I 
thoroughly understand the role of the canvas device.
>>>> In short, canvas is a hardware IP inside the Amlogic SoC. The decoder IP
>>>> needs to access DDR through canvas IP, so we need to reference the
>>> Why decoder cannot access DDR directly?
>> The internal topology of the S4 chip is designed this way, we don't know
>> why our VLSI colleauges designed like this. But similar designs have
>> been removed in subsequent chips, eliminating the need to rely on a
>> common hardware IP.
> Quite poor explanation. Based on this, this as well could be entry in
> device reg lists.
>
> Anyway, I am done guessing, explain properly the hardware instead of
> answering with half-baked responses just so I will go away.
Okay, please give me some time and I'll ask our colleagues about this.  
I you reply you basedon this message then.
> Best regards,
> Krzysztof

BRs

Zhentao

Re: [PATCH RFC v4 1/4] media: dt-bindings: Add Amlogic V4L2 video decoder

[Piotr Oniszczuk]

> Wiadomość napisana przez Krzysztof Kozlowski <krzk@kernel.org> w dniu 13 lut 2026, o godz. 09:55:
> 
> On 13/02/2026 09:31, Zhentao Guo wrote:
>>>>>> 
>>>>> Why? What for?
>>>>> 
>>>>> What is canvas provider?
>>>> The canvas provider is: drivers/soc/amlogic/meson-canvas.c
>>> What is this "canvas" device.
>> You can think of canvas as the agent through which the decoder hardware 
>> accesses DDR.
> 
> AGAIN:
> 
> What is the canvas device. Describe or point me to bindings describing
> it. Your current bindings say that canvas is "a collection of metadata
> that describes a pixel buffer" so there is no way it handles DDR access.
> 
> NAK
> 
>>>> In short, canvas is a hardware IP inside the Amlogic SoC. The decoder IP
>>>> needs to access DDR through canvas IP, so we need to reference the
>>> Why decoder cannot access DDR directly?
>> The internal topology of the S4 chip is designed this way, we don't know 
>> why our VLSI colleauges designed like this. But similar designs have 
>> been removed in subsequent chips, eliminating the need to rely on a 
>> common hardware IP.
> 
> Quite poor explanation. Based on this, this as well could be entry in
> device reg lists.
> 
> Anyway, I am done guessing, explain properly the hardware instead of
> answering with half-baked responses just so I will go away.
> 
> 
> Best regards,
> Krzysztof
> 

Krzysztof,

May you pls explain me: what added value - to upstreaming aml video decoder - will be provided by giving NAK .... because canvas/DDR access details explanations are not enough detailed FOR YOU?

Re: [PATCH RFC v4 1/4] media: dt-bindings: Add Amlogic V4L2 video decoder

[Krzysztof Kozlowski]

On 13/02/2026 12:14, Piotr Oniszczuk wrote:
>>
>>>>> In short, canvas is a hardware IP inside the Amlogic SoC. The decoder IP
>>>>> needs to access DDR through canvas IP, so we need to reference the
>>>> Why decoder cannot access DDR directly?
>>> The internal topology of the S4 chip is designed this way, we don't know 
>>> why our VLSI colleauges designed like this. But similar designs have 
>>> been removed in subsequent chips, eliminating the need to rely on a 
>>> common hardware IP.
>>
>> Quite poor explanation. Based on this, this as well could be entry in
>> device reg lists.
>>
>> Anyway, I am done guessing, explain properly the hardware instead of
>> answering with half-baked responses just so I will go away.
>>
>>
>> Best regards,
>> Krzysztof
>>
> 
> Krzysztof,
> 
> May you pls explain me: what added value - to upstreaming aml video decoder - will be provided by giving NAK .... because canvas/DDR access details explanations are not enough detailed FOR YOU?

NAK is a disagreement with this patch being merged, so there is no added
value in it. What sort of added value do you expect from NAKs?

Best regards,
Krzysztof

Re: [PATCH RFC v4 1/4] media: dt-bindings: Add Amlogic V4L2 video decoder

[Zhentao Guo]

Hi Krzysztof

Sorry for the late reply. As we discussed eariler, I would like to show 
you how the hardware module canvas work and why it is needed inside the 
Amlogic's SOCs. Hope this answers your questions.


      1. What is canvas? How it works?

The architecture is presented in the following diagram:

             +-----------------------------------+
             | Linux Kernel (CPU)                |
             |   +---------------------------+   |
             |   |                           |   |
             |   |   V4L2 Decoder Driver     |   |
             |   |                           |   |
             |   +---------------------------+   |
             +------|----------|---------^-------+
                    |	      | 	|	
                   DMA        APB       IRQ
                    |          |         |
      +-------------|----------|---------|------------+
      | Hardware    |          |         |            |
      |             v          v         |            |
      |      +----------------------------------+     |
      |      |                                  |     |
      |      |              AMRISC              |     |
      |      |                                  |     |
      |      +----------------------------------+     |
      |      |                                  |     |
      |      |           Decoder HW             |     |
      |      |                                  |     |
      |      +---|-----|-----|--------|-----|---+     |
      |         idx1 idx2 idx3 ... idx254 idx255      |
      |          |     |     |        |     |         |
      |          v     v     v        v     v         |
      |      +----------------------------------+     |
      |      |                                  |     |
      |      |            Canvas                |     |
      |      |                                  |     |
      |      +---|-----|-----|--------|-----|---+     |
      +----------|-----|-----|--------|-----|---------+
                PA1   PA2   PA3 ... PA254 PA255
                 |     |     |        |     |
                 v     v     v        v     v
      +-----------------------------------------------+
      |                                               |
      |                      DDR                      |
      |                                               |
      +-----------------------------------------------+


Canvas is a hardware module which maintains an on-chip-memory table. 
Each table entry describes a physical continuous memory region with its 
properties such as start address, size and the endian settings.
The design of Video decoder hardware uses canvas index to accesses 
memory. E.g. canvas #10 is configured to start from address 0x10000, 
size 1MB with little endian. And then this index number #10 is set to a 
hardware decoder register to set up a buffer destination. Canvas index 
is basically a reference to a memory region and its configurations. And 
a single decoder hardware register may take the canvas indexes for all 
three YUV components, which is helpful for AMRISC' s firmware (assembly 
coding) when setting up HW decoder configurations.
Memory access through canvas has HW out-of-boundary check. And it also 
has endian controls.


      2. Why canvas is needed?

 1. Since the ARM IOMMU HW is not integrated into the Amlogic SOCs,we
    need canvas to prevent the DDR memory used by the decoder from being
    rewrote by other hardware. Canvas provides the decoder with a
    configurable DDR memory range, as well as hardware-based detection
    and blocking for out-of-bounds access.
  2. From the diagram above, we can see a lite CPU called AMRISC. AMRISC
    is the controller of the decoder HW and the decoder driver needs to
    access the decoder hardware through AMRISC. However, AMRISC is a
    16-bit CPU and cannot directly handle 32-bit or 64-bit physical
    addresses. Therefore, canvas is required to convert the addresses
    into index to facilitate processing by the AMRISC core.

Regards,

Zhentao

> On 13/02/2026 09:31, Zhentao Guo wrote:
>>>>>> +  power-domains:
>>>>>> +    maxItems: 2
>>>>>> +
>>>>>> +  power-domain-names:
>>>>>> +    items:
>>>>>> +      - const: vdec
>>>>>> +      - const: hevc
>>>>>> +
>>>>>> +  resets:
>>>>>> +    maxItems: 1
>>>>>> +
>>>>>> +  amlogic,canvas:
>>>>>> +    description: should point to a canvas provider node
>>>>> Why? What for?
>>>>>
>>>>> What is canvas provider?
>>>> The canvas provider is: drivers/soc/amlogic/meson-canvas.c
>>> What is this "canvas" device.
>> You can think of canvas as the agent through which the decoder hardware
>> accesses DDR.
> AGAIN:
>
> What is the canvas device. Describe or point me to bindings describing
> it. Your current bindings say that canvas is "a collection of metadata
> that describes a pixel buffer" so there is no way it handles DDR access.
>
> NAK
>
>>>> In short, canvas is a hardware IP inside the Amlogic SoC. The decoder IP
>>>> needs to access DDR through canvas IP, so we need to reference the
>>> Why decoder cannot access DDR directly?
>> The internal topology of the S4 chip is designed this way, we don't know
>> why our VLSI colleauges designed like this. But similar designs have
>> been removed in subsequent chips, eliminating the need to rely on a
>> common hardware IP.
> Quite poor explanation. Based on this, this as well could be entry in
> device reg lists.
>
> Anyway, I am done guessing, explain properly the hardware instead of
> answering with half-baked responses just so I will go away.
>
>
> Best regards,
> Krzysztof

Re: [PATCH RFC v4 1/4] media: dt-bindings: Add Amlogic V4L2 video decoder

[Krzysztof Kozlowski]

On 05/03/2026 12:01, Zhentao Guo wrote:
> 
>       2. Why canvas is needed?
> 
>  1. Since the ARM IOMMU HW is not integrated into the Amlogic SOCs,we
>     need canvas to prevent the DDR memory used by the decoder from being
>     rewrote by other hardware. Canvas provides the decoder with a
>     configurable DDR memory range, as well as hardware-based detection
>     and blocking for out-of-bounds access.
>   2. From the diagram above, we can see a lite CPU called AMRISC. AMRISC
>     is the controller of the decoder HW and the decoder driver needs to
>     access the decoder hardware through AMRISC. However, AMRISC is a
>     16-bit CPU and cannot directly handle 32-bit or 64-bit physical
>     addresses. Therefore, canvas is required to convert the addresses
>     into index to facilitate processing by the AMRISC core.

This suggests "Canvas" is IOMMU, thus use proper IOMMU abstractions and
you cannot have own phandle for it.

Best regards,
Krzysztof

Re: [PATCH RFC v4 1/4] media: dt-bindings: Add Amlogic V4L2 video decoder

[Neil Armstrong]

On 3/5/26 12:08, Krzysztof Kozlowski wrote:
> On 05/03/2026 12:01, Zhentao Guo wrote:
>>
>>        2. Why canvas is needed?
>>
>>   1. Since the ARM IOMMU HW is not integrated into the Amlogic SOCs,we
>>      need canvas to prevent the DDR memory used by the decoder from being
>>      rewrote by other hardware. Canvas provides the decoder with a
>>      configurable DDR memory range, as well as hardware-based detection
>>      and blocking for out-of-bounds access.
>>    2. From the diagram above, we can see a lite CPU called AMRISC. AMRISC
>>      is the controller of the decoder HW and the decoder driver needs to
>>      access the decoder hardware through AMRISC. However, AMRISC is a
>>      16-bit CPU and cannot directly handle 32-bit or 64-bit physical
>>      addresses. Therefore, canvas is required to convert the addresses
>>      into index to facilitate processing by the AMRISC core.
> 
> This suggests "Canvas" is IOMMU, thus use proper IOMMU abstractions and
> you cannot have own phandle for it.


No it is not, canvas was used for a long time for the display and video processing side.

It's absolutely not like an IOMMU, the diagram is quite clear.

Neil

> 
> Best regards,
> Krzysztof

Re: [PATCH RFC v4 1/4] media: dt-bindings: Add Amlogic V4L2 video decoder

[Krzysztof Kozlowski]

On 05/03/2026 12:35, Neil Armstrong wrote:
> On 3/5/26 12:08, Krzysztof Kozlowski wrote:
>> On 05/03/2026 12:01, Zhentao Guo wrote:
>>>
>>>        2. Why canvas is needed?
>>>
>>>   1. Since the ARM IOMMU HW is not integrated into the Amlogic SOCs,we
>>>      need canvas to prevent the DDR memory used by the decoder from being
>>>      rewrote by other hardware. Canvas provides the decoder with a
>>>      configurable DDR memory range, as well as hardware-based detection
>>>      and blocking for out-of-bounds access.
>>>    2. From the diagram above, we can see a lite CPU called AMRISC. AMRISC
>>>      is the controller of the decoder HW and the decoder driver needs to
>>>      access the decoder hardware through AMRISC. However, AMRISC is a
>>>      16-bit CPU and cannot directly handle 32-bit or 64-bit physical
>>>      addresses. Therefore, canvas is required to convert the addresses
>>>      into index to facilitate processing by the AMRISC core.
>>
>> This suggests "Canvas" is IOMMU, thus use proper IOMMU abstractions and
>> you cannot have own phandle for it.
> 
> 
> No it is not, canvas was used for a long time for the display and video processing side.
> 
> It's absolutely not like an IOMMU, the diagram is quite clear.

The diagram and all descriptions points to memory mapping...

"Canvas index is basically a reference to a memory region and its
configurations."
"Memory access through canvas has HW out-of-boundary check. "
"Canvas provides the decoder with a configurable DDR memory range"
"canvas is required to convert the addresses into index to..."

so it is not a random phandle either.


Best regards,
Krzysztof

Re: [PATCH RFC v4 1/4] media: dt-bindings: Add Amlogic V4L2 video decoder

[Neil Armstrong]

On 3/5/26 12:53, Krzysztof Kozlowski wrote:
> On 05/03/2026 12:35, Neil Armstrong wrote:
>> On 3/5/26 12:08, Krzysztof Kozlowski wrote:
>>> On 05/03/2026 12:01, Zhentao Guo wrote:
>>>>
>>>>         2. Why canvas is needed?
>>>>
>>>>    1. Since the ARM IOMMU HW is not integrated into the Amlogic SOCs,we
>>>>       need canvas to prevent the DDR memory used by the decoder from being
>>>>       rewrote by other hardware. Canvas provides the decoder with a
>>>>       configurable DDR memory range, as well as hardware-based detection
>>>>       and blocking for out-of-bounds access.
>>>>     2. From the diagram above, we can see a lite CPU called AMRISC. AMRISC
>>>>       is the controller of the decoder HW and the decoder driver needs to
>>>>       access the decoder hardware through AMRISC. However, AMRISC is a
>>>>       16-bit CPU and cannot directly handle 32-bit or 64-bit physical
>>>>       addresses. Therefore, canvas is required to convert the addresses
>>>>       into index to facilitate processing by the AMRISC core.
>>>
>>> This suggests "Canvas" is IOMMU, thus use proper IOMMU abstractions and
>>> you cannot have own phandle for it.
>>
>>
>> No it is not, canvas was used for a long time for the display and video processing side.
>>
>> It's absolutely not like an IOMMU, the diagram is quite clear.
> 
> The diagram and all descriptions points to memory mapping...
> 
> "Canvas index is basically a reference to a memory region and its
> configurations."
> "Memory access through canvas has HW out-of-boundary check."
> "Canvas provides the decoder with a configurable DDR memory range"
> "canvas is required to convert the addresses into index to..."
> 
> so it is not a random phandle either.

No mapping is done by the Canvas HW, we simply reserve a "slot" we feed with
a linear buffer allocated by ourselves + parameters on the frame format, and
then the display engine or the video decoder will only need this slot index to
access the memory.

It doesn't fine anywhere and amlogic specific.

Neil

> 
> 
> Best regards,
> Krzysztof

[PATCH RFC v4 3/4] arm64: dts: amlogic: Add video decoder driver support for S4 SOCs

[Zhentao Guo via B4 Relay]

From: Zhentao Guo <zhentao.guo@amlogic.com>

Add vcodec node to enable Amlogic V4L2 stateless video decoder
support.

Signed-off-by: Zhentao Guo <zhentao.guo@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
index dfc0a30a6e61..b8355e41d550 100644
--- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
@@ -862,5 +862,33 @@ emmc: mmc@fe08c000 {
 			assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_C>;
 			assigned-clock-rates = <24000000>;
 		};
+
+		canvas: video-lut@fe036048 {
+			compatible = "amlogic,canvas";
+			reg = <0x0 0xfe036048 0x0 0x14>;
+		};
+
+		video-codec@fe320000 {
+			compatible = "amlogic,s4-vcodec-dec";
+			reg = <0x0 0xfe320000 0x0 0x10000>,
+			      <0x0 0xfe036000 0x0 0x20>;
+			amlogic,canvas = <&canvas>;
+			reg-names = "dos",
+				    "dmc";
+			interrupts = <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&clkc_periphs CLKID_DOS>,
+				 <&clkc_periphs CLKID_VDEC_SEL>,
+				 <&clkc_periphs CLKID_HEVCF_SEL>;
+			clock-names = "vdec",
+				      "clk_vdec_mux",
+				      "clk_hevcf_mux";
+			power-domains = <&pwrc PWRC_S4_DOS_VDEC_ID>,
+					<&pwrc PWRC_S4_DOS_HEVC_ID>;
+			power-domain-names = "vdec",
+					     "hevc";
+			resets = <&reset RESET_DOS>;
+		};
 	};
 };

-- 
2.42.0

[PATCH RFC v4 4/4] arm64: defconfig: Enable VDEC driver for Amlogic SoCs

[Zhentao Guo via B4 Relay]

From: Zhentao Guo <zhentao.guo@amlogic.com>

Enable the driver for Amlogic's stateless decoder.

Signed-off-by: Zhentao Guo <zhentao.guo@amlogic.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index b67d5b1fc45b..9c1dc377d519 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -905,6 +905,7 @@ CONFIG_USB_VIDEO_CLASS=m
 CONFIG_V4L_PLATFORM_DRIVERS=y
 CONFIG_SDR_PLATFORM_DRIVERS=y
 CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_VIDEO_AMLOGIC_VDEC=m
 CONFIG_VIDEO_AMPHION_VPU=m
 CONFIG_VIDEO_CADENCE_CSI2RX=m
 CONFIG_VIDEO_MEDIATEK_JPEG=m

-- 
2.42.0

Re: [PATCH RFC v4 4/4] arm64: defconfig: Enable VDEC driver for Amlogic SoCs

[Krzysztof Kozlowski]

On 13/02/2026 06:12, Zhentao Guo via B4 Relay wrote:
> From: Zhentao Guo <zhentao.guo@amlogic.com>
> 
> Enable the driver for Amlogic's stateless decoder.

Why? Read other commits how this is supposed to look like.


Best regards,
Krzysztof

Re: [PATCH RFC v4 4/4] arm64: defconfig: Enable VDEC driver for Amlogic SoCs

[Zhentao Guo]

Hi

在 2026/2/13 15:33, Krzysztof Kozlowski 写道:
> [ EXTERNAL EMAIL ]
>
> On 13/02/2026 06:12, Zhentao Guo via B4 Relay wrote:
>> From: Zhentao Guo <zhentao.guo@amlogic.com>
>>
>> Enable the driver for Amlogic's stateless decoder.
> Why? Read other commits how this is supposed to look like.
I explained the reason in patch 1/4. But please inform me if you have 
more suggestions. Thanks a lot!
> Best regards,
> Krzysztof

Re: [PATCH RFC v4 4/4] arm64: defconfig: Enable VDEC driver for Amlogic SoCs

[Krzysztof Kozlowski]

On 13/02/2026 09:06, Zhentao Guo wrote:
> Hi
> 
> 在 2026/2/13 15:33, Krzysztof Kozlowski 写道:
>> [ EXTERNAL EMAIL ]
>>
>> On 13/02/2026 06:12, Zhentao Guo via B4 Relay wrote:
>>> From: Zhentao Guo <zhentao.guo@amlogic.com>
>>>
>>> Enable the driver for Amlogic's stateless decoder.
>> Why? Read other commits how this is supposed to look like.
> I explained the reason in patch 1/4. But please inform me if you have 
> more suggestions. Thanks a lot!


There is no single reason in 1/4 and anyway it would not matter. I
already informed you how you can improve your code.

NAK

Best regards,
Krzysztof