From: mathieu.poirier@linaro.org (Mathieu Poirier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 18/26] coresight tmc: Detect support for scatter gather
Date: Wed, 2 Aug 2017 10:22:12 -0600 [thread overview]
Message-ID: <1501690940-4137-19-git-send-email-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <1501690940-4137-1-git-send-email-mathieu.poirier@linaro.org>
From: Suzuki K Poulose <suzuki.poulose@arm.com>
The SG unit in the TMC has been removed in Coresight SoC-600.
This is however advertised by DEVID:Bit 24 = 0b1. On the
previous generation, the bit is RES0, hence we can rely on the
DEVID to detect the support.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-tmc.c | 2 ++
drivers/hwtracing/coresight/coresight-tmc.h | 5 +++++
2 files changed, 7 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index 0c99ef7b9b2b..bb409c485d05 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -306,6 +306,8 @@ static int tmc_etr_setup_caps(struct tmc_drvdata *drvdata,
/* Set the unadvertised capabilities */
tmc_etr_init_caps(drvdata, (u32)(unsigned long)dev_caps);
+ if (!(devid & TMC_DEVID_NOSCAT))
+ tmc_etr_set_cap(drvdata, TMC_ETR_SG);
/*
* ETR configuration uses a 40-bit AXI master in place of
* the embedded SRAM of ETB/ETF.
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 13ab1008f110..bb6a3e3314b8 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -69,6 +69,8 @@
#define TMC_FFCR_STOP_ON_FLUSH BIT(12)
+#define TMC_DEVID_NOSCAT BIT(24)
+
enum tmc_config_type {
TMC_CONFIG_TYPE_ETB,
TMC_CONFIG_TYPE_ETR,
@@ -88,6 +90,9 @@ enum tmc_mem_intf_width {
TMC_MEM_INTF_WIDTH_256BITS = 8,
};
+/* TMC ETR Capability bit definitions */
+#define TMC_ETR_SG (0x1U << 0)
+
/**
* struct tmc_drvdata - specifics associated to an TMC component
* @base: memory mapped base address for this component.
--
2.7.4
next prev parent reply other threads:[~2017-08-02 16:22 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-02 16:21 [PATCH 00/26] coresight: next v4.13-rc3 Mathieu Poirier
2017-08-02 16:21 ` [PATCH 01/26] coresight: Correct buffer lost increment Mathieu Poirier
2017-08-02 16:21 ` [PATCH 02/26] coresight: etb10: Remove useless conversion to LE Mathieu Poirier
2017-08-02 16:21 ` [PATCH 03/26] coresight: Add barrier packet for synchronisation Mathieu Poirier
2017-08-02 16:21 ` [PATCH 04/26] coresight: etb10: Move etb_disable_hw() outside of lock Mathieu Poirier
2017-08-02 16:21 ` [PATCH 05/26] coresight: etm3x: Set synchronisation frequencty to TRM default Mathieu Poirier
2017-08-02 16:22 ` [PATCH 06/26] hwtracing: coresight: constify attribute_group structures Mathieu Poirier
2017-08-02 16:22 ` [PATCH 07/26] coresight: pmu: Adds return stack option to perf coresight pmu Mathieu Poirier
2017-08-02 16:22 ` [PATCH 08/26] coresight: ptm: Adds trace return stack option programming for PTM Mathieu Poirier
2017-08-02 16:22 ` [PATCH 09/26] coresight: etm4x: Adds trace return stack option programming for ETMv4 Mathieu Poirier
2017-08-02 16:22 ` [PATCH 10/26] coresight replicator: Cleanup programmable replicator naming Mathieu Poirier
2017-08-02 16:22 ` [PATCH 11/26] coresight: Add support for reading 64bit registers Mathieu Poirier
2017-08-02 16:22 ` [PATCH 12/26] coresight: Use the new helper for defining registers Mathieu Poirier
2017-08-02 16:22 ` [PATCH 13/26] coresight tmc: Add helpers for accessing 64bit registers Mathieu Poirier
2017-08-02 16:22 ` [PATCH 14/26] coresight tmc: Expose DBA and AXICTL Mathieu Poirier
2017-08-02 16:22 ` [PATCH 15/26] coresight replicator: Expose replicator management registers Mathieu Poirier
2017-08-02 16:22 ` [PATCH 16/26] coresight tmc: Handle configuration types properly Mathieu Poirier
2017-08-02 16:22 ` [PATCH 17/26] coresight tmc etr: Add capabilitiy information Mathieu Poirier
2017-08-02 16:22 ` Mathieu Poirier [this message]
2017-08-02 16:22 ` [PATCH 19/26] coresight tmc etr: Detect address width at runtime Mathieu Poirier
2017-08-02 16:22 ` [PATCH 20/26] coresight tmc etr: Cleanup AXICTL register handling Mathieu Poirier
2017-08-02 16:22 ` [PATCH 21/26] coresight tmc etr: Setup AXI cache encoding for read transfers Mathieu Poirier
2017-08-02 16:22 ` [PATCH 22/26] coresight tmc: Support for save-restore in ETR Mathieu Poirier
2017-08-02 16:22 ` [PATCH 23/26] coresight tmc: Add support for Coresight SoC 600 TMC Mathieu Poirier
2017-08-02 16:22 ` [PATCH 24/26] coresight: Add support for Coresight SoC 600 components Mathieu Poirier
2017-08-02 16:22 ` [PATCH 25/26] perf: cs-etm: Fix ETMv4 CONFIGR entry in perf.data file Mathieu Poirier
2017-08-02 16:22 ` [PATCH 26/26] coresight: STM: Clean up __iomem type usage Mathieu Poirier
2017-08-28 14:07 ` [PATCH 00/26] coresight: next v4.13-rc3 Greg KH
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