From: mathieu.poirier@linaro.org (Mathieu Poirier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 01/26] coresight: Correct buffer lost increment
Date: Wed, 2 Aug 2017 10:21:55 -0600 [thread overview]
Message-ID: <1501690940-4137-2-git-send-email-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <1501690940-4137-1-git-send-email-mathieu.poirier@linaro.org>
Many conditions may cause synchronisation to be lost when updating
the perf ring buffer but the end result is still the same: synchronisation
is lost. As such there is no need to increment the lost count for each
condition, just once will suffice.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-etb10.c | 10 +++++++---
drivers/hwtracing/coresight/coresight-tmc-etf.c | 8 ++++++--
2 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c
index d5b96423e1a5..d9c233135d6d 100644
--- a/drivers/hwtracing/coresight/coresight-etb10.c
+++ b/drivers/hwtracing/coresight/coresight-etb10.c
@@ -353,6 +353,7 @@ static void etb_update_buffer(struct coresight_device *csdev,
struct perf_output_handle *handle,
void *sink_config)
{
+ bool lost = false;
int i, cur;
u8 *buf_ptr;
u32 read_ptr, write_ptr, capacity;
@@ -384,7 +385,7 @@ static void etb_update_buffer(struct coresight_device *csdev,
(unsigned long)write_ptr);
write_ptr &= ~(ETB_FRAME_SIZE_WORDS - 1);
- perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
+ lost = true;
}
/*
@@ -395,7 +396,7 @@ static void etb_update_buffer(struct coresight_device *csdev,
*/
status = readl_relaxed(drvdata->base + ETB_STATUS_REG);
if (status & ETB_STATUS_RAM_FULL) {
- perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
+ lost = true;
to_read = capacity;
read_ptr = write_ptr;
} else {
@@ -428,9 +429,12 @@ static void etb_update_buffer(struct coresight_device *csdev,
if (read_ptr > (drvdata->buffer_depth - 1))
read_ptr -= drvdata->buffer_depth;
/* let the decoder know we've skipped ahead */
- perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
+ lost = true;
}
+ if (lost)
+ perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
+
/* finally tell HW where we want to start reading from */
writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER);
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index e3b9fb82eb8d..2e0fb5b9372c 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -369,6 +369,7 @@ static void tmc_update_etf_buffer(struct coresight_device *csdev,
struct perf_output_handle *handle,
void *sink_config)
{
+ bool lost = false;
int i, cur;
u32 *buf_ptr;
u32 read_ptr, write_ptr;
@@ -397,7 +398,7 @@ static void tmc_update_etf_buffer(struct coresight_device *csdev,
*/
status = readl_relaxed(drvdata->base + TMC_STS);
if (status & TMC_STS_FULL) {
- perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
+ lost = true;
to_read = drvdata->size;
} else {
to_read = CIRC_CNT(write_ptr, read_ptr, drvdata->size);
@@ -442,9 +443,12 @@ static void tmc_update_etf_buffer(struct coresight_device *csdev,
read_ptr -= drvdata->size;
/* Tell the HW */
writel_relaxed(read_ptr, drvdata->base + TMC_RRP);
- perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
+ lost = true;
}
+ if (lost)
+ perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
+
cur = buf->cur;
offset = buf->offset;
--
2.7.4
next prev parent reply other threads:[~2017-08-02 16:21 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-02 16:21 [PATCH 00/26] coresight: next v4.13-rc3 Mathieu Poirier
2017-08-02 16:21 ` Mathieu Poirier [this message]
2017-08-02 16:21 ` [PATCH 02/26] coresight: etb10: Remove useless conversion to LE Mathieu Poirier
2017-08-02 16:21 ` [PATCH 03/26] coresight: Add barrier packet for synchronisation Mathieu Poirier
2017-08-02 16:21 ` [PATCH 04/26] coresight: etb10: Move etb_disable_hw() outside of lock Mathieu Poirier
2017-08-02 16:21 ` [PATCH 05/26] coresight: etm3x: Set synchronisation frequencty to TRM default Mathieu Poirier
2017-08-02 16:22 ` [PATCH 06/26] hwtracing: coresight: constify attribute_group structures Mathieu Poirier
2017-08-02 16:22 ` [PATCH 07/26] coresight: pmu: Adds return stack option to perf coresight pmu Mathieu Poirier
2017-08-02 16:22 ` [PATCH 08/26] coresight: ptm: Adds trace return stack option programming for PTM Mathieu Poirier
2017-08-02 16:22 ` [PATCH 09/26] coresight: etm4x: Adds trace return stack option programming for ETMv4 Mathieu Poirier
2017-08-02 16:22 ` [PATCH 10/26] coresight replicator: Cleanup programmable replicator naming Mathieu Poirier
2017-08-02 16:22 ` [PATCH 11/26] coresight: Add support for reading 64bit registers Mathieu Poirier
2017-08-02 16:22 ` [PATCH 12/26] coresight: Use the new helper for defining registers Mathieu Poirier
2017-08-02 16:22 ` [PATCH 13/26] coresight tmc: Add helpers for accessing 64bit registers Mathieu Poirier
2017-08-02 16:22 ` [PATCH 14/26] coresight tmc: Expose DBA and AXICTL Mathieu Poirier
2017-08-02 16:22 ` [PATCH 15/26] coresight replicator: Expose replicator management registers Mathieu Poirier
2017-08-02 16:22 ` [PATCH 16/26] coresight tmc: Handle configuration types properly Mathieu Poirier
2017-08-02 16:22 ` [PATCH 17/26] coresight tmc etr: Add capabilitiy information Mathieu Poirier
2017-08-02 16:22 ` [PATCH 18/26] coresight tmc: Detect support for scatter gather Mathieu Poirier
2017-08-02 16:22 ` [PATCH 19/26] coresight tmc etr: Detect address width at runtime Mathieu Poirier
2017-08-02 16:22 ` [PATCH 20/26] coresight tmc etr: Cleanup AXICTL register handling Mathieu Poirier
2017-08-02 16:22 ` [PATCH 21/26] coresight tmc etr: Setup AXI cache encoding for read transfers Mathieu Poirier
2017-08-02 16:22 ` [PATCH 22/26] coresight tmc: Support for save-restore in ETR Mathieu Poirier
2017-08-02 16:22 ` [PATCH 23/26] coresight tmc: Add support for Coresight SoC 600 TMC Mathieu Poirier
2017-08-02 16:22 ` [PATCH 24/26] coresight: Add support for Coresight SoC 600 components Mathieu Poirier
2017-08-02 16:22 ` [PATCH 25/26] perf: cs-etm: Fix ETMv4 CONFIGR entry in perf.data file Mathieu Poirier
2017-08-02 16:22 ` [PATCH 26/26] coresight: STM: Clean up __iomem type usage Mathieu Poirier
2017-08-28 14:07 ` [PATCH 00/26] coresight: next v4.13-rc3 Greg KH
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1501690940-4137-2-git-send-email-mathieu.poirier@linaro.org \
--to=mathieu.poirier@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).