From: mathieu.poirier@linaro.org (Mathieu Poirier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 21/26] coresight tmc etr: Setup AXI cache encoding for read transfers
Date: Wed, 2 Aug 2017 10:22:15 -0600 [thread overview]
Message-ID: <1501690940-4137-22-git-send-email-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <1501690940-4137-1-git-send-email-mathieu.poirier@linaro.org>
From: Suzuki K Poulose <suzuki.poulose@arm.com>
If the ETR supports split cache encoding (i.e, separate bits for
read and write transfers) unlike the older version (where read
and write transfers use the same encoding in AXICTL[2-5]).
This feature is not advertised and has to be described by the
static mask associated with the device id.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 6 ++++++
drivers/hwtracing/coresight/coresight-tmc.h | 10 +++++++++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 880b53527599..40ddcf11ae4c 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -39,6 +39,12 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
axictl &= ~TMC_AXICTL_CLEAR_MASK;
axictl |= (TMC_AXICTL_PROT_CTL_B1 | TMC_AXICTL_WR_BURST_16);
axictl |= TMC_AXICTL_AXCACHE_OS;
+
+ if (tmc_etr_has_cap(drvdata, TMC_ETR_AXI_ARCACHE)) {
+ axictl &= ~TMC_AXICTL_ARCACHE_MASK;
+ axictl |= TMC_AXICTL_ARCACHE_OS;
+ }
+
writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
tmc_write_dba(drvdata, drvdata->paddr);
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 07c0bf1d9269..f39caa6a45c3 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -59,13 +59,18 @@
*
* TMC AXICTL format for SoC-400
* Bits [0-1] : ProtCtrlBit0-1
- * Bits [2-5] : CacheCtrlBits 0-3 (AxCACHE)
+ * Bits [2-5] : CacheCtrlBits 0-3 (AXCACHE)
* Bit 6 : Reserved
* Bit 7 : ScatterGatherMode
* Bits [8-11] : WrBurstLen
* Bits [12-31] : Reserved.
+ * TMC AXICTL format for SoC-600, as above except:
+ * Bits [2-5] : AXI WCACHE
+ * Bits [16-19] : AXI RCACHE
+ * Bits [20-31] : Reserved
*/
#define TMC_AXICTL_CLEAR_MASK 0xfbf
+#define TMC_AXICTL_ARCACHE_MASK (0xf << 16)
#define TMC_AXICTL_PROT_CTL_B0 BIT(0)
#define TMC_AXICTL_PROT_CTL_B1 BIT(1)
@@ -73,6 +78,7 @@
#define TMC_AXICTL_WR_BURST_16 0xF00
/* Write-back Read and Write-allocate */
#define TMC_AXICTL_AXCACHE_OS (0xf << 2)
+#define TMC_AXICTL_ARCACHE_OS (0xf << 16)
/* TMC_FFCR - 0x304 */
#define TMC_FFCR_FLUSHMAN_BIT 6
@@ -111,6 +117,8 @@ enum tmc_mem_intf_width {
/* TMC ETR Capability bit definitions */
#define TMC_ETR_SG (0x1U << 0)
+/* ETR has separate read/write cache encodings */
+#define TMC_ETR_AXI_ARCACHE (0x1U << 1)
/**
* struct tmc_drvdata - specifics associated to an TMC component
--
2.7.4
next prev parent reply other threads:[~2017-08-02 16:22 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-02 16:21 [PATCH 00/26] coresight: next v4.13-rc3 Mathieu Poirier
2017-08-02 16:21 ` [PATCH 01/26] coresight: Correct buffer lost increment Mathieu Poirier
2017-08-02 16:21 ` [PATCH 02/26] coresight: etb10: Remove useless conversion to LE Mathieu Poirier
2017-08-02 16:21 ` [PATCH 03/26] coresight: Add barrier packet for synchronisation Mathieu Poirier
2017-08-02 16:21 ` [PATCH 04/26] coresight: etb10: Move etb_disable_hw() outside of lock Mathieu Poirier
2017-08-02 16:21 ` [PATCH 05/26] coresight: etm3x: Set synchronisation frequencty to TRM default Mathieu Poirier
2017-08-02 16:22 ` [PATCH 06/26] hwtracing: coresight: constify attribute_group structures Mathieu Poirier
2017-08-02 16:22 ` [PATCH 07/26] coresight: pmu: Adds return stack option to perf coresight pmu Mathieu Poirier
2017-08-02 16:22 ` [PATCH 08/26] coresight: ptm: Adds trace return stack option programming for PTM Mathieu Poirier
2017-08-02 16:22 ` [PATCH 09/26] coresight: etm4x: Adds trace return stack option programming for ETMv4 Mathieu Poirier
2017-08-02 16:22 ` [PATCH 10/26] coresight replicator: Cleanup programmable replicator naming Mathieu Poirier
2017-08-02 16:22 ` [PATCH 11/26] coresight: Add support for reading 64bit registers Mathieu Poirier
2017-08-02 16:22 ` [PATCH 12/26] coresight: Use the new helper for defining registers Mathieu Poirier
2017-08-02 16:22 ` [PATCH 13/26] coresight tmc: Add helpers for accessing 64bit registers Mathieu Poirier
2017-08-02 16:22 ` [PATCH 14/26] coresight tmc: Expose DBA and AXICTL Mathieu Poirier
2017-08-02 16:22 ` [PATCH 15/26] coresight replicator: Expose replicator management registers Mathieu Poirier
2017-08-02 16:22 ` [PATCH 16/26] coresight tmc: Handle configuration types properly Mathieu Poirier
2017-08-02 16:22 ` [PATCH 17/26] coresight tmc etr: Add capabilitiy information Mathieu Poirier
2017-08-02 16:22 ` [PATCH 18/26] coresight tmc: Detect support for scatter gather Mathieu Poirier
2017-08-02 16:22 ` [PATCH 19/26] coresight tmc etr: Detect address width at runtime Mathieu Poirier
2017-08-02 16:22 ` [PATCH 20/26] coresight tmc etr: Cleanup AXICTL register handling Mathieu Poirier
2017-08-02 16:22 ` Mathieu Poirier [this message]
2017-08-02 16:22 ` [PATCH 22/26] coresight tmc: Support for save-restore in ETR Mathieu Poirier
2017-08-02 16:22 ` [PATCH 23/26] coresight tmc: Add support for Coresight SoC 600 TMC Mathieu Poirier
2017-08-02 16:22 ` [PATCH 24/26] coresight: Add support for Coresight SoC 600 components Mathieu Poirier
2017-08-02 16:22 ` [PATCH 25/26] perf: cs-etm: Fix ETMv4 CONFIGR entry in perf.data file Mathieu Poirier
2017-08-02 16:22 ` [PATCH 26/26] coresight: STM: Clean up __iomem type usage Mathieu Poirier
2017-08-28 14:07 ` [PATCH 00/26] coresight: next v4.13-rc3 Greg KH
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