[PATCH v2 0/4] clk: rockchip: rv1108: support mac clk

[PATCH v2 0/4] clk: rockchip: rv1108: support mac clk

[Elaine Zhang]

change in V2:
[PATCH v2 1/4] : NONE
[PATCH v2 2/4] : NONE
[PATCH v2 3/4] : NONE
[PATCH v2 4/4] : fix up the clk_mac mux regs description error

Elaine Zhang (4):
  clk: rockchip: add rv1108 ACLK_GAMC and PCLK_GMAC ID
  clk: rockchip: rv1108: add ACLK_GMAC and PCLK_GMAC clk id
  clk: rockchip: rv1108: rename macphy to mac
  clk: rockchip: rv1108: fix up the clk_mac sel register description

 drivers/clk/rockchip/clk-rv1108.c      | 14 ++++++++------
 include/dt-bindings/clock/rv1108-cru.h |  8 +++++---
 2 files changed, 13 insertions(+), 9 deletions(-)

-- 
1.9.1

[PATCH v2 1/4] clk: rockchip: add rv1108 ACLK_GAMC and PCLK_GMAC ID

[Elaine Zhang]

This patch exports gmac aclk and pclk for dts reference.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 include/dt-bindings/clock/rv1108-cru.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/dt-bindings/clock/rv1108-cru.h b/include/dt-bindings/clock/rv1108-cru.h
index f269d833e41a..2239ae2a19b9 100644
--- a/include/dt-bindings/clock/rv1108-cru.h
+++ b/include/dt-bindings/clock/rv1108-cru.h
@@ -110,6 +110,7 @@
 #define ACLK_CIF2			207
 #define ACLK_CIF3			208
 #define ACLK_PERI			209
+#define ACLK_GMAC			210
 
 /* pclk gates */
 #define PCLK_GPIO1			256
@@ -141,6 +142,7 @@
 #define PCLK_EFUSE0			282
 #define PCLK_EFUSE1			283
 #define PCLK_WDT			284
+#define PCLK_GMAC			285
 
 /* hclk gates */
 #define HCLK_I2S0_8CH			320
-- 
1.9.1

[PATCH v2 2/4] clk: rockchip: rv1108: add ACLK_GMAC and PCLK_GMAC clk id

[Elaine Zhang]

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/rockchip/clk-rv1108.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/rockchip/clk-rv1108.c b/drivers/clk/rockchip/clk-rv1108.c
index d1065dd9f442..0e441ec21e90 100644
--- a/drivers/clk/rockchip/clk-rv1108.c
+++ b/drivers/clk/rockchip/clk-rv1108.c
@@ -763,6 +763,8 @@ enum rv1108_plls {
 	GATE(SCLK_MACPHY_RX, "sclk_macphy_rx", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 8, GFLAGS),
 	GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 6, GFLAGS),
 	GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 7, GFLAGS),
+	GATE(ACLK_GMAC, "aclk_gmac", "aclk_periph", 0, RV1108_CLKGATE_CON(15), 4, GFLAGS),
+	GATE(PCLK_GMAC, "pclk_gmac", "pclk_periph", 0, RV1108_CLKGATE_CON(15), 5, GFLAGS),
 
 	MMC(SCLK_SDMMC_DRV,    "sdmmc_drv",    "sclk_sdmmc", RV1108_SDMMC_CON0, 1),
 	MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RV1108_SDMMC_CON1, 1),
-- 
1.9.1

[PATCH v2 3/4] clk: rockchip: rv1108: rename macphy to mac

[Elaine Zhang]

This MAC has no internal phy for rv1108.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/rockchip/clk-rv1108.c      | 12 ++++++------
 include/dt-bindings/clock/rv1108-cru.h |  6 +++---
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rv1108.c b/drivers/clk/rockchip/clk-rv1108.c
index 0e441ec21e90..658da17c9d99 100644
--- a/drivers/clk/rockchip/clk-rv1108.c
+++ b/drivers/clk/rockchip/clk-rv1108.c
@@ -140,7 +140,7 @@ enum rv1108_plls {
 PNAME(mux_uart0_p)		= { "uart0_src", "uart0_frac", "xin24m" };
 PNAME(mux_uart1_p)		= { "uart1_src", "uart1_frac", "xin24m" };
 PNAME(mux_uart2_p)		= { "uart2_src", "uart2_frac", "xin24m" };
-PNAME(mux_sclk_macphy_p)	= { "ext_gmac", "sclk_macphy_pre" };
+PNAME(mux_sclk_mac_p)	= { "ext_gmac", "sclk_mac_pre" };
 PNAME(mux_i2s0_pre_p)		= { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
 PNAME(mux_i2s_out_p)		= { "i2s0_pre", "xin12m" };
 PNAME(mux_i2s1_p)		= { "i2s1_src", "i2s1_frac", "dummy", "xin12m" };
@@ -755,14 +755,14 @@ enum rv1108_plls {
 			RV1108_CLKGATE_CON(5), 4, GFLAGS),
 	GATE(HCLK_SFC, "hclk_sfc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 10, GFLAGS),
 
-	COMPOSITE(SCLK_MACPHY_PRE, "sclk_macphy_pre", mux_pll_src_apll_gpll_p, 0,
+	COMPOSITE(SCLK_MAC_PRE, "sclk_mac_pre", mux_pll_src_apll_gpll_p, 0,
 			RV1108_CLKSEL_CON(24), 12, 1, MFLAGS, 0, 5, DFLAGS,
 			RV1108_CLKGATE_CON(4), 10, GFLAGS),
-	MUX(SCLK_MACPHY, "sclk_macphy", mux_sclk_macphy_p, CLK_SET_RATE_PARENT,
+	MUX(SCLK_MAC, "sclk_mac", mux_sclk_mac_p, CLK_SET_RATE_PARENT,
 			RV1108_CLKSEL_CON(24), 8, 1, MFLAGS),
-	GATE(SCLK_MACPHY_RX, "sclk_macphy_rx", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 8, GFLAGS),
-	GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 6, GFLAGS),
-	GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 7, GFLAGS),
+	GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 8, GFLAGS),
+	GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 6, GFLAGS),
+	GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 7, GFLAGS),
 	GATE(ACLK_GMAC, "aclk_gmac", "aclk_periph", 0, RV1108_CLKGATE_CON(15), 4, GFLAGS),
 	GATE(PCLK_GMAC, "pclk_gmac", "pclk_periph", 0, RV1108_CLKGATE_CON(15), 5, GFLAGS),
 
diff --git a/include/dt-bindings/clock/rv1108-cru.h b/include/dt-bindings/clock/rv1108-cru.h
index 2239ae2a19b9..d8d0e0456dc2 100644
--- a/include/dt-bindings/clock/rv1108-cru.h
+++ b/include/dt-bindings/clock/rv1108-cru.h
@@ -67,9 +67,9 @@
 #define SCLK_SPI			108
 #define SCLK_SARADC			109
 #define SCLK_TSADC			110
-#define SCLK_MACPHY_PRE			111
-#define SCLK_MACPHY			112
-#define SCLK_MACPHY_RX			113
+#define SCLK_MAC_PRE			111
+#define SCLK_MAC			112
+#define SCLK_MAC_RX			113
 #define SCLK_MAC_REF			114
 #define SCLK_MAC_REFOUT			115
 #define SCLK_DSP_PFM			116
-- 
1.9.1

[PATCH v2 4/4] clk: rockchip: rv1108: fix up the clk_mac sel register description

[Elaine Zhang]

cru_sel24_con[8]
rmii_extclk_sel
clock source select control register
1'b0: from internal PLL
1'b1: from external IO

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/rockchip/clk-rv1108.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rv1108.c b/drivers/clk/rockchip/clk-rv1108.c
index 658da17c9d99..4d87828df4f7 100644
--- a/drivers/clk/rockchip/clk-rv1108.c
+++ b/drivers/clk/rockchip/clk-rv1108.c
@@ -140,7 +140,7 @@ enum rv1108_plls {
 PNAME(mux_uart0_p)		= { "uart0_src", "uart0_frac", "xin24m" };
 PNAME(mux_uart1_p)		= { "uart1_src", "uart1_frac", "xin24m" };
 PNAME(mux_uart2_p)		= { "uart2_src", "uart2_frac", "xin24m" };
-PNAME(mux_sclk_mac_p)	= { "ext_gmac", "sclk_mac_pre" };
+PNAME(mux_sclk_mac_p)	= { "sclk_mac_pre", "ext_gmac" };
 PNAME(mux_i2s0_pre_p)		= { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
 PNAME(mux_i2s_out_p)		= { "i2s0_pre", "xin12m" };
 PNAME(mux_i2s1_p)		= { "i2s1_src", "i2s1_frac", "dummy", "xin12m" };
-- 
1.9.1

[PATCH v2 1/4] clk: rockchip: add rv1108 ACLK_GAMC and PCLK_GMAC ID

[David.Wu]

Hi Elaine,

? 2017/8/21 16:16, Elaine Zhang ??:
> This patch exports gmac aclk and pclk for dts reference.
> 
> Signed-off-by: Elaine Zhang<zhangqing@rock-chips.com>
> ---
>   include/dt-bindings/clock/rv1108-cru.h | 2 ++
>   1 file changed, 2 insertions(+)

Acked-by: David Wu <david.wu@rock-chips.com>

[PATCH v2 2/4] clk: rockchip: rv1108: add ACLK_GMAC and PCLK_GMAC clk id

[David.Wu]

Hi Elaine,

? 2017/8/21 16:16, Elaine Zhang ??:
> Signed-off-by: Elaine Zhang<zhangqing@rock-chips.com>
> ---
>   drivers/clk/rockchip/clk-rv1108.c | 2 ++
>   1 file changed, 2 insertions(+)

Acked-by: David Wu <david.wu@rock-chips.com>

[PATCH v2 3/4] clk: rockchip: rv1108: rename macphy to mac

[David.Wu]

Hi Elaine,

? 2017/8/21 16:16, Elaine Zhang ??:
> This MAC has no internal phy for rv1108.
> 
> Signed-off-by: Elaine Zhang<zhangqing@rock-chips.com>
> ---
>   drivers/clk/rockchip/clk-rv1108.c      | 12 ++++++------
>   include/dt-bindings/clock/rv1108-cru.h |  6 +++---
>   2 files changed, 9 insertions(+), 9 deletions(-)

Acked-by: David Wu <david.wu@rock-chips.com>

Usually, MAC and PHY are separate, macphy is easy to cause ambiguity, 
and RV1108 SOC does not have integrated ethernet PHY. It is more clear 
to change the name.

[PATCH v2 4/4] clk: rockchip: rv1108: fix up the clk_mac sel register description

[David.Wu]

Hi Elaine,

? 2017/8/21 16:16, Elaine Zhang ??:
> cru_sel24_con[8]
> rmii_extclk_sel
> clock source select control register
> 1'b0: from internal PLL
> 1'b1: from external IO
> 
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> ---
>   drivers/clk/rockchip/clk-rv1108.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/rockchip/clk-rv1108.c b/drivers/clk/rockchip/clk-rv1108.c
> index 658da17c9d99..4d87828df4f7 100644
> --- a/drivers/clk/rockchip/clk-rv1108.c
> +++ b/drivers/clk/rockchip/clk-rv1108.c
> @@ -140,7 +140,7 @@ enum rv1108_plls {
>   PNAME(mux_uart0_p)		= { "uart0_src", "uart0_frac", "xin24m" };
>   PNAME(mux_uart1_p)		= { "uart1_src", "uart1_frac", "xin24m" };
>   PNAME(mux_uart2_p)		= { "uart2_src", "uart2_frac", "xin24m" };
> -PNAME(mux_sclk_mac_p)	= { "ext_gmac", "sclk_mac_pre" };
> +PNAME(mux_sclk_mac_p)	= { "sclk_mac_pre", "ext_gmac" };
>   PNAME(mux_i2s0_pre_p)		= { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
>   PNAME(mux_i2s_out_p)		= { "i2s0_pre", "xin12m" };
>   PNAME(mux_i2s1_p)		= { "i2s1_src", "i2s1_frac", "dummy", "xin12m" };
> 

Acked-by: David Wu <david.wu@rock-chips.com>

[PATCH v2 1/4] clk: rockchip: add rv1108 ACLK_GAMC and PCLK_GMAC ID

[Heiko Stuebner]

Hi David,

Am Montag, 21. August 2017, 18:22:31 CEST schrieb David.Wu:
> Hi Elaine,
> 
> ? 2017/8/21 16:16, Elaine Zhang ??:
> > This patch exports gmac aclk and pclk for dts reference.
> > 
> > Signed-off-by: Elaine Zhang<zhangqing@rock-chips.com>
> > ---
> >   include/dt-bindings/clock/rv1108-cru.h | 2 ++
> >   1 file changed, 2 insertions(+)
> 
> Acked-by: David Wu <david.wu@rock-chips.com>

Acked-by is mainly meant for cross-maintainer stuff (changes
for one subsystem going through a different tree etc).

If you want to show that the change is correct and you have reviewed
the patch, please use "Reviewed-by".


Heiko

[PATCH v2 1/4] clk: rockchip: add rv1108 ACLK_GAMC and PCLK_GMAC ID

[David.Wu]

Hi Heiko,

? 2017/8/21 18:32, Heiko Stuebner ??:
> Hi David,
> 
> Am Montag, 21. August 2017, 18:22:31 CEST schrieb David.Wu:
>> Hi Elaine,
>>
>> ? 2017/8/21 16:16, Elaine Zhang ??:
>>> This patch exports gmac aclk and pclk for dts reference.
>>>
>>> Signed-off-by: Elaine Zhang<zhangqing@rock-chips.com>
>>> ---
>>>    include/dt-bindings/clock/rv1108-cru.h | 2 ++
>>>    1 file changed, 2 insertions(+)
>>
>> Acked-by: David Wu <david.wu@rock-chips.com>
> 
> Acked-by is mainly meant for cross-maintainer stuff (changes
> for one subsystem going through a different tree etc).
> 
> If you want to show that the change is correct and you have reviewed
> the patch, please use "Reviewed-by".
> 

Yeap, my intent is that the patches are correct. And change the tag here.?
So for the series:

Reviewed-by: David Wu <david.wu@rock-chips.com>

> 
> Heiko
> 
> 
> 

[PATCH v2 1/4] clk: rockchip: add rv1108 ACLK_GAMC and PCLK_GMAC ID

[Heiko Stuebner]

Am Montag, 21. August 2017, 16:16:04 CEST schrieb Elaine Zhang:
> This patch exports gmac aclk and pclk for dts reference.
> 
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

applied for 4.14


Thanks
Heiko

[PATCH v2 2/4] clk: rockchip: rv1108: add ACLK_GMAC and PCLK_GMAC clk id

[Heiko Stuebner]

Am Montag, 21. August 2017, 16:16:05 CEST schrieb Elaine Zhang:
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

applied for 4.14 after adapting the subject and adding a commit message


Heiko

[PATCH v2 3/4] clk: rockchip: rv1108: rename macphy to mac

[Heiko Stuebner]

Am Montag, 21. August 2017, 16:16:06 CEST schrieb Elaine Zhang:
> This MAC has no internal phy for rv1108.
> 
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

applied for 4.14 after adapting the subject and adding a sentence
to the commit message that this change is safe due to gmac not
being used yet.


Heiko

[PATCH v2 4/4] clk: rockchip: rv1108: fix up the clk_mac sel register description

[Heiko Stuebner]

Am Montag, 21. August 2017, 16:16:07 CEST schrieb Elaine Zhang:
> cru_sel24_con[8]
> rmii_extclk_sel
> clock source select control register
> 1'b0: from internal PLL
> 1'b1: from external IO
> 
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

applied for 4.14.


Thanks
Heiko