[PATCH 0/8] ARM: renesas: Latest r8a774[35] dts updates

[PATCH 0/8] ARM: renesas: Latest r8a774[35] dts updates

[Chris Paterson]

This series contains multiple additions to the r8a774[35] device trees.

I've bundled them into a series to help avoid merge issues due to multiple
changes to the same files. Hopefully this doesn't add too much confusion!


Kind regards, Chris


Fabrizio Castro (8):
  ARM: dts: r8a7745: Add APMU node and second CPU core
  ARM: dts: r8a7745: Add SDHI controllers
  ARM: dts: iwg22m: Enable SDHI1 controller
  ARM: dts: iwg22d: Enable SDHI0 controller
  ARM: dts: r8a7743: Add QSPI support
  ARM: dts: iwg20m: Add SPI NOR support
  ARM: dts: r8a7745: Add QSPI support
  ARM: drs: iwg22m: Add SPI NOR support

 arch/arm/boot/dts/r8a7743-iwg20m.dtsi       | 26 ++++++++++
 arch/arm/boot/dts/r8a7743.dtsi              | 17 +++++++
 arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 37 ++++++++++++++
 arch/arm/boot/dts/r8a7745-iwg22m.dtsi       | 43 +++++++++++++++++
 arch/arm/boot/dts/r8a7745.dtsi              | 75 +++++++++++++++++++++++++++++
 5 files changed, 198 insertions(+)

-- 
1.9.1

[PATCH 1/8] ARM: dts: r8a7745: Add APMU node and second CPU core

[Chris Paterson]

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Add DT node for the Advanced Power Management Unit (APMU), add the
second CPU core, and use "renesas,apmu" as "enable-method".

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
---
This patch is based on renesas-devel-20170913-v4.13.


 arch/arm/boot/dts/r8a7745.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index 6e82991..8ed2ac5 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -30,6 +30,7 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		enable-method = "renesas,apmu";
 
 		cpu0: cpu at 0 {
 			device_type = "cpu";
@@ -41,6 +42,15 @@
 			next-level-cache = <&L2_CA7>;
 		};
 
+		cpu1: cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <1>;
+			clock-frequency = <1000000000>;
+			power-domains = <&sysc R8A7745_PD_CA7_CPU1>;
+			next-level-cache = <&L2_CA7>;
+		};
+
 		L2_CA7: cache-controller-0 {
 			compatible = "cache";
 			cache-unified;
@@ -57,6 +67,12 @@
 		#size-cells = <2>;
 		ranges;
 
+		apmu at e6151000 {
+			compatible = "renesas,r8a7745-apmu", "renesas,apmu";
+			reg = <0 0xe6151000 0 0x188>;
+			cpus = <&cpu0 &cpu1>;
+		};
+
 		gic: interrupt-controller at f1001000 {
 			compatible = "arm,gic-400";
 			#interrupt-cells = <3>;
-- 
1.9.1

[PATCH 1/8] ARM: dts: r8a7745: Add APMU node and second CPU core

[Simon Horman]

[Cc Geert]

On Wed, Sep 13, 2017 at 06:05:34PM +0100, Chris Paterson wrote:
> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> 
> Add DT node for the Advanced Power Management Unit (APMU), add the
> second CPU core, and use "renesas,apmu" as "enable-method".
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
> ---
> This patch is based on renesas-devel-20170913-v4.13.

Hi,

with reference to "[PATCH v3 0/3] ARM: renesas: Enable SMP on R-Car E2"
is the CNTVOFF initialised in the boot loader of boards (in upstream)
for this SoC? If not I expect you will have trouble with the arch timer
on secondary CPU cores.

The patch itself looks good to me.

[PATCH 1/8] ARM: dts: r8a7745: Add APMU node and second CPU core

[Geert Uytterhoeven]

Hi Simon, Fabrizio,

On Fri, Sep 15, 2017 at 9:45 AM, Simon Horman <horms@verge.net.au> wrote:
> On Wed, Sep 13, 2017 at 06:05:34PM +0100, Chris Paterson wrote:
>> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>>
>> Add DT node for the Advanced Power Management Unit (APMU), add the
>> second CPU core, and use "renesas,apmu" as "enable-method".
>>
>> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
>> ---
>> This patch is based on renesas-devel-20170913-v4.13.
>
> Hi,
>
> with reference to "[PATCH v3 0/3] ARM: renesas: Enable SMP on R-Car E2"
> is the CNTVOFF initialised in the boot loader of boards (in upstream)
> for this SoC? If not I expect you will have trouble with the arch timer
> on secondary CPU cores.

Exactly my question.

Fabrizio: Given your feedback on "[PATCH v3 0/3] ARM: renesas: Enable SMP on
R-Car E2", I think SMP enablement on RZ/G1E has to be postponed until "ARM:
shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15" has been
accepted upstream.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 1/8] ARM: dts: r8a7745: Add APMU node and second CPU core

[Fabrizio Castro]

Hi Simon, Geert,

> -----Original Message-----
> From: linux-renesas-soc-owner at vger.kernel.org [mailto:linux-renesas-soc-owner at vger.kernel.org] On Behalf Of Geert
> Uytterhoeven
> Sent: 15 September 2017 09:05
> To: Simon Horman <horms@verge.net.au>; Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Cc: Chris Paterson <Chris.Paterson2@renesas.com>; Rob Herring <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>;
> Magnus Damm <magnus.damm@gmail.com>; Russell King <linux@armlinux.org.uk>; devicetree at vger.kernel.org; Linux-Renesas
> <linux-renesas-soc@vger.kernel.org>; linux-arm-kernel at lists.infradead.org; Geert Uytterhoeven <geert+renesas@glider.be>
> Subject: Re: [PATCH 1/8] ARM: dts: r8a7745: Add APMU node and second CPU core
>
> Hi Simon, Fabrizio,
>
> On Fri, Sep 15, 2017 at 9:45 AM, Simon Horman <horms@verge.net.au> wrote:
> > On Wed, Sep 13, 2017 at 06:05:34PM +0100, Chris Paterson wrote:
> >> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> >>
> >> Add DT node for the Advanced Power Management Unit (APMU), add the
> >> second CPU core, and use "renesas,apmu" as "enable-method".
> >>
> >> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> >> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
> >> ---
> >> This patch is based on renesas-devel-20170913-v4.13.
> >
> > Hi,
> >
> > with reference to "[PATCH v3 0/3] ARM: renesas: Enable SMP on R-Car E2"
> > is the CNTVOFF initialised in the boot loader of boards (in upstream)
> > for this SoC? If not I expect you will have trouble with the arch timer
> > on secondary CPU cores.

I can confirm that this patch relies on:
* "ARM: Add definition for monitor mode", and
* "ARM: shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15 "
as the bootloader doesn't initialize CNTVOFF.

>
> Exactly my question.
>
> Fabrizio: Given your feedback on "[PATCH v3 0/3] ARM: renesas: Enable SMP on
> R-Car E2", I think SMP enablement on RZ/G1E has to be postponed until "ARM:
> shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15" has been
> accepted upstream.

You are right, somehow we missed the comment made by Simon on Monday:

" I would like to deffer the third and last patch until v4.16 to avoid
an awkward branch dependency on the above - the branches are different
even though the tree is the same. Please resubmit this patch once the
above dependencies are present in an rc release, which at this stage
I expect to be v4.15-rc1."

Apologies for this, we will send this patch later on, once both patches have been
accepted upstream.

Simon, is this going to make the application of the remaining patches problematic?
Please, let me (or Chris) know if you want us to rebase and resend without this
patch.

Best regards,
Fabrizio

>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

[PATCH 1/8] ARM: dts: r8a7745: Add APMU node and second CPU core

[Simon Horman]

On Fri, Sep 15, 2017 at 08:57:53AM +0000, Fabrizio Castro wrote:
> Hi Simon, Geert,
> 
> > -----Original Message-----
> > From: linux-renesas-soc-owner at vger.kernel.org [mailto:linux-renesas-soc-owner at vger.kernel.org] On Behalf Of Geert
> > Uytterhoeven
> > Sent: 15 September 2017 09:05
> > To: Simon Horman <horms@verge.net.au>; Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Cc: Chris Paterson <Chris.Paterson2@renesas.com>; Rob Herring <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>;
> > Magnus Damm <magnus.damm@gmail.com>; Russell King <linux@armlinux.org.uk>; devicetree at vger.kernel.org; Linux-Renesas
> > <linux-renesas-soc@vger.kernel.org>; linux-arm-kernel at lists.infradead.org; Geert Uytterhoeven <geert+renesas@glider.be>
> > Subject: Re: [PATCH 1/8] ARM: dts: r8a7745: Add APMU node and second CPU core
> >
> > Hi Simon, Fabrizio,
> >
> > On Fri, Sep 15, 2017 at 9:45 AM, Simon Horman <horms@verge.net.au> wrote:
> > > On Wed, Sep 13, 2017 at 06:05:34PM +0100, Chris Paterson wrote:
> > >> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > >>
> > >> Add DT node for the Advanced Power Management Unit (APMU), add the
> > >> second CPU core, and use "renesas,apmu" as "enable-method".
> > >>
> > >> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > >> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
> > >> ---
> > >> This patch is based on renesas-devel-20170913-v4.13.
> > >
> > > Hi,
> > >
> > > with reference to "[PATCH v3 0/3] ARM: renesas: Enable SMP on R-Car E2"
> > > is the CNTVOFF initialised in the boot loader of boards (in upstream)
> > > for this SoC? If not I expect you will have trouble with the arch timer
> > > on secondary CPU cores.
> 
> I can confirm that this patch relies on:
> * "ARM: Add definition for monitor mode", and
> * "ARM: shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15 "
> as the bootloader doesn't initialize CNTVOFF.
> 
> >
> > Exactly my question.
> >
> > Fabrizio: Given your feedback on "[PATCH v3 0/3] ARM: renesas: Enable SMP on
> > R-Car E2", I think SMP enablement on RZ/G1E has to be postponed until "ARM:
> > shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15" has been
> > accepted upstream.
> 
> You are right, somehow we missed the comment made by Simon on Monday:
> 
> " I would like to deffer the third and last patch until v4.16 to avoid
> an awkward branch dependency on the above - the branches are different
> even though the tree is the same. Please resubmit this patch once the
> above dependencies are present in an rc release, which at this stage
> I expect to be v4.15-rc1."
> 
> Apologies for this, we will send this patch later on, once both patches have been
> accepted upstream.

No problem, I will mark this one as deferred.

> Simon, is this going to make the application of the remaining patches
> problematic?  Please, let me (or Chris) know if you want us to rebase and
> resend without this patch.

No, I don't think you need to rebase and repost due to this.

[PATCH 1/8] ARM: dts: r8a7745: Add APMU node and second CPU core

[Geert Uytterhoeven]

Hi Simon,

On Fri, Sep 15, 2017 at 1:06 PM, Simon Horman <horms@verge.net.au> wrote:
> On Fri, Sep 15, 2017 at 08:57:53AM +0000, Fabrizio Castro wrote:
>> > -----Original Message-----
>> > From: linux-renesas-soc-owner at vger.kernel.org [mailto:linux-renesas-soc-owner at vger.kernel.org] On Behalf Of Geert
>> > Uytterhoeven
>> > Sent: 15 September 2017 09:05
>> > To: Simon Horman <horms@verge.net.au>; Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>> > Cc: Chris Paterson <Chris.Paterson2@renesas.com>; Rob Herring <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>;
>> > Magnus Damm <magnus.damm@gmail.com>; Russell King <linux@armlinux.org.uk>; devicetree at vger.kernel.org; Linux-Renesas
>> > <linux-renesas-soc@vger.kernel.org>; linux-arm-kernel at lists.infradead.org; Geert Uytterhoeven <geert+renesas@glider.be>
>> > Subject: Re: [PATCH 1/8] ARM: dts: r8a7745: Add APMU node and second CPU core
>> >
>> > Hi Simon, Fabrizio,
>> >
>> > On Fri, Sep 15, 2017 at 9:45 AM, Simon Horman <horms@verge.net.au> wrote:
>> > > On Wed, Sep 13, 2017 at 06:05:34PM +0100, Chris Paterson wrote:
>> > >> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>> > >>
>> > >> Add DT node for the Advanced Power Management Unit (APMU), add the
>> > >> second CPU core, and use "renesas,apmu" as "enable-method".
>> > >>
>> > >> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>> > >> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
>> > >> ---
>> > >> This patch is based on renesas-devel-20170913-v4.13.
>> > >
>> > > Hi,
>> > >
>> > > with reference to "[PATCH v3 0/3] ARM: renesas: Enable SMP on R-Car E2"
>> > > is the CNTVOFF initialised in the boot loader of boards (in upstream)
>> > > for this SoC? If not I expect you will have trouble with the arch timer
>> > > on secondary CPU cores.
>>
>> I can confirm that this patch relies on:
>> * "ARM: Add definition for monitor mode", and
>> * "ARM: shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15 "
>> as the bootloader doesn't initialize CNTVOFF.
>>
>> >
>> > Exactly my question.
>> >
>> > Fabrizio: Given your feedback on "[PATCH v3 0/3] ARM: renesas: Enable SMP on
>> > R-Car E2", I think SMP enablement on RZ/G1E has to be postponed until "ARM:
>> > shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15" has been
>> > accepted upstream.
>>
>> You are right, somehow we missed the comment made by Simon on Monday:
>>
>> " I would like to deffer the third and last patch until v4.16 to avoid
>> an awkward branch dependency on the above - the branches are different
>> even though the tree is the same. Please resubmit this patch once the
>> above dependencies are present in an rc release, which at this stage
>> I expect to be v4.15-rc1."
>>
>> Apologies for this, we will send this patch later on, once both patches have been
>> accepted upstream.
>
> No problem, I will mark this one as deferred.

As the dependency is in v4.15-rc1, it can be applied now.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 1/8] ARM: dts: r8a7745: Add APMU node and second CPU core

[Fabrizio Castro]

Hello Geert, Simon,

>
> As the dependency is in v4.15-rc1, it can be applied now.
>

we thought exactly the same thing, therefore we rebased and we re-ran our tests, to discover that something broke in between versions.
I'll be in touch once I have more information, but it's a no go for now.

Thanks,
Fab


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This Christmas, instead of sending out cards, Renesas Electronics Europe have decided to support Unicef with a donation. For further details click here<https://www.unicef.org/> to find out about the valuable work they do, helping children all over the world.
We would like to take this opportunity to wish you a Merry Christmas and a prosperous New Year.



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

[PATCH 1/8] ARM: dts: r8a7745: Add APMU node and second CPU core

[Fabrizio Castro]

Hello Geert, Simon,

the problems I am seeing are not related to APMU/SMP, I'll send a v2 shortly.

Thanks,
Fab

>
> Hello Geert, Simon,
>
> >
> > As the dependency is in v4.15-rc1, it can be applied now.
> >
>
> we thought exactly the same thing, therefore we rebased and we re-ran our tests, to discover that something broke in between
> versions.
> I'll be in touch once I have more information, but it's a no go for now.
>
> Thanks,
> Fab
>
>
> [https://www2.renesas.eu/media/email/unicef_2017.jpg]
>
> This Christmas, instead of sending out cards, Renesas Electronics Europe have decided to support Unicef with a donation. For further
> details click here<https://www.unicef.org/> to find out about the valuable work they do, helping children all over the world.
> We would like to take this opportunity to wish you a Merry Christmas and a prosperous New Year.
>
>
>
> Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England &
> Wales under Registered No. 04586709.


[https://www2.renesas.eu/media/email/unicef_2017.jpg]

This Christmas, instead of sending out cards, Renesas Electronics Europe have decided to support Unicef with a donation. For further details click here<https://www.unicef.org/> to find out about the valuable work they do, helping children all over the world.
We would like to take this opportunity to wish you a Merry Christmas and a prosperous New Year.



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

[PATCH 1/8] ARM: dts: r8a7745: Add APMU node and second CPU core

[Geert Uytterhoeven]

On Wed, Sep 13, 2017 at 7:05 PM, Chris Paterson
<chris.paterson2@renesas.com> wrote:
> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>
> Add DT node for the Advanced Power Management Unit (APMU), add the
> second CPU core, and use "renesas,apmu" as "enable-method".
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 2/8] ARM: dts: r8a7745: Add SDHI controllers

[Chris Paterson]

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Add the SDHI controllers to the r8a7745 device tree.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
---
This patch is based on renesas-devel-20170913-v4.13.

This patch is dependant on:
- "dt-bindings: mmc: sh_mmcif: Document r8a7745 DT bindings"


 arch/arm/boot/dts/r8a7745.dtsi | 42 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index 8ed2ac5..37c0fac 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -751,6 +751,48 @@
 			max-frequency = <97500000>;
 			status = "disabled";
 		};
+
+		sdhi0: sd at ee100000 {
+			compatible = "renesas,sdhi-r8a7745";
+			reg = <0 0xee100000 0 0x328>;
+			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 314>;
+			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+			       <&dmac1 0xcd>, <&dmac1 0xce>;
+			dma-names = "tx", "rx", "tx", "rx";
+			max-frequency = <195000000>;
+			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+			resets = <&cpg 314>;
+			status = "disabled";
+		};
+
+		sdhi1: sd at ee140000 {
+			compatible = "renesas,sdhi-r8a7745";
+			reg = <0 0xee140000 0 0x100>;
+			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 312>;
+			dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+			       <&dmac1 0xc1>, <&dmac1 0xc2>;
+			dma-names = "tx", "rx", "tx", "rx";
+			max-frequency = <97500000>;
+			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+			resets = <&cpg 312>;
+			status = "disabled";
+		};
+
+		sdhi2: sd at ee160000 {
+			compatible = "renesas,sdhi-r8a7745";
+			reg = <0 0xee160000 0 0x100>;
+			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 311>;
+			dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+			       <&dmac1 0xd3>, <&dmac1 0xd4>;
+			dma-names = "tx", "rx", "tx", "rx";
+			max-frequency = <97500000>;
+			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+			resets = <&cpg 311>;
+			status = "disabled";
+		};
 	};
 
 	/* External root clock */
-- 
1.9.1

[PATCH 2/8] ARM: dts: r8a7745: Add SDHI controllers

[Simon Horman]

On Wed, Sep 13, 2017 at 06:05:35PM +0100, Chris Paterson wrote:
> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> 
> Add the SDHI controllers to the r8a7745 device tree.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>

Thanks, applied.

> ---
> This patch is based on renesas-devel-20170913-v4.13.
> 
> This patch is dependant on:
> - "dt-bindings: mmc: sh_mmcif: Document r8a7745 DT bindings"

I think that should be "[PATCH v3] mmc: renesas_sdhi: Add r8a7743/5 support"

[PATCH 2/8] ARM: dts: r8a7745: Add SDHI controllers

[Chris Paterson]

> From: Simon Horman [mailto:horms at verge.net.au]
> Sent: 15 September 2017 08:54
> 
> On Wed, Sep 13, 2017 at 06:05:35PM +0100, Chris Paterson wrote:
> > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> >
> > Add the SDHI controllers to the r8a7745 device tree.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
> 
> Thanks, applied.

Thank you!

> 
> > ---
> > This patch is based on renesas-devel-20170913-v4.13.
> >
> > This patch is dependant on:
> > - "dt-bindings: mmc: sh_mmcif: Document r8a7745 DT bindings"
> 
> I think that should be "[PATCH v3] mmc: renesas_sdhi: Add r8a7743/5
> support"

Correct. Sorry for the confusion!

[PATCH 3/8] ARM: dts: iwg22m: Enable SDHI1 controller

[Chris Paterson]

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Enable the SDHI1 controller on iWave RZ/G1E SoM.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
---
This patch is based on renesas-devel-20170913-v4.13.


 arch/arm/boot/dts/r8a7745-iwg22m.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
index e306e7c..f7f9cef 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
+++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
@@ -9,6 +9,7 @@
  */
 
 #include "r8a7745.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	compatible = "iwave,g22m", "renesas,r8a7745";
@@ -38,6 +39,12 @@
 		function = "mmc";
 	};
 
+	sdhi1_pins: sd1 {
+		groups = "sdhi1_data4", "sdhi1_ctrl";
+		function = "sdhi1";
+		power-source = <3300>;
+	};
+
 	i2c3_pins: i2c3 {
 		groups = "i2c3_b";
 		function = "i2c3";
@@ -54,6 +61,16 @@
 	status = "okay";
 };
 
+&sdhi1 {
+	pinctrl-0 = <&sdhi1_pins>;
+	pinctrl-names = "default";
+
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_3p3v>;
+	cd-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
 &i2c3 {
 	pinctrl-0 = <&i2c3_pins>;
 	pinctrl-names = "default";
-- 
1.9.1

[PATCH 3/8] ARM: dts: iwg22m: Enable SDHI1 controller

[Simon Horman]

On Wed, Sep 13, 2017 at 06:05:36PM +0100, Chris Paterson wrote:
> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> 
> Enable the SDHI1 controller on iWave RZ/G1E SoM.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
> ---
> This patch is based on renesas-devel-20170913-v4.13.
> 
> 
>  arch/arm/boot/dts/r8a7745-iwg22m.dtsi | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
> index e306e7c..f7f9cef 100644
> --- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
> +++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
> @@ -9,6 +9,7 @@
>   */
>  
>  #include "r8a7745.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
>  
>  / {
>  	compatible = "iwave,g22m", "renesas,r8a7745";
> @@ -38,6 +39,12 @@
>  		function = "mmc";
>  	};
>  
> +	sdhi1_pins: sd1 {
> +		groups = "sdhi1_data4", "sdhi1_ctrl";
> +		function = "sdhi1";
> +		power-source = <3300>;
> +	};
> +
>  	i2c3_pins: i2c3 {
>  		groups = "i2c3_b";
>  		function = "i2c3";
> @@ -54,6 +61,16 @@
>  	status = "okay";
>  };
>  
> +&sdhi1 {
> +	pinctrl-0 = <&sdhi1_pins>;
> +	pinctrl-names = "default";
> +
> +	vmmc-supply = <&reg_3p3v>;
> +	vqmmc-supply = <&reg_3p3v>;
> +	cd-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;

No wp-gpios property means this is a ?SD slot, right?

Do you have any plans to enable sdr-50 and sdr-104?
Is it not supported for some reason?

I don't mind if its not enabled in this patch but I would like to
know if it can be enabled or not and reflect that information in the wiki.

http://elinux.org/index.php?title=Renesas-MMC-Enabled-Speeds

> +	status = "okay";
> +};
> +
>  &i2c3 {
>  	pinctrl-0 = <&i2c3_pins>;
>  	pinctrl-names = "default";
> -- 
> 1.9.1
> 

[PATCH 3/8] ARM: dts: iwg22m: Enable SDHI1 controller

[Geert Uytterhoeven]

On Fri, Sep 15, 2017 at 10:11 AM, Simon Horman <horms@verge.net.au> wrote:
> On Wed, Sep 13, 2017 at 06:05:36PM +0100, Chris Paterson wrote:
>> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>>
>> Enable the SDHI1 controller on iWave RZ/G1E SoM.
>>
>> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

>> --- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
>> +++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi

>> @@ -54,6 +61,16 @@
>>       status = "okay";
>>  };
>>
>> +&sdhi1 {
>> +     pinctrl-0 = <&sdhi1_pins>;
>> +     pinctrl-names = "default";
>> +
>> +     vmmc-supply = <&reg_3p3v>;
>> +     vqmmc-supply = <&reg_3p3v>;
>> +     cd-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
>
> No wp-gpios property means this is a ?SD slot, right?

Correct.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 3/8] ARM: dts: iwg22m: Enable SDHI1 controller

[Chris Paterson]

Hello Simon,

> From: devicetree-owner at vger.kernel.org [mailto:devicetree-
> owner at vger.kernel.org] On Behalf Of Simon Horman
> Sent: 15 September 2017 09:12
> To: Chris Paterson <Chris.Paterson2@renesas.com>
> 
> On Wed, Sep 13, 2017 at 06:05:36PM +0100, Chris Paterson wrote:
> > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> >
> > Enable the SDHI1 controller on iWave RZ/G1E SoM.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
> > ---
> > This patch is based on renesas-devel-20170913-v4.13.
> >
> >
> >  arch/arm/boot/dts/r8a7745-iwg22m.dtsi | 17 +++++++++++++++++
> >  1 file changed, 17 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
> > b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
> > index e306e7c..f7f9cef 100644
> > --- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
> > +++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
> > @@ -9,6 +9,7 @@
> >   */
> >
> >  #include "r8a7745.dtsi"
> > +#include <dt-bindings/gpio/gpio.h>
> >
> >  / {
> >  	compatible = "iwave,g22m", "renesas,r8a7745"; @@ -38,6 +39,12
> @@
> >  		function = "mmc";
> >  	};
> >
> > +	sdhi1_pins: sd1 {
> > +		groups = "sdhi1_data4", "sdhi1_ctrl";
> > +		function = "sdhi1";
> > +		power-source = <3300>;
> > +	};
> > +
> >  	i2c3_pins: i2c3 {
> >  		groups = "i2c3_b";
> >  		function = "i2c3";
> > @@ -54,6 +61,16 @@
> >  	status = "okay";
> >  };
> >
> > +&sdhi1 {
> > +	pinctrl-0 = <&sdhi1_pins>;
> > +	pinctrl-names = "default";
> > +
> > +	vmmc-supply = <&reg_3p3v>;
> > +	vqmmc-supply = <&reg_3p3v>;
> > +	cd-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
> 
> No wp-gpios property means this is a ?SD slot, right?

Correct

> 
> Do you have any plans to enable sdr-50 and sdr-104?
> Is it not supported for some reason?

Nope (unless the hardware changes down the line).
Both vmmc and vqmmc are fixed to 3V3 on the iWave-E SOM module.

Kind regards, Chris


> 
> I don't mind if its not enabled in this patch but I would like to know if it can be
> enabled or not and reflect that information in the wiki.
> 
> http://elinux.org/index.php?title=Renesas-MMC-Enabled-Speeds
> 
> > +	status = "okay";
> > +};
> > +
> >  &i2c3 {
> >  	pinctrl-0 = <&i2c3_pins>;
> >  	pinctrl-names = "default";
> > --
> > 1.9.1
> >
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in the
> body of a message to majordomo at vger.kernel.org More majordomo info at
> http://vger.kernel.org/majordomo-info.html

[PATCH 3/8] ARM: dts: iwg22m: Enable SDHI1 controller

[Simon Horman]

On Wed, Sep 20, 2017 at 01:05:07PM +0000, Chris Paterson wrote:
> Hello Simon,
> 
> > From: devicetree-owner at vger.kernel.org [mailto:devicetree-
> > owner at vger.kernel.org] On Behalf Of Simon Horman
> > Sent: 15 September 2017 09:12
> > To: Chris Paterson <Chris.Paterson2@renesas.com>
> > 
> > On Wed, Sep 13, 2017 at 06:05:36PM +0100, Chris Paterson wrote:
> > > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > >
> > > Enable the SDHI1 controller on iWave RZ/G1E SoM.
> > >
> > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
> > > ---
> > > This patch is based on renesas-devel-20170913-v4.13.
> > >
> > >
> > >  arch/arm/boot/dts/r8a7745-iwg22m.dtsi | 17 +++++++++++++++++
> > >  1 file changed, 17 insertions(+)
> > >
> > > diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
> > > b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
> > > index e306e7c..f7f9cef 100644
> > > --- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
> > > +++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
> > > @@ -9,6 +9,7 @@
> > >   */
> > >
> > >  #include "r8a7745.dtsi"
> > > +#include <dt-bindings/gpio/gpio.h>
> > >
> > >  / {
> > >  	compatible = "iwave,g22m", "renesas,r8a7745"; @@ -38,6 +39,12
> > @@
> > >  		function = "mmc";
> > >  	};
> > >
> > > +	sdhi1_pins: sd1 {
> > > +		groups = "sdhi1_data4", "sdhi1_ctrl";
> > > +		function = "sdhi1";
> > > +		power-source = <3300>;
> > > +	};
> > > +
> > >  	i2c3_pins: i2c3 {
> > >  		groups = "i2c3_b";
> > >  		function = "i2c3";
> > > @@ -54,6 +61,16 @@
> > >  	status = "okay";
> > >  };
> > >
> > > +&sdhi1 {
> > > +	pinctrl-0 = <&sdhi1_pins>;
> > > +	pinctrl-names = "default";
> > > +
> > > +	vmmc-supply = <&reg_3p3v>;
> > > +	vqmmc-supply = <&reg_3p3v>;
> > > +	cd-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
> > 
> > No wp-gpios property means this is a ?SD slot, right?
> 
> Correct
> 
> > 
> > Do you have any plans to enable sdr-50 and sdr-104?
> > Is it not supported for some reason?
> 
> Nope (unless the hardware changes down the line).
> Both vmmc and vqmmc are fixed to 3V3 on the iWave-E SOM module.

Thanks, got it.

[PATCH 3/8] ARM: dts: iwg22m: Enable SDHI1 controller

[Simon Horman]

On Thu, Sep 21, 2017 at 10:31:16AM +0200, Simon Horman wrote:
> On Wed, Sep 20, 2017 at 01:05:07PM +0000, Chris Paterson wrote:
> > Hello Simon,
> > 
> > > From: devicetree-owner at vger.kernel.org [mailto:devicetree-
> > > owner at vger.kernel.org] On Behalf Of Simon Horman
> > > Sent: 15 September 2017 09:12
> > > To: Chris Paterson <Chris.Paterson2@renesas.com>
> > > 
> > > On Wed, Sep 13, 2017 at 06:05:36PM +0100, Chris Paterson wrote:
> > > > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > >
> > > > Enable the SDHI1 controller on iWave RZ/G1E SoM.
> > > >
> > > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > > Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
> > > > ---
> > > > This patch is based on renesas-devel-20170913-v4.13.
> > > >
> > > >
> > > >  arch/arm/boot/dts/r8a7745-iwg22m.dtsi | 17 +++++++++++++++++
> > > >  1 file changed, 17 insertions(+)
> > > >
> > > > diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
> > > > b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
> > > > index e306e7c..f7f9cef 100644
> > > > --- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
> > > > +++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
> > > > @@ -9,6 +9,7 @@
> > > >   */
> > > >
> > > >  #include "r8a7745.dtsi"
> > > > +#include <dt-bindings/gpio/gpio.h>
> > > >
> > > >  / {
> > > >  	compatible = "iwave,g22m", "renesas,r8a7745"; @@ -38,6 +39,12
> > > @@
> > > >  		function = "mmc";
> > > >  	};
> > > >
> > > > +	sdhi1_pins: sd1 {
> > > > +		groups = "sdhi1_data4", "sdhi1_ctrl";
> > > > +		function = "sdhi1";
> > > > +		power-source = <3300>;
> > > > +	};
> > > > +
> > > >  	i2c3_pins: i2c3 {
> > > >  		groups = "i2c3_b";
> > > >  		function = "i2c3";
> > > > @@ -54,6 +61,16 @@
> > > >  	status = "okay";
> > > >  };
> > > >
> > > > +&sdhi1 {
> > > > +	pinctrl-0 = <&sdhi1_pins>;
> > > > +	pinctrl-names = "default";
> > > > +
> > > > +	vmmc-supply = <&reg_3p3v>;
> > > > +	vqmmc-supply = <&reg_3p3v>;
> > > > +	cd-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
> > > 
> > > No wp-gpios property means this is a ?SD slot, right?
> > 
> > Correct
> > 
> > > 
> > > Do you have any plans to enable sdr-50 and sdr-104?
> > > Is it not supported for some reason?
> > 
> > Nope (unless the hardware changes down the line).
> > Both vmmc and vqmmc are fixed to 3V3 on the iWave-E SOM module.
> 
> Thanks, got it.

Thanks for the clarification above, I have applied this patch.

[PATCH 3/8] ARM: dts: iwg22m: Enable SDHI1 controller

[Chris Paterson]

> From: Chris Paterson
> Sent: 20 September 2017 14:05

> 
> >
> > I don't mind if its not enabled in this patch but I would like to know
> > if it can be enabled or not and reflect that information in the wiki.
> >
> > http://elinux.org/index.php?title=Renesas-MMC-Enabled-Speeds

Will do.

Chris

[PATCH 3/8] ARM: dts: iwg22m: Enable SDHI1 controller

[Simon Horman]

On Wed, Sep 20, 2017 at 01:06:30PM +0000, Chris Paterson wrote:
> 
> > From: Chris Paterson
> > Sent: 20 September 2017 14:05
> 
> > 
> > >
> > > I don't mind if its not enabled in this patch but I would like to know
> > > if it can be enabled or not and reflect that information in the wiki.
> > >
> > > http://elinux.org/index.php?title=Renesas-MMC-Enabled-Speeds
> 
> Will do.

Thanks.

[PATCH 4/8] ARM: dts: iwg22d: Enable SDHI0 controller

[Chris Paterson]

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Enable the SDHI0 controller on iWave RZ/G1E carrier board.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
---
This patch is based on renesas-devel-20170913-v4.13.


 arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 37 +++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
index aac84c6..c34dbe7 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
@@ -24,6 +24,19 @@
 		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
 		stdout-path = "serial0:115200n8";
 	};
+
+	vccq_sdhi0: regulator-vccq-sdhi0 {
+		compatible = "regulator-gpio";
+
+		regulator-name = "SDHI0 VccQ";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
+		gpios-states = <1>;
+		states = <3300000 1
+			  1800000 0>;
+	};
 };
 
 &pfc {
@@ -36,6 +49,18 @@
 		groups = "avb_mdio", "avb_gmii";
 		function = "avb";
 	};
+
+	sdhi0_pins: sd0 {
+		groups = "sdhi0_data4", "sdhi0_ctrl";
+		function = "sdhi0";
+		power-source = <3300>;
+	};
+
+	sdhi0_pins_uhs: sd0_uhs {
+		groups = "sdhi0_data4", "sdhi0_ctrl";
+		function = "sdhi0";
+		power-source = <1800>;
+	};
 };
 
 &scif4 {
@@ -63,3 +88,15 @@
 		micrel,led-mode = <1>;
 	};
 };
+
+&sdhi0 {
+	pinctrl-0 = <&sdhi0_pins>;
+	pinctrl-1 = <&sdhi0_pins_uhs>;
+	pinctrl-names = "default", "state_uhs";
+
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&vccq_sdhi0>;
+	cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
+	sd-uhs-sdr104;
+	status = "okay";
+};
-- 
1.9.1

[PATCH 4/8] ARM: dts: iwg22d: Enable SDHI0 controller

[Simon Horman]

On Wed, Sep 13, 2017 at 06:05:37PM +0100, Chris Paterson wrote:
> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> 
> Enable the SDHI0 controller on iWave RZ/G1E carrier board.

...

> @@ -63,3 +88,15 @@
>  		micrel,led-mode = <1>;
>  	};
>  };
> +
> +&sdhi0 {
> +	pinctrl-0 = <&sdhi0_pins>;
> +	pinctrl-1 = <&sdhi0_pins_uhs>;
> +	pinctrl-names = "default", "state_uhs";
> +
> +	vmmc-supply = <&reg_3p3v>;
> +	vqmmc-supply = <&vccq_sdhi0>;
> +	cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;

I take that the absence of a wp-gpio means that that this is a ?SD slot.
Could you help me by documenting this correctly on
http://elinux.org/index.php?title=Renesas-MMC-Enabled-Speeds ?

For some reason I thought that SDHI0 wasn't exposed at all, so I guess
my reading of the documentation was incorrect.


I think you also want sd-uhs-sdr50 here too.
You can test it by removing the sd-uhs-sdr104 property.

> +	sd-uhs-sdr104;
> +	status = "okay";
> +};
> -- 
> 1.9.1
> 

[PATCH 4/8] ARM: dts: iwg22d: Enable SDHI0 controller

[Fabrizio Castro]

Hi Simon,

Apologies for the delay in getting back to you.

> -----Original Message-----
> From: Simon Horman [mailto:horms at verge.net.au]
> Sent: 15 September 2017 09:06
> To: Chris Paterson <Chris.Paterson2@renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>; Magnus Damm <magnus.damm@gmail.com>;
> Russell King <linux@armlinux.org.uk>; Fabrizio Castro <fabrizio.castro@bp.renesas.com>; devicetree at vger.kernel.org; linux-renesas-
> soc at vger.kernel.org; linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH 4/8] ARM: dts: iwg22d: Enable SDHI0 controller
>
> On Wed, Sep 13, 2017 at 06:05:37PM +0100, Chris Paterson wrote:
> > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> >
> > Enable the SDHI0 controller on iWave RZ/G1E carrier board.
>
> ...
>
> > @@ -63,3 +88,15 @@
> >  micrel,led-mode = <1>;
> >  };
> >  };
> > +
> > +&sdhi0 {
> > +pinctrl-0 = <&sdhi0_pins>;
> > +pinctrl-1 = <&sdhi0_pins_uhs>;
> > +pinctrl-names = "default", "state_uhs";
> > +
> > +vmmc-supply = <&reg_3p3v>;
> > +vqmmc-supply = <&vccq_sdhi0>;
> > +cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
>
> I take that the absence of a wp-gpio means that that this is a ?SD slot.
> Could you help me by documenting this correctly on
> http://elinux.org/index.php?title=Renesas-MMC-Enabled-Speeds ?
>
> For some reason I thought that SDHI0 wasn't exposed at all, so I guess
> my reading of the documentation was incorrect.
>
>
> I think you also want sd-uhs-sdr50 here too.
> You can test it by removing the sd-uhs-sdr104 property.

Whilst playing with uhs properties I have noticed that with the version of the DT I was using I couldn't put sdhi0 into an uhs mode and that was down to the fact that the driver wasn't driving the regulator to 1.8V. This happens because (in my case) the power regulator gets probed after the sdhi does, and the sdhi code doesn't seem to deal with it. Am I the only one with this problem or is it a known problem?

Thanks,
Fabrizio

>
> > +sd-uhs-sdr104;
> > +status = "okay";
> > +};
> > --
> > 1.9.1
> >



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

[PATCH 4/8] ARM: dts: iwg22d: Enable SDHI0 controller

[Fabrizio Castro]

Hello Simon, Geert

thank you for your patience on this one. We found out that there is an HW issue on SDHI0 , SDHC_CD# and SDHC_CMD (on the carrier board) are pulled up to 3.3V, therefore we are dropping UHS on this interface, and as result we are dropping this patch. We will send a V2 shortly.

Thanks,
Fabrizio

> -----Original Message-----
> From: Simon Horman [mailto:horms at verge.net.au]
> Sent: 15 September 2017 09:06
> To: Chris Paterson <Chris.Paterson2@renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>; Magnus Damm <magnus.damm@gmail.com>;
> Russell King <linux@armlinux.org.uk>; Fabrizio Castro <fabrizio.castro@bp.renesas.com>; devicetree at vger.kernel.org; linux-renesas-
> soc at vger.kernel.org; linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH 4/8] ARM: dts: iwg22d: Enable SDHI0 controller
>
> On Wed, Sep 13, 2017 at 06:05:37PM +0100, Chris Paterson wrote:
> > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> >
> > Enable the SDHI0 controller on iWave RZ/G1E carrier board.
>
> ...
>
> > @@ -63,3 +88,15 @@
> >  micrel,led-mode = <1>;
> >  };
> >  };
> > +
> > +&sdhi0 {
> > +pinctrl-0 = <&sdhi0_pins>;
> > +pinctrl-1 = <&sdhi0_pins_uhs>;
> > +pinctrl-names = "default", "state_uhs";
> > +
> > +vmmc-supply = <&reg_3p3v>;
> > +vqmmc-supply = <&vccq_sdhi0>;
> > +cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
>
> I take that the absence of a wp-gpio means that that this is a ?SD slot.
> Could you help me by documenting this correctly on
> http://elinux.org/index.php?title=Renesas-MMC-Enabled-Speeds ?
>
> For some reason I thought that SDHI0 wasn't exposed at all, so I guess
> my reading of the documentation was incorrect.
>
>
> I think you also want sd-uhs-sdr50 here too.
> You can test it by removing the sd-uhs-sdr104 property.
>
> > +sd-uhs-sdr104;
> > +status = "okay";
> > +};
> > --
> > 1.9.1
> >



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

[PATCH 4/8] ARM: dts: iwg22d: Enable SDHI0 controller

[Geert Uytterhoeven]

On Wed, Sep 13, 2017 at 7:05 PM, Chris Paterson
<chris.paterson2@renesas.com> wrote:
> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>
> Enable the SDHI0 controller on iWave RZ/G1E carrier board.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 4/8] ARM: dts: iwg22d: Enable SDHI0 controller

[Simon Horman]

On Wed, Sep 20, 2017 at 01:40:20PM +0200, Geert Uytterhoeven wrote:
> On Wed, Sep 13, 2017 at 7:05 PM, Chris Paterson
> <chris.paterson2@renesas.com> wrote:
> > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> >
> > Enable the SDHI0 controller on iWave RZ/G1E carrier board.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
> 
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Thanks, applied.

[PATCH 4/8] ARM: dts: iwg22d: Enable SDHI0 controller

[Simon Horman]

On Thu, Sep 21, 2017 at 10:38:40AM +0200, Simon Horman wrote:
> On Wed, Sep 20, 2017 at 01:40:20PM +0200, Geert Uytterhoeven wrote:
> > On Wed, Sep 13, 2017 at 7:05 PM, Chris Paterson
> > <chris.paterson2@renesas.com> wrote:
> > > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > >
> > > Enable the SDHI0 controller on iWave RZ/G1E carrier board.
> > >
> > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
> > 
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> 
> Thanks, applied.

Sorry, I somehow overlooked Fabrizio's comments.
I have dropped this patch for now.

[PATCH 4/8] ARM: dts: iwg22d: Enable SDHI0 controller

[Fabrizio Castro]

Hello Simon,

> -----Original Message-----
> From: Simon Horman [mailto:horms at verge.net.au]
> Sent: 21 September 2017 09:42
> To: Geert Uytterhoeven <geert@linux-m68k.org>
> Cc: Chris Paterson <Chris.Paterson2@renesas.com>; Rob Herring <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>;
> Magnus Damm <magnus.damm@gmail.com>; Russell King <linux@armlinux.org.uk>; Fabrizio Castro
> <fabrizio.castro@bp.renesas.com>; devicetree at vger.kernel.org; Linux-Renesas <linux-renesas-soc@vger.kernel.org>; linux-arm-
> kernel at lists.infradead.org
> Subject: Re: [PATCH 4/8] ARM: dts: iwg22d: Enable SDHI0 controller
>
> On Thu, Sep 21, 2017 at 10:38:40AM +0200, Simon Horman wrote:
> > On Wed, Sep 20, 2017 at 01:40:20PM +0200, Geert Uytterhoeven wrote:
> > > On Wed, Sep 13, 2017 at 7:05 PM, Chris Paterson
> > > <chris.paterson2@renesas.com> wrote:
> > > > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > >
> > > > Enable the SDHI0 controller on iWave RZ/G1E carrier board.
> > > >
> > > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > > Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
> > >
> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> >
> > Thanks, applied.
>
> Sorry, I somehow overlooked Fabrizio's comments.
> I have dropped this patch for now.

Thank you for doing this.
We are working on a new patch now, I'll submit a V2 as soon as it is ready.
Just to recap (all in one place), we found an HW issue and a SW one preventing SDHI0 from working properly at UHS SDR50 and SDR104, therefore we need a new patch to limit the speed of this interface.

Thanks,
Fabrizio





Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

[PATCH 4/8] ARM: dts: iwg22d: Enable SDHI0 controller

[Simon Horman]

On Thu, Sep 21, 2017 at 08:53:00AM +0000, Fabrizio Castro wrote:
> Hello Simon,
> 
> > -----Original Message-----
> > From: Simon Horman [mailto:horms at verge.net.au]
> > Sent: 21 September 2017 09:42
> > To: Geert Uytterhoeven <geert@linux-m68k.org>
> > Cc: Chris Paterson <Chris.Paterson2@renesas.com>; Rob Herring <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>;
> > Magnus Damm <magnus.damm@gmail.com>; Russell King <linux@armlinux.org.uk>; Fabrizio Castro
> > <fabrizio.castro@bp.renesas.com>; devicetree at vger.kernel.org; Linux-Renesas <linux-renesas-soc@vger.kernel.org>; linux-arm-
> > kernel at lists.infradead.org
> > Subject: Re: [PATCH 4/8] ARM: dts: iwg22d: Enable SDHI0 controller
> >
> > On Thu, Sep 21, 2017 at 10:38:40AM +0200, Simon Horman wrote:
> > > On Wed, Sep 20, 2017 at 01:40:20PM +0200, Geert Uytterhoeven wrote:
> > > > On Wed, Sep 13, 2017 at 7:05 PM, Chris Paterson
> > > > <chris.paterson2@renesas.com> wrote:
> > > > > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > > >
> > > > > Enable the SDHI0 controller on iWave RZ/G1E carrier board.
> > > > >
> > > > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > > > Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
> > > >
> > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > >
> > > Thanks, applied.
> >
> > Sorry, I somehow overlooked Fabrizio's comments.
> > I have dropped this patch for now.
> 
> Thank you for doing this.
> We are working on a new patch now, I'll submit a V2 as soon as it is ready.
> Just to recap (all in one place), we found an HW issue and a SW one preventing SDHI0 from working properly at UHS SDR50 and SDR104, therefore we need a new patch to limit the speed of this interface.

Thanks for catching this, UHS can be quite troublesome in my experience.

[PATCH 4/8] ARM: dts: iwg22d: Enable SDHI0 controller

[Chris Paterson]

> From: Simon Horman [mailto:horms at verge.net.au]
> Sent: 21 September 2017 10:04
> 
> On Thu, Sep 21, 2017 at 08:53:00AM +0000, Fabrizio Castro wrote:
> > Hello Simon,
> >
> > > -----Original Message-----
> > > From: Simon Horman [mailto:horms at verge.net.au]
> > > Sent: 21 September 2017 09:42
> > > To: Geert Uytterhoeven <geert@linux-m68k.org>
> > > Cc: Chris Paterson <Chris.Paterson2@renesas.com>; Rob Herring
> > > <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>;
> Magnus
> > > Damm <magnus.damm@gmail.com>; Russell King
> <linux@armlinux.org.uk>;
> > > Fabrizio Castro <fabrizio.castro@bp.renesas.com>;
> > > devicetree at vger.kernel.org; Linux-Renesas
> > > <linux-renesas-soc@vger.kernel.org>; linux-arm-
> > > kernel at lists.infradead.org
> > > Subject: Re: [PATCH 4/8] ARM: dts: iwg22d: Enable SDHI0 controller
> > >
> > > On Thu, Sep 21, 2017 at 10:38:40AM +0200, Simon Horman wrote:
> > > > On Wed, Sep 20, 2017 at 01:40:20PM +0200, Geert Uytterhoeven wrote:
> > > > > On Wed, Sep 13, 2017 at 7:05 PM, Chris Paterson
> > > > > <chris.paterson2@renesas.com> wrote:
> > > > > > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > > > >
> > > > > > Enable the SDHI0 controller on iWave RZ/G1E carrier board.
> > > > > >
> > > > > > Signed-off-by: Fabrizio Castro
> > > > > > <fabrizio.castro@bp.renesas.com>
> > > > > > Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
> > > > >
> > > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > >
> > > > Thanks, applied.
> > >
> > > Sorry, I somehow overlooked Fabrizio's comments.
> > > I have dropped this patch for now.
> >
> > Thank you for doing this.
> > We are working on a new patch now, I'll submit a V2 as soon as it is ready.
> > Just to recap (all in one place), we found an HW issue and a SW one
> preventing SDHI0 from working properly at UHS SDR50 and SDR104,
> therefore we need a new patch to limit the speed of this interface.
> 
> Thanks for catching this, UHS can be quite troublesome in my experience.

So we've seen!

[PATCH v2] ARM: dts: iwg22d: Enable SDHI0 controller

[Fabrizio Castro]

Enable the SDHI0 controller on iWave RZ/G1E carrier board.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
---
 arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
index aac84c6..8772c56 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
@@ -24,6 +24,19 @@
 		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
 		stdout-path = "serial0:115200n8";
 	};
+
+	vccq_sdhi0: regulator-vccq-sdhi0 {
+		compatible = "regulator-gpio";
+
+		regulator-name = "SDHI0 VccQ";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
+		gpios-states = <1>;
+		states = <3300000 1
+			  1800000 0>;
+	};
 };
 
 &pfc {
@@ -36,6 +49,12 @@
 		groups = "avb_mdio", "avb_gmii";
 		function = "avb";
 	};
+
+	sdhi0_pins: sd0 {
+		groups = "sdhi0_data4", "sdhi0_ctrl";
+		function = "sdhi0";
+		power-source = <3300>;
+	};
 };
 
 &scif4 {
@@ -63,3 +82,13 @@
 		micrel,led-mode = <1>;
 	};
 };
+
+&sdhi0 {
+	pinctrl-0 = <&sdhi0_pins>;
+	pinctrl-names = "default";
+
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&vccq_sdhi0>;
+	cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
-- 
2.7.4

[PATCH v2] ARM: dts: iwg22d: Enable SDHI0 controller

[Fabrizio Castro]

Hello Simon,

just to clarify the changes between v1 and v2, we can't use SDR50 and SDR104 (due to an HW issue) therefore the pinctrl for UHS has been removed and we dropped property "sd-uhs-sdr104". High Speed has been tested, therefore if you are happy with the patch I guess you can update the following page accordingly:
http://elinux.org/index.php?title=Renesas-MMC-Enabled-Speeds&type=revision&diff=451426&oldid=451421

Although (due to a bug) sdhi0 may not hold a reference to "vccq_sdhi0", the gpio regulator will initialize "SDHI0 VccQ" at 3.3V.
I have sent another patch (mmc: tmio: check mmc_regulator_get_supply return value) to start a discussion about a possible fix for the bug.

Let me know if you need more information.

Thanks,
Fabrizio

> -----Original Message-----
> From: linux-renesas-soc-owner at vger.kernel.org [mailto:linux-renesas-soc-owner at vger.kernel.org] On Behalf Of Fabrizio Castro
> Sent: 22 September 2017 14:01
> To: Simon Horman <horms+renesas@verge.net.au>
> Cc: Rob Herring <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>; Magnus Damm <magnus.damm@gmail.com>;
> Russell King <linux@armlinux.org.uk>; Chris Paterson <Chris.Paterson2@renesas.com>; Fabrizio Castro
> <fabrizio.castro@bp.renesas.com>; Biju Das <biju.das@bp.renesas.com>; devicetree at vger.kernel.org; linux-renesas-
> soc at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Chris Paterson <Chris.Paterson2@renesas.com>
> Subject: [PATCH v2] ARM: dts: iwg22d: Enable SDHI0 controller
>
> Enable the SDHI0 controller on iWave RZ/G1E carrier board.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
> ---
>  arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 29 +++++++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
>
> diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
> index aac84c6..8772c56 100644
> --- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
> +++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
> @@ -24,6 +24,19 @@
>  bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
>  stdout-path = "serial0:115200n8";
>  };
> +
> +vccq_sdhi0: regulator-vccq-sdhi0 {
> +compatible = "regulator-gpio";
> +
> +regulator-name = "SDHI0 VccQ";
> +regulator-min-microvolt = <1800000>;
> +regulator-max-microvolt = <3300000>;
> +
> +gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
> +gpios-states = <1>;
> +states = <3300000 1
> +  1800000 0>;
> +};
>  };
>
>  &pfc {
> @@ -36,6 +49,12 @@
>  groups = "avb_mdio", "avb_gmii";
>  function = "avb";
>  };
> +
> +sdhi0_pins: sd0 {
> +groups = "sdhi0_data4", "sdhi0_ctrl";
> +function = "sdhi0";
> +power-source = <3300>;
> +};
>  };
>
>  &scif4 {
> @@ -63,3 +82,13 @@
>  micrel,led-mode = <1>;
>  };
>  };
> +
> +&sdhi0 {
> +pinctrl-0 = <&sdhi0_pins>;
> +pinctrl-names = "default";
> +
> +vmmc-supply = <&reg_3p3v>;
> +vqmmc-supply = <&vccq_sdhi0>;
> +cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
> +status = "okay";
> +};
> --
> 2.7.4




Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

[PATCH v2] ARM: dts: iwg22d: Enable SDHI0 controller

[Simon Horman]

On Fri, Sep 22, 2017 at 01:33:39PM +0000, Fabrizio Castro wrote:
> Hello Simon,
> 
> just to clarify the changes between v1 and v2, we can't use SDR50 and SDR104 (due to an HW issue) therefore the pinctrl for UHS has been removed and we dropped property "sd-uhs-sdr104". High Speed has been tested, therefore if you are happy with the patch I guess you can update the following page accordingly:
> http://elinux.org/index.php?title=Renesas-MMC-Enabled-Speeds&type=revision&diff=451426&oldid=451421
> 
> Although (due to a bug) sdhi0 may not hold a reference to "vccq_sdhi0", the gpio regulator will initialize "SDHI0 VccQ" at 3.3V.
> I have sent another patch (mmc: tmio: check mmc_regulator_get_supply return value) to start a discussion about a possible fix for the bug.
> 
> Let me know if you need more information.

Thanks again for following up on this.

I have applied the patch with Geert's tag.

I have also updated the Wiki at the URL above,
feel free to make any further updates there as appropriate.

[PATCH v2] ARM: dts: iwg22d: Enable SDHI0 controller

[Chris Paterson]

Hello Simon,

> From: Simon Horman [mailto:horms at verge.net.au]
> Sent: 25 September 2017 08:18
> 
> On Fri, Sep 22, 2017 at 01:33:39PM +0000, Fabrizio Castro wrote:
> > Hello Simon,
> >
> > just to clarify the changes between v1 and v2, we can't use SDR50 and
> SDR104 (due to an HW issue) therefore the pinctrl for UHS has been
> removed and we dropped property "sd-uhs-sdr104". High Speed has been
> tested, therefore if you are happy with the patch I guess you can update the
> following page accordingly:
> > http://elinux.org/index.php?title=Renesas-MMC-Enabled-
> Speeds&type=revi
> > sion&diff=451426&oldid=451421
> >
> > Although (due to a bug) sdhi0 may not hold a reference to "vccq_sdhi0",
> the gpio regulator will initialize "SDHI0 VccQ" at 3.3V.
> > I have sent another patch (mmc: tmio: check mmc_regulator_get_supply
> return value) to start a discussion about a possible fix for the bug.
> >
> > Let me know if you need more information.
> 
> Thanks again for following up on this.
> 
> I have applied the patch with Geert's tag.

Thanks

> 
> I have also updated the Wiki at the URL above, feel free to make any further
> updates there as appropriate.

Thanks, looks okay to me.

Kind regards, Chris

[PATCH v2] ARM: dts: iwg22d: Enable SDHI0 controller

[Geert Uytterhoeven]

On Fri, Sep 22, 2017 at 3:01 PM, Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> Enable the SDHI0 controller on iWave RZ/G1E carrier board.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 5/8] ARM: dts: r8a7743: Add QSPI support

[Chris Paterson]

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Add the DT node for the QSPI interface to the SoC dtsi.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
---
This patch is based on renesas-devel-20170913-v4.13.

This patch is dependant on:
- "dt-bindings: qspi: Add r8a7743/5 to the compatible list"


 arch/arm/boot/dts/r8a7743.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 266c5ec..454f980 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -28,6 +28,7 @@
 		i2c6 = &iic0;
 		i2c7 = &iic1;
 		i2c8 = &iic3;
+		spi0 = &qspi;
 	};
 
 	cpus {
@@ -835,6 +836,22 @@
 			status = "disabled";
 		};
 
+		qspi: spi at e6b10000 {
+			compatible = "renesas,qspi-r8a7743", "renesas,qspi";
+			reg = <0 0xe6b10000 0 0x2c>;
+			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 917>;
+			dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+			       <&dmac1 0x17>, <&dmac1 0x18>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+			num-cs = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			resets = <&cpg 917>;
+			status = "disabled";
+		};
+
 		sdhi0: sd at ee100000 {
 			compatible = "renesas,sdhi-r8a7743";
 			reg = <0 0xee100000 0 0x328>;
-- 
1.9.1

[PATCH 5/8] ARM: dts: r8a7743: Add QSPI support

[Geert Uytterhoeven]

On Wed, Sep 13, 2017 at 7:05 PM, Chris Paterson
<chris.paterson2@renesas.com> wrote:
> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>
> Add the DT node for the QSPI interface to the SoC dtsi.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 5/8] ARM: dts: r8a7743: Add QSPI support

[Simon Horman]

On Tue, Sep 19, 2017 at 05:09:47PM +0200, Geert Uytterhoeven wrote:
> On Wed, Sep 13, 2017 at 7:05 PM, Chris Paterson
> <chris.paterson2@renesas.com> wrote:
> > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> >
> > Add the DT node for the QSPI interface to the SoC dtsi.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
> 
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Thanks, applied.

[PATCH 6/8] ARM: dts: iwg20m: Add SPI NOR support

[Chris Paterson]

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Add support for the SPI NOR device used to boot up the system
to the System on Module DT.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
---
This patch is based on renesas-devel-20170913-v4.13.

This patch is dependant on:
- "of: add vendor prefix for Silicon Storage Technology Inc."
- "doc: dt: mtd: Add sst25vf016b to the list of supported chip names"


 arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
index 4119737..75a8ca5 100644
--- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
+++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
@@ -44,6 +44,11 @@
 		function = "mmc";
 	};
 
+	qspi_pins: qspi {
+		groups = "qspi_ctrl", "qspi_data2";
+		function = "qspi";
+	};
+
 	sdhi0_pins: sd0 {
 		groups = "sdhi0_data4", "sdhi0_ctrl";
 		function = "sdhi0";
@@ -61,6 +66,27 @@
 	status = "okay";
 };
 
+&qspi {
+	pinctrl-0 = <&qspi_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	/* WARNING - This device contains the bootloader. Handle with care. */
+	flash: flash at 0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "sst,sst25vf016b", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+		m25p,fast-read;
+		spi-cpol;
+		spi-cpha;
+	};
+};
+
 &sdhi0 {
 	pinctrl-0 = <&sdhi0_pins>;
 	pinctrl-names = "default";
-- 
1.9.1

[PATCH 6/8] ARM: dts: iwg20m: Add SPI NOR support

[Simon Horman]

On Wed, Sep 13, 2017 at 06:05:39PM +0100, Chris Paterson wrote:
> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> 
> Add support for the SPI NOR device used to boot up the system
> to the System on Module DT.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
> ---
> This patch is based on renesas-devel-20170913-v4.13.
> 
> This patch is dependant on:
> - "of: add vendor prefix for Silicon Storage Technology Inc."
> - "doc: dt: mtd: Add sst25vf016b to the list of supported chip names"
> 
> 
>  arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
> index 4119737..75a8ca5 100644
> --- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
> +++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
> @@ -44,6 +44,11 @@
>  		function = "mmc";
>  	};
>  
> +	qspi_pins: qspi {
> +		groups = "qspi_ctrl", "qspi_data2";
> +		function = "qspi";
> +	};
> +
>  	sdhi0_pins: sd0 {
>  		groups = "sdhi0_data4", "sdhi0_ctrl";
>  		function = "sdhi0";
> @@ -61,6 +66,27 @@
>  	status = "okay";
>  };
>  
> +&qspi {
> +	pinctrl-0 = <&qspi_pins>;
> +	pinctrl-names = "default";
> +
> +	status = "okay";
> +
> +	/* WARNING - This device contains the bootloader. Handle with care. */
> +	flash: flash at 0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "sst,sst25vf016b", "jedec,spi-nor";
> +		reg = <0>;
> +		spi-max-frequency = <50000000>;
> +		spi-tx-bus-width = <1>;
> +		spi-rx-bus-width = <1>;
> +		m25p,fast-read;
> +		spi-cpol;
> +		spi-cpha;
> +	};

Does the device have partitions?
If so, should they be described here?

> +};
> +
>  &sdhi0 {
>  	pinctrl-0 = <&sdhi0_pins>;
>  	pinctrl-names = "default";
> -- 
> 1.9.1
> 

[PATCH 6/8] ARM: dts: iwg20m: Add SPI NOR support

[Chris Paterson]

Hello Simon,

> From: devicetree-owner at vger.kernel.org [mailto:devicetree-
> owner at vger.kernel.org] On Behalf Of Simon Horman
> Sent: 15 September 2017 09:35
> 
> On Wed, Sep 13, 2017 at 06:05:39PM +0100, Chris Paterson wrote:
> > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> >
> > Add support for the SPI NOR device used to boot up the system to the
> > System on Module DT.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
> > ---
> > This patch is based on renesas-devel-20170913-v4.13.
> >
> > This patch is dependant on:
> > - "of: add vendor prefix for Silicon Storage Technology Inc."
> > - "doc: dt: mtd: Add sst25vf016b to the list of supported chip names"
> >
> >
> >  arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 26
> ++++++++++++++++++++++++++
> >  1 file changed, 26 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
> > b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
> > index 4119737..75a8ca5 100644
> > --- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
> > +++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
> > @@ -44,6 +44,11 @@
> >  		function = "mmc";
> >  	};
> >
> > +	qspi_pins: qspi {
> > +		groups = "qspi_ctrl", "qspi_data2";
> > +		function = "qspi";
> > +	};
> > +
> >  	sdhi0_pins: sd0 {
> >  		groups = "sdhi0_data4", "sdhi0_ctrl";
> >  		function = "sdhi0";
> > @@ -61,6 +66,27 @@
> >  	status = "okay";
> >  };
> >
> > +&qspi {
> > +	pinctrl-0 = <&qspi_pins>;
> > +	pinctrl-names = "default";
> > +
> > +	status = "okay";
> > +
> > +	/* WARNING - This device contains the bootloader. Handle with care.
> */
> > +	flash: flash at 0 {
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		compatible = "sst,sst25vf016b", "jedec,spi-nor";
> > +		reg = <0>;
> > +		spi-max-frequency = <50000000>;
> > +		spi-tx-bus-width = <1>;
> > +		spi-rx-bus-width = <1>;
> > +		m25p,fast-read;
> > +		spi-cpol;
> > +		spi-cpha;
> > +	};
> 
> Does the device have partitions?
> If so, should they be described here?

We aren't confident that all devices will come with the same partitions, so decided not to add any here.

Kind regards, Chris

> 
> > +};
> > +
> >  &sdhi0 {
> >  	pinctrl-0 = <&sdhi0_pins>;
> >  	pinctrl-names = "default";
> > --
> > 1.9.1
> >
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in the
> body of a message to majordomo at vger.kernel.org More majordomo info at
> http://vger.kernel.org/majordomo-info.html

[PATCH 6/8] ARM: dts: iwg20m: Add SPI NOR support

[Simon Horman]

On Fri, Sep 15, 2017 at 03:12:04PM +0000, Chris Paterson wrote:
> Hello Simon,
> 
> > From: devicetree-owner at vger.kernel.org [mailto:devicetree-
> > owner at vger.kernel.org] On Behalf Of Simon Horman
> > Sent: 15 September 2017 09:35
> > 
> > On Wed, Sep 13, 2017 at 06:05:39PM +0100, Chris Paterson wrote:
> > > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > >
> > > Add support for the SPI NOR device used to boot up the system to the
> > > System on Module DT.
> > >
> > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
> > > ---
> > > This patch is based on renesas-devel-20170913-v4.13.
> > >
> > > This patch is dependant on:
> > > - "of: add vendor prefix for Silicon Storage Technology Inc."
> > > - "doc: dt: mtd: Add sst25vf016b to the list of supported chip names"
> > >
> > >
> > >  arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 26
> > ++++++++++++++++++++++++++
> > >  1 file changed, 26 insertions(+)
> > >
> > > diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
> > > b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
> > > index 4119737..75a8ca5 100644
> > > --- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
> > > +++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
> > > @@ -44,6 +44,11 @@
> > >  		function = "mmc";
> > >  	};
> > >
> > > +	qspi_pins: qspi {
> > > +		groups = "qspi_ctrl", "qspi_data2";
> > > +		function = "qspi";
> > > +	};
> > > +
> > >  	sdhi0_pins: sd0 {
> > >  		groups = "sdhi0_data4", "sdhi0_ctrl";
> > >  		function = "sdhi0";
> > > @@ -61,6 +66,27 @@
> > >  	status = "okay";
> > >  };
> > >
> > > +&qspi {
> > > +	pinctrl-0 = <&qspi_pins>;
> > > +	pinctrl-names = "default";
> > > +
> > > +	status = "okay";
> > > +
> > > +	/* WARNING - This device contains the bootloader. Handle with care.
> > */
> > > +	flash: flash at 0 {
> > > +		#address-cells = <1>;
> > > +		#size-cells = <1>;
> > > +		compatible = "sst,sst25vf016b", "jedec,spi-nor";
> > > +		reg = <0>;
> > > +		spi-max-frequency = <50000000>;
> > > +		spi-tx-bus-width = <1>;
> > > +		spi-rx-bus-width = <1>;
> > > +		m25p,fast-read;
> > > +		spi-cpol;
> > > +		spi-cpha;
> > > +	};
> > 
> > Does the device have partitions?
> > If so, should they be described here?
> 
> We aren't confident that all devices will come with the same partitions, so decided not to add any here.

Thanks for the clarification, applied with Geert's tag.

[PATCH 6/8] ARM: dts: iwg20m: Add SPI NOR support

[Geert Uytterhoeven]

On Wed, Sep 13, 2017 at 7:05 PM, Chris Paterson
<chris.paterson2@renesas.com> wrote:
> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>
> Add support for the SPI NOR device used to boot up the system
> to the System on Module DT.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 7/8] ARM: dts: r8a7745: Add QSPI support

[Chris Paterson]

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Add the DT node for the QSPI interface to the SoC dtsi.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
---
This patch is based on renesas-devel-20170913-v4.13.

This patch is dependant on:
- "dt-bindings: qspi: Add r8a7743/5 to the compatible list"


 arch/arm/boot/dts/r8a7745.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index 37c0fac..b819ec5 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -25,6 +25,7 @@
 		i2c3 = &i2c3;
 		i2c4 = &i2c4;
 		i2c5 = &i2c5;
+		spi0 = &qspi;
 	};
 
 	cpus {
@@ -752,6 +753,22 @@
 			status = "disabled";
 		};
 
+		qspi: spi at e6b10000 {
+			compatible = "renesas,qspi-r8a7745", "renesas,qspi";
+			reg = <0 0xe6b10000 0 0x2c>;
+			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 917>;
+			dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+			       <&dmac1 0x17>, <&dmac1 0x18>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+			num-cs = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			resets = <&cpg 917>;
+			status = "disabled";
+		};
+
 		sdhi0: sd at ee100000 {
 			compatible = "renesas,sdhi-r8a7745";
 			reg = <0 0xee100000 0 0x328>;
-- 
1.9.1

[PATCH 7/8] ARM: dts: r8a7745: Add QSPI support

[Geert Uytterhoeven]

On Wed, Sep 13, 2017 at 7:05 PM, Chris Paterson
<chris.paterson2@renesas.com> wrote:
> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>
> Add the DT node for the QSPI interface to the SoC dtsi.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 7/8] ARM: dts: r8a7745: Add QSPI support

[Simon Horman]

On Tue, Sep 19, 2017 at 05:10:06PM +0200, Geert Uytterhoeven wrote:
> On Wed, Sep 13, 2017 at 7:05 PM, Chris Paterson
> <chris.paterson2@renesas.com> wrote:
> > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> >
> > Add the DT node for the QSPI interface to the SoC dtsi.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
> 
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Thanks, applied.

[PATCH 8/8] ARM: drs: iwg22m: Add SPI NOR support

[Chris Paterson]

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Add support for the SPI NOR device used to boot up the system
to the System on Module DT.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
---
This patch is based on renesas-devel-20170913-v4.13.

This patch is dependant on:
- "of: add vendor prefix for Silicon Storage Technology Inc."
- "doc: dt: mtd: Add sst25vf016b to the list of supported chip names"


 arch/arm/boot/dts/r8a7745-iwg22m.dtsi | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
index f7f9cef..ed9a8cf 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
+++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
@@ -39,6 +39,11 @@
 		function = "mmc";
 	};
 
+	qspi_pins: qspi {
+		groups = "qspi_ctrl", "qspi_data2";
+		function = "qspi";
+	};
+
 	sdhi1_pins: sd1 {
 		groups = "sdhi1_data4", "sdhi1_ctrl";
 		function = "sdhi1";
@@ -61,6 +66,27 @@
 	status = "okay";
 };
 
+&qspi {
+	pinctrl-0 = <&qspi_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	/* WARNING - This device contains the bootloader. Handle with care. */
+	flash: flash at 0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "sst,sst25vf016b", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+		m25p,fast-read;
+		spi-cpol;
+		spi-cpha;
+	};
+};
+
 &sdhi1 {
 	pinctrl-0 = <&sdhi1_pins>;
 	pinctrl-names = "default";
-- 
1.9.1

[PATCH 8/8] ARM: drs: iwg22m: Add SPI NOR support

[Biju Das]

Hi,

> -----Original Message-----
> From: devicetree-owner at vger.kernel.org [mailto:devicetree-
> owner at vger.kernel.org] On Behalf Of Chris Paterson
> Sent: 13 September 2017 18:06
> To: Simon Horman <horms@verge.net.au>
> Cc: Rob Herring <robh+dt@kernel.org>; Mark Rutland
> <mark.rutland@arm.com>; Magnus Damm <magnus.damm@gmail.com>;
> Russell King <linux@armlinux.org.uk>; Fabrizio Castro
> <fabrizio.castro@bp.renesas.com>; devicetree at vger.kernel.org; linux-renesas-
> soc at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Chris Paterson
> <Chris.Paterson2@renesas.com>
> Subject: [PATCH 8/8] ARM: drs: iwg22m: Add SPI NOR support

Subject should be " ARM: dts: iwg22m: Add SPI NOR support"

> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>
> Add support for the SPI NOR device used to boot up the system to the System on
> Module DT.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>




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[PATCH 8/8] ARM: drs: iwg22m: Add SPI NOR support

[Geert Uytterhoeven]

On Wed, Sep 13, 2017 at 7:05 PM, Chris Paterson
<chris.paterson2@renesas.com> wrote:
> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>
> Add support for the SPI NOR device used to boot up the system
> to the System on Module DT.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>

With the subject fixed (s/drs/dts/):
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 8/8] ARM: drs: iwg22m: Add SPI NOR support

[Simon Horman]

On Wed, Sep 20, 2017 at 01:10:00PM +0200, Geert Uytterhoeven wrote:
> On Wed, Sep 13, 2017 at 7:05 PM, Chris Paterson
> <chris.paterson2@renesas.com> wrote:
> > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> >
> > Add support for the SPI NOR device used to boot up the system
> > to the System on Module DT.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
> 
> With the subject fixed (s/drs/dts/):
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Thanks, applied as

ARM: dts: iwg22m: Add SPI NOR support