From: jbrunet@baylibre.com (Jerome Brunet)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v6 4/6] clk: meson: make the spinlock naming more specific
Date: Mon, 11 Dec 2017 12:27:17 +0100 [thread overview]
Message-ID: <1512991637.334.28.camel@baylibre.com> (raw)
In-Reply-To: <20171211064853.32111-5-yixun.lan@amlogic.com>
On Mon, 2017-12-11 at 14:48 +0800, Yixun Lan wrote:
> .ops = &clk_gate_ops,
> diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
> index 1629da9b4141..87f06a801a4d 100644
> --- a/drivers/clk/meson/clkc.h
> +++ b/drivers/clk/meson/clkc.h
> @@ -134,7 +134,7 @@ struct meson_clk_audio_divider {
> struct clk_gate _name = { \
> .reg = (void __iomem *) _reg, \
> .bit_idx = (_bit), \
> - .lock = &clk_lock, \
> + .lock = &meson_clk_lock, \
Something is not right here, line is over 80 characters
Remember to run checkpatch on your series please.
> .hw.init = &(struct clk_init_data) { \
> .name = #_name, \
> .ops = &clk_gate_ops, \
next prev parent reply other threads:[~2017-12-11 11:27 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-11 6:48 [PATCH v6 0/6] add clk controller driver for Meson-AXG SoC Yixun Lan
2017-12-11 6:48 ` [PATCH v6 1/6] dt-bindings: clock: add compatible variant for the Meson-AXG Yixun Lan
2017-12-11 6:48 ` [PATCH v6 2/6] clk: meson-axg: add clocks dt-bindings required header Yixun Lan
2017-12-11 6:48 ` [PATCH v6 3/6] clk: meson-axg: add clock controller drivers Yixun Lan
2017-12-11 9:46 ` Jerome Brunet
2017-12-11 10:16 ` Yixun Lan
2017-12-11 10:21 ` Jerome Brunet
2017-12-11 6:48 ` [PATCH v6 4/6] clk: meson: make the spinlock naming more specific Yixun Lan
2017-12-11 9:26 ` Jerome Brunet
2017-12-11 11:27 ` Jerome Brunet [this message]
2017-12-11 6:48 ` [PATCH v6 5/6] arm64: dts: meson-axg: add clock DT info for Meson AXG SoC Yixun Lan
2017-12-11 6:48 ` [PATCH v6 6/6] arm64: dts: meson-axg: switch uart_ao clock to CLK81 Yixun Lan
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