* [PATCH v4 0/7] ARM: davinci: convert to common clock framework
@ 2017-12-31 23:39 David Lechner
2017-12-31 23:39 ` [PATCH v4 1/7] ARM: davinci: move davinci_clk_init() to init_time David Lechner
` (7 more replies)
0 siblings, 8 replies; 29+ messages in thread
From: David Lechner @ 2017-12-31 23:39 UTC (permalink / raw)
To: linux-arm-kernel
This series converts mach-davinci to use the common clock framework.
Basically, this series does some cleanup and rearranging to get things
ready for the conversion. Then there is a patch to add new driver in
drivers/clk and finally a patch to make the conversion from the mach
clock drivers to the new drivers.
I have tested this on LEGO MINDSTORMS EV3 (TI AM1808), so I am confident
that I haven't broken anything (too badly) in da850. But, I don't have
other hardware to test.
The one thing that I know I have broken is CPU frequency scaling on da850.
I don't think it was working with device tree anyway, so I can't really test
it with the hardware I have. I'm hoping that it will be OK to defer fixing
it and add device tree support at the same time.
Dependencies:
* This series applies on top of "ARM: davinici: move watchdog restart from
mach to drivers?" [1][2]
* On da850, you will also need a patch to prevent problems with the USB PHY
clocks [3]
* Or get it all at once:
git fetch https://github.com/dlech/ev3dev-kernel.git common-clk-v4
[1]: https://patchwork.kernel.org/patch/10105623/
[2]: https://patchwork.kernel.org/patch/10105613/
[3]: https://patchwork.kernel.org/patch/10133193/
v4 changes:
* Basically, the whole series is new/reworked except for the first patch.
* Instead of having an intermediate conversion of the clocks in mach-davinci,
new clock drivers are introduced in drivers/clk.
* There are a few more cleanup patches added before making the conversion.
v3 changes:
* Remove leftovers from rebasing in "ARM: davinci: don't use static clk_lookup"
(fixes compile error)
v2 changes:
* Dropped "ARM: davinci: clean up map_io functions" - will resend as separate
patch series
* Reworked remaining patches so that there is less shuffling around
David Lechner (7):
ARM: davinci: move davinci_clk_init() to init_time
ARM: davinci: don't use static clk_lookup
ARM: davinci: fix duplicate clocks
ARM: davinci: remove davinci_set_refclk_rate()
clk: Introduce davinci clocks
ARM: davinci: convert to common clock framework
ARM: davinci_all_defconfig: remove CONFIG_DAVINCI_RESET_CLOCKS
arch/arm/Kconfig | 2 +-
arch/arm/configs/davinci_all_defconfig | 1 -
arch/arm/mach-davinci/Kconfig | 12 -
arch/arm/mach-davinci/Makefile | 2 +-
arch/arm/mach-davinci/board-da830-evm.c | 17 +-
arch/arm/mach-davinci/board-da850-evm.c | 2 +-
arch/arm/mach-davinci/board-dm355-evm.c | 2 +-
arch/arm/mach-davinci/board-dm355-leopard.c | 2 +-
arch/arm/mach-davinci/board-dm365-evm.c | 2 +-
arch/arm/mach-davinci/board-dm644x-evm.c | 2 +-
arch/arm/mach-davinci/board-dm646x-evm.c | 17 +-
arch/arm/mach-davinci/board-mityomapl138.c | 2 +-
arch/arm/mach-davinci/board-neuros-osd2.c | 2 +-
arch/arm/mach-davinci/board-omapl138-hawk.c | 17 +-
arch/arm/mach-davinci/board-sffsdr.c | 2 +-
arch/arm/mach-davinci/clock.c | 745 --------------------------
arch/arm/mach-davinci/clock.h | 72 ---
arch/arm/mach-davinci/common.c | 1 -
arch/arm/mach-davinci/da830.c | 536 +++++--------------
arch/arm/mach-davinci/da850.c | 785 ++++++----------------------
arch/arm/mach-davinci/da8xx-dt.c | 17 +-
arch/arm/mach-davinci/davinci.h | 4 +
arch/arm/mach-davinci/devices-da8xx.c | 46 +-
arch/arm/mach-davinci/dm355.c | 452 ++++------------
arch/arm/mach-davinci/dm365.c | 594 ++++++---------------
arch/arm/mach-davinci/dm644x.c | 401 ++++----------
arch/arm/mach-davinci/dm646x.c | 451 +++++-----------
arch/arm/mach-davinci/include/mach/clock.h | 3 -
arch/arm/mach-davinci/include/mach/common.h | 9 -
arch/arm/mach-davinci/include/mach/da8xx.h | 11 +-
arch/arm/mach-davinci/psc.c | 137 -----
arch/arm/mach-davinci/psc.h | 14 -
arch/arm/mach-davinci/usb-da8xx.c | 225 +-------
drivers/clk/Makefile | 1 +
drivers/clk/davinci/Makefile | 3 +
drivers/clk/davinci/da8xx-cfgchip-clk.c | 380 ++++++++++++++
drivers/clk/davinci/pll.c | 333 ++++++++++++
drivers/clk/davinci/psc.c | 217 ++++++++
include/linux/clk/davinci.h | 46 ++
include/linux/platform_data/davinci_clk.h | 25 +
40 files changed, 1875 insertions(+), 3717 deletions(-)
delete mode 100644 arch/arm/mach-davinci/clock.c
delete mode 100644 arch/arm/mach-davinci/psc.c
create mode 100644 drivers/clk/davinci/Makefile
create mode 100644 drivers/clk/davinci/da8xx-cfgchip-clk.c
create mode 100644 drivers/clk/davinci/pll.c
create mode 100644 drivers/clk/davinci/psc.c
create mode 100644 include/linux/clk/davinci.h
create mode 100644 include/linux/platform_data/davinci_clk.h
--
2.7.4
^ permalink raw reply [flat|nested] 29+ messages in thread* [PATCH v4 1/7] ARM: davinci: move davinci_clk_init() to init_time 2017-12-31 23:39 [PATCH v4 0/7] ARM: davinci: convert to common clock framework David Lechner @ 2017-12-31 23:39 ` David Lechner 2017-12-31 23:39 ` [PATCH v4 2/7] ARM: davinci: don't use static clk_lookup David Lechner ` (6 subsequent siblings) 7 siblings, 0 replies; 29+ messages in thread From: David Lechner @ 2017-12-31 23:39 UTC (permalink / raw) To: linux-arm-kernel This moves the call of davinci_clk_init() from map_io to init_time for all boards. This is the proper place to init clocks. This is also done in preparation for moving to the common clock framework. Signed-off-by: David Lechner <david@lechnology.com> --- arch/arm/mach-davinci/board-da830-evm.c | 2 +- arch/arm/mach-davinci/board-da850-evm.c | 2 +- arch/arm/mach-davinci/board-dm355-evm.c | 2 +- arch/arm/mach-davinci/board-dm355-leopard.c | 2 +- arch/arm/mach-davinci/board-dm365-evm.c | 2 +- arch/arm/mach-davinci/board-dm644x-evm.c | 2 +- arch/arm/mach-davinci/board-dm646x-evm.c | 11 +++++++---- arch/arm/mach-davinci/board-mityomapl138.c | 2 +- arch/arm/mach-davinci/board-neuros-osd2.c | 2 +- arch/arm/mach-davinci/board-omapl138-hawk.c | 2 +- arch/arm/mach-davinci/board-sffsdr.c | 2 +- arch/arm/mach-davinci/da830.c | 4 ++++ arch/arm/mach-davinci/da850.c | 4 ++++ arch/arm/mach-davinci/da8xx-dt.c | 2 +- arch/arm/mach-davinci/davinci.h | 4 ++++ arch/arm/mach-davinci/dm355.c | 5 +++++ arch/arm/mach-davinci/dm365.c | 5 +++++ arch/arm/mach-davinci/dm644x.c | 5 +++++ arch/arm/mach-davinci/dm646x.c | 5 +++++ arch/arm/mach-davinci/include/mach/da8xx.h | 3 +++ 20 files changed, 53 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index a58bfca..7adf009 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -638,7 +638,7 @@ MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM") .atag_offset = 0x100, .map_io = da830_evm_map_io, .init_irq = cp_intc_init, - .init_time = davinci_timer_init, + .init_time = da830_init_time, .init_machine = da830_evm_init, .init_late = davinci_init_late, .dma_zone_size = SZ_128M, diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 6039ec1..8602d0d 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -1481,7 +1481,7 @@ MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM") .atag_offset = 0x100, .map_io = da850_evm_map_io, .init_irq = cp_intc_init, - .init_time = davinci_timer_init, + .init_time = da850_init_time, .init_machine = da850_evm_init, .init_late = davinci_init_late, .dma_zone_size = SZ_128M, diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c index d60d998..3c15cb7 100644 --- a/arch/arm/mach-davinci/board-dm355-evm.c +++ b/arch/arm/mach-davinci/board-dm355-evm.c @@ -416,7 +416,7 @@ MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM") .atag_offset = 0x100, .map_io = dm355_evm_map_io, .init_irq = davinci_irq_init, - .init_time = davinci_timer_init, + .init_time = dm355_init_time, .init_machine = dm355_evm_init, .init_late = davinci_init_late, .dma_zone_size = SZ_128M, diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c index 1e7e9b8..3ebc89d 100644 --- a/arch/arm/mach-davinci/board-dm355-leopard.c +++ b/arch/arm/mach-davinci/board-dm355-leopard.c @@ -271,7 +271,7 @@ MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard") .atag_offset = 0x100, .map_io = dm355_leopard_map_io, .init_irq = davinci_irq_init, - .init_time = davinci_timer_init, + .init_time = dm355_init_time, .init_machine = dm355_leopard_init, .init_late = davinci_init_late, .dma_zone_size = SZ_128M, diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c index 17b2c29..3daeac7 100644 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ b/arch/arm/mach-davinci/board-dm365-evm.c @@ -774,7 +774,7 @@ MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM") .atag_offset = 0x100, .map_io = dm365_evm_map_io, .init_irq = davinci_irq_init, - .init_time = davinci_timer_init, + .init_time = dm365_init_time, .init_machine = dm365_evm_init, .init_late = davinci_init_late, .dma_zone_size = SZ_128M, diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c index 5e1afc2..8d8c4ab 100644 --- a/arch/arm/mach-davinci/board-dm644x-evm.c +++ b/arch/arm/mach-davinci/board-dm644x-evm.c @@ -817,7 +817,7 @@ MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM") .atag_offset = 0x100, .map_io = davinci_evm_map_io, .init_irq = davinci_irq_init, - .init_time = davinci_timer_init, + .init_time = dm644x_init_time, .init_machine = davinci_evm_init, .init_late = davinci_init_late, .dma_zone_size = SZ_128M, diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index 003bbe5..dafc852 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c @@ -721,9 +721,12 @@ static void __init evm_init_i2c(void) static void __init davinci_map_io(void) { dm646x_init(); +} - if (machine_is_davinci_dm6467tevm()) - davinci_set_refclk_rate(DM6467T_EVM_REF_FREQ); +static void __init dm6467t_evm_init_time(void) +{ + dm646x_init_time(); + davinci_set_refclk_rate(DM6467T_EVM_REF_FREQ); } #define DM646X_EVM_PHY_ID "davinci_mdio-0:01" @@ -797,7 +800,7 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM") .atag_offset = 0x100, .map_io = davinci_map_io, .init_irq = davinci_irq_init, - .init_time = davinci_timer_init, + .init_time = dm646x_init_time, .init_machine = evm_init, .init_late = davinci_init_late, .dma_zone_size = SZ_128M, @@ -807,7 +810,7 @@ MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM") .atag_offset = 0x100, .map_io = davinci_map_io, .init_irq = davinci_irq_init, - .init_time = davinci_timer_init, + .init_time = dm6467t_evm_init_time, .init_machine = evm_init, .init_late = davinci_init_late, .dma_zone_size = SZ_128M, diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c index 0b23cf3..f9a725a 100644 --- a/arch/arm/mach-davinci/board-mityomapl138.c +++ b/arch/arm/mach-davinci/board-mityomapl138.c @@ -570,7 +570,7 @@ MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808") .atag_offset = 0x100, .map_io = mityomapl138_map_io, .init_irq = cp_intc_init, - .init_time = davinci_timer_init, + .init_time = da850_init_time, .init_machine = mityomapl138_init, .init_late = davinci_init_late, .dma_zone_size = SZ_128M, diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c index 1e27baa..ff871a0 100644 --- a/arch/arm/mach-davinci/board-neuros-osd2.c +++ b/arch/arm/mach-davinci/board-neuros-osd2.c @@ -227,7 +227,7 @@ MACHINE_START(NEUROS_OSD2, "Neuros OSD2") .atag_offset = 0x100, .map_io = davinci_ntosd2_map_io, .init_irq = davinci_irq_init, - .init_time = davinci_timer_init, + .init_time = dm644x_init_time, .init_machine = davinci_ntosd2_init, .init_late = davinci_init_late, .dma_zone_size = SZ_128M, diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c index 88ab45c..bc8a747 100644 --- a/arch/arm/mach-davinci/board-omapl138-hawk.c +++ b/arch/arm/mach-davinci/board-omapl138-hawk.c @@ -334,7 +334,7 @@ MACHINE_START(OMAPL138_HAWKBOARD, "AM18x/OMAP-L138 Hawkboard") .atag_offset = 0x100, .map_io = omapl138_hawk_map_io, .init_irq = cp_intc_init, - .init_time = davinci_timer_init, + .init_time = da850_init_time, .init_machine = omapl138_hawk_init, .init_late = davinci_init_late, .dma_zone_size = SZ_128M, diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c index 1f02d4e..2922da9 100644 --- a/arch/arm/mach-davinci/board-sffsdr.c +++ b/arch/arm/mach-davinci/board-sffsdr.c @@ -150,7 +150,7 @@ MACHINE_START(SFFSDR, "Lyrtech SFFSDR") .atag_offset = 0x100, .map_io = davinci_sffsdr_map_io, .init_irq = davinci_irq_init, - .init_time = davinci_timer_init, + .init_time = dm644x_init_time, .init_machine = davinci_sffsdr_init, .init_late = davinci_init_late, .dma_zone_size = SZ_128M, diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c index ed0b700..6a8b6ff 100644 --- a/arch/arm/mach-davinci/da830.c +++ b/arch/arm/mach-davinci/da830.c @@ -1220,6 +1220,10 @@ void __init da830_init(void) da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K); WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"); +} +void __init da830_init_time(void) +{ davinci_clk_init(davinci_soc_info_da830.cpu_clks); + davinci_timer_init(); } diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 04a58a3..4da5b25 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -1392,6 +1392,10 @@ void __init da850_init(void) v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); v &= ~CFGCHIP3_PLL1_MASTER_LOCK; __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); +} +void __init da850_init_time(void) +{ davinci_clk_init(davinci_soc_info_da850.cpu_clks); + davinci_timer_init(); } diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c index 779e8ce..ab199f4 100644 --- a/arch/arm/mach-davinci/da8xx-dt.c +++ b/arch/arm/mach-davinci/da8xx-dt.c @@ -96,7 +96,7 @@ static const char *const da850_boards_compat[] __initconst = { DT_MACHINE_START(DA850_DT, "Generic DA850/OMAP-L138/AM18x") .map_io = da850_init, - .init_time = davinci_timer_init, + .init_time = da850_init_time, .init_machine = da850_init_machine, .dt_compat = da850_boards_compat, .init_late = davinci_init_late, diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h index c62b90c..d70f4d9 100644 --- a/arch/arm/mach-davinci/davinci.h +++ b/arch/arm/mach-davinci/davinci.h @@ -83,6 +83,7 @@ int davinci_init_wdt(void); /* DM355 function declarations */ void dm355_init(void); +void dm355_init_time(void); void dm355_init_spi0(unsigned chipselect_mask, const struct spi_board_info *info, unsigned len); void dm355_init_asp1(u32 evt_enable); @@ -91,6 +92,7 @@ int dm355_gpio_register(void); /* DM365 function declarations */ void dm365_init(void); +void dm365_init_time(void); void dm365_init_asp(void); void dm365_init_vc(void); void dm365_init_ks(struct davinci_ks_platform_data *pdata); @@ -102,12 +104,14 @@ int dm365_gpio_register(void); /* DM644x function declarations */ void dm644x_init(void); +void dm644x_init_time(void); void dm644x_init_asp(void); int dm644x_init_video(struct vpfe_config *, struct vpbe_config *); int dm644x_gpio_register(void); /* DM646x function declarations */ void dm646x_init(void); +void dm646x_init_time(void); void dm646x_init_mcasp0(struct snd_platform_data *pdata); void dm646x_init_mcasp1(struct snd_platform_data *pdata); int dm646x_init_edma(struct edma_rsv_info *rsv); diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index 938747f..40641c0 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -1043,7 +1043,12 @@ void __init dm355_init(void) { davinci_common_init(&davinci_soc_info_dm355); davinci_map_sysmod(); +} + +void __init dm355_init_time(void) +{ davinci_clk_init(davinci_soc_info_dm355.cpu_clks); + davinci_timer_init(); } int __init dm355_init_video(struct vpfe_config *vpfe_cfg, diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 5d9f96d..0789ac6 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -1168,7 +1168,12 @@ void __init dm365_init(void) { davinci_common_init(&davinci_soc_info_dm365); davinci_map_sysmod(); +} + +void __init dm365_init_time(void) +{ davinci_clk_init(davinci_soc_info_dm365.cpu_clks); + davinci_timer_init(); } static struct resource dm365_vpss_resources[] = { diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 6b41e1c..a1a2433 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -931,7 +931,12 @@ void __init dm644x_init(void) { davinci_common_init(&davinci_soc_info_dm644x); davinci_map_sysmod(); +} + +void __init dm644x_init_time(void) +{ davinci_clk_init(davinci_soc_info_dm644x.cpu_clks); + davinci_timer_init(); } int __init dm644x_init_video(struct vpfe_config *vpfe_cfg, diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index 6fc06a6..c518403 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -956,7 +956,12 @@ void __init dm646x_init(void) { davinci_common_init(&davinci_soc_info_dm646x); davinci_map_sysmod(); +} + +void __init dm646x_init_time(void) +{ davinci_clk_init(davinci_soc_info_dm646x.cpu_clks); + davinci_timer_init(); } static int __init dm646x_init_devices(void) diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 751d2ac..3481a0d 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -87,7 +87,10 @@ extern unsigned int da850_max_speed; #define DA8XX_ARM_RAM_BASE 0xffff0000 void da830_init(void); +void da830_init_time(void); + void da850_init(void); +void da850_init_time(void); int da830_register_edma(struct edma_rsv_info *rsv); int da850_register_edma(struct edma_rsv_info *rsv[2]); -- 2.7.4 ^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v4 2/7] ARM: davinci: don't use static clk_lookup 2017-12-31 23:39 [PATCH v4 0/7] ARM: davinci: convert to common clock framework David Lechner 2017-12-31 23:39 ` [PATCH v4 1/7] ARM: davinci: move davinci_clk_init() to init_time David Lechner @ 2017-12-31 23:39 ` David Lechner 2018-01-04 11:10 ` Sekhar Nori 2017-12-31 23:39 ` [PATCH v4 3/7] ARM: davinci: fix duplicate clocks David Lechner ` (5 subsequent siblings) 7 siblings, 1 reply; 29+ messages in thread From: David Lechner @ 2017-12-31 23:39 UTC (permalink / raw) To: linux-arm-kernel In preparation of moving to the common clock framework, usage of static struct clk_lookup is removed. The common clock framework uses an opaque struct clk, so we won't be able to use static tables as was previously done. davinci_clk_init() is changed to init a single clock instead of a table and an individual clk_register_clkdev() is added for each clock. Signed-off-by: David Lechner <david@lechnology.com> --- arch/arm/mach-davinci/clock.c | 73 +++++------ arch/arm/mach-davinci/clock.h | 9 +- arch/arm/mach-davinci/da830.c | 164 +++++++++++++++-------- arch/arm/mach-davinci/da850.c | 197 ++++++++++++++++++---------- arch/arm/mach-davinci/devices-da8xx.c | 5 +- arch/arm/mach-davinci/dm355.c | 137 ++++++++++++------- arch/arm/mach-davinci/dm365.c | 182 ++++++++++++++++--------- arch/arm/mach-davinci/dm644x.c | 125 ++++++++++++------ arch/arm/mach-davinci/dm646x.c | 131 +++++++++++------- arch/arm/mach-davinci/include/mach/common.h | 1 - arch/arm/mach-davinci/usb-da8xx.c | 15 +-- 11 files changed, 652 insertions(+), 387 deletions(-) diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index f77a4f7..f82a90c 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -607,62 +607,51 @@ int davinci_set_refclk_rate(unsigned long rate) return 0; } -int __init davinci_clk_init(struct clk_lookup *clocks) +struct clk * __init davinci_clk_init(struct clk *clk) { - struct clk_lookup *c; - struct clk *clk; - size_t num_clocks = 0; - - for (c = clocks; c->clk; c++) { - clk = c->clk; + if (!clk->recalc) { - if (!clk->recalc) { + /* Check if clock is a PLL */ + if (clk->pll_data) + clk->recalc = clk_pllclk_recalc; - /* Check if clock is a PLL */ - if (clk->pll_data) - clk->recalc = clk_pllclk_recalc; + /* Else, if it is a PLL-derived clock */ + else if (clk->flags & CLK_PLL) + clk->recalc = clk_sysclk_recalc; - /* Else, if it is a PLL-derived clock */ - else if (clk->flags & CLK_PLL) - clk->recalc = clk_sysclk_recalc; - - /* Otherwise, it is a leaf clock (PSC clock) */ - else if (clk->parent) - clk->recalc = clk_leafclk_recalc; - } + /* Otherwise, it is a leaf clock (PSC clock) */ + else if (clk->parent) + clk->recalc = clk_leafclk_recalc; + } - if (clk->pll_data) { - struct pll_data *pll = clk->pll_data; + if (clk->pll_data) { + struct pll_data *pll = clk->pll_data; - if (!pll->div_ratio_mask) - pll->div_ratio_mask = PLLDIV_RATIO_MASK; + if (!pll->div_ratio_mask) + pll->div_ratio_mask = PLLDIV_RATIO_MASK; - if (pll->phys_base && !pll->base) { - pll->base = ioremap(pll->phys_base, SZ_4K); - WARN_ON(!pll->base); - } + if (pll->phys_base && !pll->base) { + pll->base = ioremap(pll->phys_base, SZ_4K); + WARN_ON(!pll->base); } + } - if (clk->recalc) - clk->rate = clk->recalc(clk); - - if (clk->lpsc) - clk->flags |= CLK_PSC; + if (clk->recalc) + clk->rate = clk->recalc(clk); - if (clk->flags & PSC_LRST) - clk->reset = davinci_clk_reset; + if (clk->lpsc) + clk->flags |= CLK_PSC; - clk_register(clk); - num_clocks++; + if (clk->flags & PSC_LRST) + clk->reset = davinci_clk_reset; - /* Turn on clocks that Linux doesn't otherwise manage */ - if (clk->flags & ALWAYS_ENABLED) - clk_enable(clk); - } + clk_register(clk); - clkdev_add_table(clocks, num_clocks); + /* Turn on clocks that Linux doesn't otherwise manage */ + if (clk->flags & ALWAYS_ENABLED) + clk_enable(clk); - return 0; + return clk; } #ifdef CONFIG_DEBUG_FS diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index cf46781..66c40a2 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -118,14 +118,7 @@ struct clk { #define PSC_FORCE BIT(6) /* Force module state transtition */ #define PSC_LRST BIT(8) /* Use local reset on enable/disable */ -#define CLK(dev, con, ck) \ - { \ - .dev_id = dev, \ - .con_id = con, \ - .clk = ck, \ - } \ - -int davinci_clk_init(struct clk_lookup *clocks); +struct clk *davinci_clk_init(struct clk *clk); int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, unsigned int mult, unsigned int postdiv); int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate); diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c index 6a8b6ff..73c48f5 100644 --- a/arch/arm/mach-davinci/da830.c +++ b/arch/arm/mach-davinci/da830.c @@ -378,60 +378,113 @@ static struct clk rmii_clk = { .parent = &pll0_sysclk7, }; -static struct clk_lookup da830_clks[] = { - CLK(NULL, "ref", &ref_clk), - CLK(NULL, "pll0", &pll0_clk), - CLK(NULL, "pll0_aux", &pll0_aux_clk), - CLK(NULL, "pll0_sysclk2", &pll0_sysclk2), - CLK(NULL, "pll0_sysclk3", &pll0_sysclk3), - CLK(NULL, "pll0_sysclk4", &pll0_sysclk4), - CLK(NULL, "pll0_sysclk5", &pll0_sysclk5), - CLK(NULL, "pll0_sysclk6", &pll0_sysclk6), - CLK(NULL, "pll0_sysclk7", &pll0_sysclk7), - CLK("i2c_davinci.1", NULL, &i2c0_clk), - CLK(NULL, "timer0", &timerp64_0_clk), - CLK("davinci-wdt", NULL, &timerp64_1_clk), - CLK(NULL, "arm_rom", &arm_rom_clk), - CLK(NULL, "scr0_ss", &scr0_ss_clk), - CLK(NULL, "scr1_ss", &scr1_ss_clk), - CLK(NULL, "scr2_ss", &scr2_ss_clk), - CLK(NULL, "dmax", &dmax_clk), - CLK(NULL, "tpcc", &tpcc_clk), - CLK(NULL, "tptc0", &tptc0_clk), - CLK(NULL, "tptc1", &tptc1_clk), - CLK("da830-mmc.0", NULL, &mmcsd_clk), - CLK("serial8250.0", NULL, &uart0_clk), - CLK("serial8250.1", NULL, &uart1_clk), - CLK("serial8250.2", NULL, &uart2_clk), - CLK("spi_davinci.0", NULL, &spi0_clk), - CLK("spi_davinci.1", NULL, &spi1_clk), - CLK(NULL, "ecap0", &ecap0_clk), - CLK(NULL, "ecap1", &ecap1_clk), - CLK(NULL, "ecap2", &ecap2_clk), - CLK(NULL, "pwm0", &pwm0_clk), - CLK(NULL, "pwm1", &pwm1_clk), - CLK(NULL, "pwm2", &pwm2_clk), - CLK("eqep.0", NULL, &eqep0_clk), - CLK("eqep.1", NULL, &eqep1_clk), - CLK("da8xx_lcdc.0", "fck", &lcdc_clk), - CLK("davinci-mcasp.0", NULL, &mcasp0_clk), - CLK("davinci-mcasp.1", NULL, &mcasp1_clk), - CLK("davinci-mcasp.2", NULL, &mcasp2_clk), - CLK("musb-da8xx", "usb20", &usb20_clk), - CLK("cppi41-dmaengine", NULL, &cppi41_clk), - CLK(NULL, "aemif", &aemif_clk), - CLK(NULL, "aintc", &aintc_clk), - CLK(NULL, "secu_mgr", &secu_mgr_clk), - CLK("davinci_emac.1", NULL, &emac_clk), - CLK("davinci_mdio.0", "fck", &emac_clk), - CLK(NULL, "gpio", &gpio_clk), - CLK("i2c_davinci.2", NULL, &i2c1_clk), - CLK("ohci-da8xx", "usb11", &usb11_clk), - CLK(NULL, "emif3", &emif3_clk), - CLK(NULL, "arm", &arm_clk), - CLK(NULL, "rmii", &rmii_clk), - CLK(NULL, NULL, NULL), -}; +static __init void da830_clk_init(void) +{ + struct clk *clk; + + clk = davinci_clk_init(&ref_clk); + clk_register_clkdev(clk, "ref", NULL); + clk = davinci_clk_init(&pll0_clk); + clk_register_clkdev(clk, "pll0", NULL); + clk = davinci_clk_init(&pll0_aux_clk); + clk_register_clkdev(clk, "pll0_aux", NULL); + clk = davinci_clk_init(&pll0_sysclk2); + clk_register_clkdev(clk, "pll0_sysclk2", NULL); + clk = davinci_clk_init(&pll0_sysclk3); + clk_register_clkdev(clk, "pll0_sysclk3", NULL); + clk = davinci_clk_init(&pll0_sysclk4); + clk_register_clkdev(clk, "pll0_sysclk4", NULL); + clk = davinci_clk_init(&pll0_sysclk5); + clk_register_clkdev(clk, "pll0_sysclk5", NULL); + clk = davinci_clk_init(&pll0_sysclk6); + clk_register_clkdev(clk, "pll0_sysclk6", NULL); + clk = davinci_clk_init(&pll0_sysclk7); + clk_register_clkdev(clk, "pll0_sysclk7", NULL); + clk = davinci_clk_init(&i2c0_clk); + clk_register_clkdev(clk, NULL, "i2c_davinci.1"); + clk = davinci_clk_init(&timerp64_0_clk); + clk_register_clkdev(clk, "timer0", NULL); + clk = davinci_clk_init(&timerp64_1_clk); + clk_register_clkdev(clk, NULL, "davinci-wdt"); + clk = davinci_clk_init(&arm_rom_clk); + clk_register_clkdev(clk, "arm_rom", NULL); + clk = davinci_clk_init(&scr0_ss_clk); + clk_register_clkdev(clk, "scr0_ss", NULL); + clk = davinci_clk_init(&scr1_ss_clk); + clk_register_clkdev(clk, "scr1_ss", NULL); + clk = davinci_clk_init(&scr2_ss_clk); + clk_register_clkdev(clk, "scr2_ss", NULL); + clk = davinci_clk_init(&dmax_clk); + clk_register_clkdev(clk, "dmax", NULL); + clk = davinci_clk_init(&tpcc_clk); + clk_register_clkdev(clk, "tpcc", NULL); + clk = davinci_clk_init(&tptc0_clk); + clk_register_clkdev(clk, "tptc0", NULL); + clk = davinci_clk_init(&tptc1_clk); + clk_register_clkdev(clk, "tptc1", NULL); + clk = davinci_clk_init(&mmcsd_clk); + clk_register_clkdev(clk, NULL, "da830-mmc.0"); + clk = davinci_clk_init(&uart0_clk); + clk_register_clkdev(clk, NULL, "serial8250.0"); + clk = davinci_clk_init(&uart1_clk); + clk_register_clkdev(clk, NULL, "serial8250.1"); + clk = davinci_clk_init(&uart2_clk); + clk_register_clkdev(clk, NULL, "serial8250.2"); + clk = davinci_clk_init(&spi0_clk); + clk_register_clkdev(clk, NULL, "spi_davinci.0"); + clk = davinci_clk_init(&spi1_clk); + clk_register_clkdev(clk, NULL, "spi_davinci.1"); + clk = davinci_clk_init(&ecap0_clk); + clk_register_clkdev(clk, "ecap0", NULL); + clk = davinci_clk_init(&ecap1_clk); + clk_register_clkdev(clk, "ecap1", NULL); + clk = davinci_clk_init(&ecap2_clk); + clk_register_clkdev(clk, "ecap2", NULL); + clk = davinci_clk_init(&pwm0_clk); + clk_register_clkdev(clk, "pwm0", NULL); + clk = davinci_clk_init(&pwm1_clk); + clk_register_clkdev(clk, "pwm1", NULL); + clk = davinci_clk_init(&pwm2_clk); + clk_register_clkdev(clk, "pwm2", NULL); + clk = davinci_clk_init(&eqep0_clk); + clk_register_clkdev(clk, NULL, "eqep.0"); + clk = davinci_clk_init(&eqep1_clk); + clk_register_clkdev(clk, NULL, "eqep.1"); + clk = davinci_clk_init(&lcdc_clk); + clk_register_clkdev(clk, "fck", "da8xx_lcdc.0"); + clk = davinci_clk_init(&mcasp0_clk); + clk_register_clkdev(clk, NULL, "davinci-mcasp.0"); + clk = davinci_clk_init(&mcasp1_clk); + clk_register_clkdev(clk, NULL, "davinci-mcasp.1"); + clk = davinci_clk_init(&mcasp2_clk); + clk_register_clkdev(clk, NULL, "davinci-mcasp.2"); + clk = davinci_clk_init(&usb20_clk); + clk_register_clkdev(clk, "usb20", "musb-da8xx"); + clk = davinci_clk_init(&cppi41_clk); + clk_register_clkdev(clk, NULL, "cppi41-dmaengine"); + clk = davinci_clk_init(&aemif_clk); + clk_register_clkdev(clk, "aemif", NULL); + clk = davinci_clk_init(&aintc_clk); + clk_register_clkdev(clk, "aintc", NULL); + clk = davinci_clk_init(&secu_mgr_clk); + clk_register_clkdev(clk, "secu_mgr", NULL); + clk = davinci_clk_init(&emac_clk); + clk_register_clkdev(clk, NULL, "davinci_emac.1"); + clk = davinci_clk_init(&emac_clk); + clk_register_clkdev(clk, "fck", "davinci_mdio.0"); + clk = davinci_clk_init(&gpio_clk); + clk_register_clkdev(clk, "gpio", NULL); + clk = davinci_clk_init(&i2c1_clk); + clk_register_clkdev(clk, NULL, "i2c_davinci.2"); + clk = davinci_clk_init(&usb11_clk); + clk_register_clkdev(clk, "usb11", "ohci-da8xx"); + clk = davinci_clk_init(&emif3_clk); + clk_register_clkdev(clk, "emif3", NULL); + clk = davinci_clk_init(&arm_clk); + clk_register_clkdev(clk, "arm", NULL); + clk = davinci_clk_init(&rmii_clk); + clk_register_clkdev(clk, "rmii", NULL); +} /* * Device specific mux setup @@ -1200,7 +1253,6 @@ static const struct davinci_soc_info davinci_soc_info_da830 = { .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG, .ids = da830_ids, .ids_num = ARRAY_SIZE(da830_ids), - .cpu_clks = da830_clks, .psc_bases = da830_psc_bases, .psc_bases_num = ARRAY_SIZE(da830_psc_bases), .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, @@ -1224,6 +1276,6 @@ void __init da830_init(void) void __init da830_init_time(void) { - davinci_clk_init(davinci_soc_info_da830.cpu_clks); + da830_clk_init(); davinci_timer_init(); } diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 4da5b25..eaa05ac 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -518,71 +518,135 @@ static struct clk ecap2_clk = { .parent = &ecap_clk, }; -static struct clk_lookup da850_clks[] = { - CLK(NULL, "ref", &ref_clk), - CLK(NULL, "pll0", &pll0_clk), - CLK(NULL, "pll0_aux", &pll0_aux_clk), - CLK(NULL, "pll0_sysclk1", &pll0_sysclk1), - CLK(NULL, "pll0_sysclk2", &pll0_sysclk2), - CLK(NULL, "pll0_sysclk3", &pll0_sysclk3), - CLK(NULL, "pll0_sysclk4", &pll0_sysclk4), - CLK(NULL, "pll0_sysclk5", &pll0_sysclk5), - CLK(NULL, "pll0_sysclk6", &pll0_sysclk6), - CLK(NULL, "pll0_sysclk7", &pll0_sysclk7), - CLK(NULL, "pll1", &pll1_clk), - CLK(NULL, "pll1_aux", &pll1_aux_clk), - CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), - CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), - CLK(NULL, "async3", &async3_clk), - CLK("i2c_davinci.1", NULL, &i2c0_clk), - CLK(NULL, "timer0", &timerp64_0_clk), - CLK("davinci-wdt", NULL, &timerp64_1_clk), - CLK(NULL, "arm_rom", &arm_rom_clk), - CLK(NULL, "tpcc0", &tpcc0_clk), - CLK(NULL, "tptc0", &tptc0_clk), - CLK(NULL, "tptc1", &tptc1_clk), - CLK(NULL, "tpcc1", &tpcc1_clk), - CLK(NULL, "tptc2", &tptc2_clk), - CLK("pruss_uio", "pruss", &pruss_clk), - CLK("serial8250.0", NULL, &uart0_clk), - CLK("serial8250.1", NULL, &uart1_clk), - CLK("serial8250.2", NULL, &uart2_clk), - CLK(NULL, "aintc", &aintc_clk), - CLK(NULL, "gpio", &gpio_clk), - CLK("i2c_davinci.2", NULL, &i2c1_clk), - CLK(NULL, "emif3", &emif3_clk), - CLK(NULL, "arm", &arm_clk), - CLK(NULL, "rmii", &rmii_clk), - CLK("davinci_emac.1", NULL, &emac_clk), - CLK("davinci_mdio.0", "fck", &mdio_clk), - CLK("davinci-mcasp.0", NULL, &mcasp_clk), - CLK("davinci-mcbsp.0", NULL, &mcbsp0_clk), - CLK("davinci-mcbsp.1", NULL, &mcbsp1_clk), - CLK("da8xx_lcdc.0", "fck", &lcdc_clk), - CLK("da830-mmc.0", NULL, &mmcsd0_clk), - CLK("da830-mmc.1", NULL, &mmcsd1_clk), - CLK("ti-aemif", NULL, &aemif_clk), - CLK("davinci-nand.0", "aemif", &aemif_nand_clk), - CLK("ohci-da8xx", "usb11", &usb11_clk), - CLK("musb-da8xx", "usb20", &usb20_clk), - CLK("cppi41-dmaengine", NULL, &cppi41_clk), - CLK("spi_davinci.0", NULL, &spi0_clk), - CLK("spi_davinci.1", NULL, &spi1_clk), - CLK("vpif", NULL, &vpif_clk), - CLK("ahci_da850", "fck", &sata_clk), - CLK("davinci-rproc.0", NULL, &dsp_clk), - CLK(NULL, NULL, &ehrpwm_clk), - CLK("ehrpwm.0", "fck", &ehrpwm0_clk), - CLK("ehrpwm.1", "fck", &ehrpwm1_clk), - CLK(NULL, NULL, &ehrpwm_tbclk), - CLK("ehrpwm.0", "tbclk", &ehrpwm0_tbclk), - CLK("ehrpwm.1", "tbclk", &ehrpwm1_tbclk), - CLK(NULL, NULL, &ecap_clk), - CLK("ecap.0", "fck", &ecap0_clk), - CLK("ecap.1", "fck", &ecap1_clk), - CLK("ecap.2", "fck", &ecap2_clk), - CLK(NULL, NULL, NULL), -}; +static __init void da850_clk_init(void) +{ + struct clk *clk; + + clk = davinci_clk_init(&ref_clk); + clk_register_clkdev(clk, "ref", NULL); + clk = davinci_clk_init(&pll0_clk); + clk_register_clkdev(clk, "pll0", NULL); + clk = davinci_clk_init(&pll0_aux_clk); + clk_register_clkdev(clk, "pll0_aux", NULL); + clk = davinci_clk_init(&pll0_sysclk1); + clk_register_clkdev(clk, "pll0_sysclk1", NULL); + clk = davinci_clk_init(&pll0_sysclk2); + clk_register_clkdev(clk, "pll0_sysclk2", NULL); + clk = davinci_clk_init(&pll0_sysclk3); + clk_register_clkdev(clk, "pll0_sysclk3", NULL); + clk = davinci_clk_init(&pll0_sysclk4); + clk_register_clkdev(clk, "pll0_sysclk4", NULL); + clk = davinci_clk_init(&pll0_sysclk5); + clk_register_clkdev(clk, "pll0_sysclk5", NULL); + clk = davinci_clk_init(&pll0_sysclk6); + clk_register_clkdev(clk, "pll0_sysclk6", NULL); + clk = davinci_clk_init(&pll0_sysclk7); + clk_register_clkdev(clk, "pll0_sysclk7", NULL); + clk = davinci_clk_init(&pll1_clk); + clk_register_clkdev(clk, "pll1", NULL); + clk = davinci_clk_init(&pll1_aux_clk); + clk_register_clkdev(clk, "pll1_aux", NULL); + clk = davinci_clk_init(&pll1_sysclk2); + clk_register_clkdev(clk, "pll1_sysclk2", NULL); + clk = davinci_clk_init(&pll1_sysclk3); + clk_register_clkdev(clk, "pll1_sysclk3", NULL); + clk = davinci_clk_init(&async3_clk); + clk_register_clkdev(clk, "async3", NULL); + clk = davinci_clk_init(&i2c0_clk); + clk_register_clkdev(clk, NULL, "i2c_davinci.1"); + clk = davinci_clk_init(&timerp64_0_clk); + clk_register_clkdev(clk, "timer0", NULL); + clk = davinci_clk_init(&timerp64_1_clk); + clk_register_clkdev(clk, NULL, "davinci-wdt"); + clk = davinci_clk_init(&arm_rom_clk); + clk_register_clkdev(clk, "arm_rom", NULL); + clk = davinci_clk_init(&tpcc0_clk); + clk_register_clkdev(clk, "tpcc0", NULL); + clk = davinci_clk_init(&tptc0_clk); + clk_register_clkdev(clk, "tptc0", NULL); + clk = davinci_clk_init(&tptc1_clk); + clk_register_clkdev(clk, "tptc1", NULL); + clk = davinci_clk_init(&tpcc1_clk); + clk_register_clkdev(clk, "tpcc1", NULL); + clk = davinci_clk_init(&tptc2_clk); + clk_register_clkdev(clk, "tptc2", NULL); + clk = davinci_clk_init(&pruss_clk); + clk_register_clkdev(clk, "pruss", "pruss_uio"); + clk = davinci_clk_init(&uart0_clk); + clk_register_clkdev(clk, NULL, "serial8250.0"); + clk = davinci_clk_init(&uart1_clk); + clk_register_clkdev(clk, NULL, "serial8250.1"); + clk = davinci_clk_init(&uart2_clk); + clk_register_clkdev(clk, NULL, "serial8250.2"); + clk = davinci_clk_init(&aintc_clk); + clk_register_clkdev(clk, "aintc", NULL); + clk = davinci_clk_init(&gpio_clk); + clk_register_clkdev(clk, "gpio", NULL); + clk = davinci_clk_init(&i2c1_clk); + clk_register_clkdev(clk, NULL, "i2c_davinci.2"); + clk = davinci_clk_init(&emif3_clk); + clk_register_clkdev(clk, "emif3", NULL); + clk = davinci_clk_init(&arm_clk); + clk_register_clkdev(clk, "arm", NULL); + clk = davinci_clk_init(&rmii_clk); + clk_register_clkdev(clk, "rmii", NULL); + clk = davinci_clk_init(&emac_clk); + clk_register_clkdev(clk, NULL, "davinci_emac.1"); + clk = davinci_clk_init(&mdio_clk); + clk_register_clkdev(clk, "fck", "davinci_mdio.0"); + clk = davinci_clk_init(&mcasp_clk); + clk_register_clkdev(clk, NULL, "davinci-mcasp.0"); + clk = davinci_clk_init(&mcbsp0_clk); + clk_register_clkdev(clk, NULL, "davinci-mcbsp.0"); + clk = davinci_clk_init(&mcbsp1_clk); + clk_register_clkdev(clk, NULL, "davinci-mcbsp.1"); + clk = davinci_clk_init(&lcdc_clk); + clk_register_clkdev(clk, "fck", "da8xx_lcdc.0"); + clk = davinci_clk_init(&mmcsd0_clk); + clk_register_clkdev(clk, NULL, "da830-mmc.0"); + clk = davinci_clk_init(&mmcsd1_clk); + clk_register_clkdev(clk, NULL, "da830-mmc.1"); + clk = davinci_clk_init(&aemif_clk); + clk_register_clkdev(clk, NULL, "ti-aemif"); + clk = davinci_clk_init(&aemif_nand_clk); + clk_register_clkdev(clk, "aemif", "davinci-nand.0"); + clk = davinci_clk_init(&usb11_clk); + clk_register_clkdev(clk, "usb11", "ohci-da8xx"); + clk = davinci_clk_init(&usb20_clk); + clk_register_clkdev(clk, "usb20", "musb-da8xx"); + clk = davinci_clk_init(&cppi41_clk); + clk_register_clkdev(clk, NULL, "cppi41-dmaengine"); + clk = davinci_clk_init(&spi0_clk); + clk_register_clkdev(clk, NULL, "spi_davinci.0"); + clk = davinci_clk_init(&spi1_clk); + clk_register_clkdev(clk, NULL, "spi_davinci.1"); + clk = davinci_clk_init(&vpif_clk); + clk_register_clkdev(clk, NULL, "vpif"); + clk = davinci_clk_init(&sata_clk); + clk_register_clkdev(clk, "fck", "ahci_da850"); + clk = davinci_clk_init(&dsp_clk); + clk_register_clkdev(clk, NULL, "davinci-rproc.0"); + clk = davinci_clk_init(&ehrpwm_clk); + clk_register_clkdev(clk, NULL, NULL); + clk = davinci_clk_init(&ehrpwm0_clk); + clk_register_clkdev(clk, "fck", "ehrpwm.0"); + clk = davinci_clk_init(&ehrpwm1_clk); + clk_register_clkdev(clk, "fck", "ehrpwm.1"); + clk = davinci_clk_init(&ehrpwm_tbclk); + clk_register_clkdev(clk, NULL, NULL); + clk = davinci_clk_init(&ehrpwm0_tbclk); + clk_register_clkdev(clk, "tbclk", "ehrpwm.0"); + clk = davinci_clk_init(&ehrpwm1_tbclk); + clk_register_clkdev(clk, "tbclk", "ehrpwm.1"); + clk = davinci_clk_init(&ecap_clk); + clk_register_clkdev(clk, NULL, NULL); + clk = davinci_clk_init(&ecap0_clk); + clk_register_clkdev(clk, "fck", "ecap.0"); + clk = davinci_clk_init(&ecap1_clk); + clk_register_clkdev(clk, "fck", "ecap.1"); + clk = davinci_clk_init(&ecap2_clk); + clk_register_clkdev(clk, "fck", "ecap.2"); +} /* * Device specific mux setup @@ -1353,7 +1417,6 @@ static const struct davinci_soc_info davinci_soc_info_da850 = { .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG, .ids = da850_ids, .ids_num = ARRAY_SIZE(da850_ids), - .cpu_clks = da850_clks, .psc_bases = da850_psc_bases, .psc_bases_num = ARRAY_SIZE(da850_psc_bases), .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, @@ -1396,6 +1459,6 @@ void __init da850_init(void) void __init da850_init_time(void) { - davinci_clk_init(davinci_soc_info_da850.cpu_clks); + da850_clk_init(); davinci_timer_init(); } diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index fe5e15a..c9a79b2 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -1046,9 +1046,6 @@ static struct clk sata_refclk = { .set_rate = davinci_simple_set_rate, }; -static struct clk_lookup sata_refclk_lookup = - CLK("ahci_da850", "refclk", &sata_refclk); - int __init da850_register_sata_refclk(int rate) { int ret; @@ -1058,7 +1055,7 @@ int __init da850_register_sata_refclk(int rate) if (ret) return ret; - clkdev_add(&sata_refclk_lookup); + clk_register_clkdev(&sata_refclk, "refclk", "ahci_da850"); return 0; } diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index 40641c0..9e5cfa9 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -337,51 +337,95 @@ static struct clk usb_clk = { .lpsc = DAVINCI_LPSC_USB, }; -static struct clk_lookup dm355_clks[] = { - CLK(NULL, "ref", &ref_clk), - CLK(NULL, "pll1", &pll1_clk), - CLK(NULL, "pll1_sysclk1", &pll1_sysclk1), - CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), - CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), - CLK(NULL, "pll1_sysclk4", &pll1_sysclk4), - CLK(NULL, "pll1_aux", &pll1_aux_clk), - CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp), - CLK(NULL, "vpss_dac", &vpss_dac_clk), - CLK("vpss", "master", &vpss_master_clk), - CLK("vpss", "slave", &vpss_slave_clk), - CLK(NULL, "clkout1", &clkout1_clk), - CLK(NULL, "clkout2", &clkout2_clk), - CLK(NULL, "pll2", &pll2_clk), - CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), - CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp), - CLK(NULL, "clkout3", &clkout3_clk), - CLK(NULL, "arm", &arm_clk), - CLK(NULL, "mjcp", &mjcp_clk), - CLK("serial8250.0", NULL, &uart0_clk), - CLK("serial8250.1", NULL, &uart1_clk), - CLK("serial8250.2", NULL, &uart2_clk), - CLK("i2c_davinci.1", NULL, &i2c_clk), - CLK("davinci-mcbsp.0", NULL, &asp0_clk), - CLK("davinci-mcbsp.1", NULL, &asp1_clk), - CLK("dm6441-mmc.0", NULL, &mmcsd0_clk), - CLK("dm6441-mmc.1", NULL, &mmcsd1_clk), - CLK("spi_davinci.0", NULL, &spi0_clk), - CLK("spi_davinci.1", NULL, &spi1_clk), - CLK("spi_davinci.2", NULL, &spi2_clk), - CLK(NULL, "gpio", &gpio_clk), - CLK(NULL, "aemif", &aemif_clk), - CLK(NULL, "pwm0", &pwm0_clk), - CLK(NULL, "pwm1", &pwm1_clk), - CLK(NULL, "pwm2", &pwm2_clk), - CLK(NULL, "pwm3", &pwm3_clk), - CLK(NULL, "timer0", &timer0_clk), - CLK(NULL, "timer1", &timer1_clk), - CLK("davinci-wdt", NULL, &timer2_clk), - CLK(NULL, "timer3", &timer3_clk), - CLK(NULL, "rto", &rto_clk), - CLK(NULL, "usb", &usb_clk), - CLK(NULL, NULL, NULL), -}; +static __init void dm355_clk_init(void) +{ + struct clk *clk; + + clk = davinci_clk_init(&ref_clk); + clk_register_clkdev(clk, "ref", NULL); + clk = davinci_clk_init(&pll1_clk); + clk_register_clkdev(clk, "pll1", NULL); + clk = davinci_clk_init(&pll1_sysclk1); + clk_register_clkdev(clk, "pll1_sysclk1", NULL); + clk = davinci_clk_init(&pll1_sysclk2); + clk_register_clkdev(clk, "pll1_sysclk2", NULL); + clk = davinci_clk_init(&pll1_sysclk3); + clk_register_clkdev(clk, "pll1_sysclk3", NULL); + clk = davinci_clk_init(&pll1_sysclk4); + clk_register_clkdev(clk, "pll1_sysclk4", NULL); + clk = davinci_clk_init(&pll1_aux_clk); + clk_register_clkdev(clk, "pll1_aux", NULL); + clk = davinci_clk_init(&pll1_sysclkbp); + clk_register_clkdev(clk, "pll1_sysclkbp", NULL); + clk = davinci_clk_init(&vpss_dac_clk); + clk_register_clkdev(clk, "vpss_dac", NULL); + clk = davinci_clk_init(&vpss_master_clk); + clk_register_clkdev(clk, "master", "vpss"); + clk = davinci_clk_init(&vpss_slave_clk); + clk_register_clkdev(clk, "slave", "vpss"); + clk = davinci_clk_init(&clkout1_clk); + clk_register_clkdev(clk, "clkout1", NULL); + clk = davinci_clk_init(&clkout2_clk); + clk_register_clkdev(clk, "clkout2", NULL); + clk = davinci_clk_init(&pll2_clk); + clk_register_clkdev(clk, "pll2", NULL); + clk = davinci_clk_init(&pll2_sysclk1); + clk_register_clkdev(clk, "pll2_sysclk1", NULL); + clk = davinci_clk_init(&pll2_sysclkbp); + clk_register_clkdev(clk, "pll2_sysclkbp", NULL); + clk = davinci_clk_init(&clkout3_clk); + clk_register_clkdev(clk, "clkout3", NULL); + clk = davinci_clk_init(&arm_clk); + clk_register_clkdev(clk, "arm", NULL); + clk = davinci_clk_init(&mjcp_clk); + clk_register_clkdev(clk, "mjcp", NULL); + clk = davinci_clk_init(&uart0_clk); + clk_register_clkdev(clk, NULL, "serial8250.0"); + clk = davinci_clk_init(&uart1_clk); + clk_register_clkdev(clk, NULL, "serial8250.1"); + clk = davinci_clk_init(&uart2_clk); + clk_register_clkdev(clk, NULL, "serial8250.2"); + clk = davinci_clk_init(&i2c_clk); + clk_register_clkdev(clk, NULL, "i2c_davinci.1"); + clk = davinci_clk_init(&asp0_clk); + clk_register_clkdev(clk, NULL, "davinci-mcbsp.0"); + clk = davinci_clk_init(&asp1_clk); + clk_register_clkdev(clk, NULL, "davinci-mcbsp.1"); + clk = davinci_clk_init(&mmcsd0_clk); + clk_register_clkdev(clk, NULL, "dm6441-mmc.0"); + clk = davinci_clk_init(&mmcsd1_clk); + clk_register_clkdev(clk, NULL, "dm6441-mmc.1"); + clk = davinci_clk_init(&spi0_clk); + clk_register_clkdev(clk, NULL, "spi_davinci.0"); + clk = davinci_clk_init(&spi1_clk); + clk_register_clkdev(clk, NULL, "spi_davinci.1"); + clk = davinci_clk_init(&spi2_clk); + clk_register_clkdev(clk, NULL, "spi_davinci.2"); + clk = davinci_clk_init(&gpio_clk); + clk_register_clkdev(clk, "gpio", NULL); + clk = davinci_clk_init(&aemif_clk); + clk_register_clkdev(clk, "aemif", NULL); + clk = davinci_clk_init(&pwm0_clk); + clk_register_clkdev(clk, "pwm0", NULL); + clk = davinci_clk_init(&pwm1_clk); + clk_register_clkdev(clk, "pwm1", NULL); + clk = davinci_clk_init(&pwm2_clk); + clk_register_clkdev(clk, "pwm2", NULL); + clk = davinci_clk_init(&pwm3_clk); + clk_register_clkdev(clk, "pwm3", NULL); + clk = davinci_clk_init(&timer0_clk); + clk_register_clkdev(clk, "timer0", NULL); + clk = davinci_clk_init(&timer1_clk); + clk_register_clkdev(clk, "timer1", NULL); + clk = davinci_clk_init(&timer2_clk); + clk_register_clkdev(clk, NULL, "davinci-wdt"); + clk = davinci_clk_init(&timer3_clk); + clk_register_clkdev(clk, "timer3", NULL); + clk = davinci_clk_init(&rto_clk); + clk_register_clkdev(clk, "rto", NULL); + clk = davinci_clk_init(&usb_clk); + clk_register_clkdev(clk, "usb", NULL); +} /*----------------------------------------------------------------------*/ @@ -1012,7 +1056,6 @@ static const struct davinci_soc_info davinci_soc_info_dm355 = { .jtag_id_reg = 0x01c40028, .ids = dm355_ids, .ids_num = ARRAY_SIZE(dm355_ids), - .cpu_clks = dm355_clks, .psc_bases = dm355_psc_bases, .psc_bases_num = ARRAY_SIZE(dm355_psc_bases), .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, @@ -1047,7 +1090,7 @@ void __init dm355_init(void) void __init dm355_init_time(void) { - davinci_clk_init(davinci_soc_info_dm355.cpu_clks); + dm355_clk_init(); davinci_timer_init(); } diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 0789ac6..0cf4ab4 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -425,66 +425,125 @@ static struct clk mjcp_clk = { .lpsc = DM365_LPSC_MJCP, }; -static struct clk_lookup dm365_clks[] = { - CLK(NULL, "ref", &ref_clk), - CLK(NULL, "pll1", &pll1_clk), - CLK(NULL, "pll1_aux", &pll1_aux_clk), - CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp), - CLK(NULL, "clkout0", &clkout0_clk), - CLK(NULL, "pll1_sysclk1", &pll1_sysclk1), - CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), - CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), - CLK(NULL, "pll1_sysclk4", &pll1_sysclk4), - CLK(NULL, "pll1_sysclk5", &pll1_sysclk5), - CLK(NULL, "pll1_sysclk6", &pll1_sysclk6), - CLK(NULL, "pll1_sysclk7", &pll1_sysclk7), - CLK(NULL, "pll1_sysclk8", &pll1_sysclk8), - CLK(NULL, "pll1_sysclk9", &pll1_sysclk9), - CLK(NULL, "pll2", &pll2_clk), - CLK(NULL, "pll2_aux", &pll2_aux_clk), - CLK(NULL, "clkout1", &clkout1_clk), - CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), - CLK(NULL, "pll2_sysclk2", &pll2_sysclk2), - CLK(NULL, "pll2_sysclk3", &pll2_sysclk3), - CLK(NULL, "pll2_sysclk4", &pll2_sysclk4), - CLK(NULL, "pll2_sysclk5", &pll2_sysclk5), - CLK(NULL, "pll2_sysclk6", &pll2_sysclk6), - CLK(NULL, "pll2_sysclk7", &pll2_sysclk7), - CLK(NULL, "pll2_sysclk8", &pll2_sysclk8), - CLK(NULL, "pll2_sysclk9", &pll2_sysclk9), - CLK(NULL, "vpss_dac", &vpss_dac_clk), - CLK("vpss", "master", &vpss_master_clk), - CLK("vpss", "slave", &vpss_slave_clk), - CLK(NULL, "arm", &arm_clk), - CLK("serial8250.0", NULL, &uart0_clk), - CLK("serial8250.1", NULL, &uart1_clk), - CLK("i2c_davinci.1", NULL, &i2c_clk), - CLK("da830-mmc.0", NULL, &mmcsd0_clk), - CLK("da830-mmc.1", NULL, &mmcsd1_clk), - CLK("spi_davinci.0", NULL, &spi0_clk), - CLK("spi_davinci.1", NULL, &spi1_clk), - CLK("spi_davinci.2", NULL, &spi2_clk), - CLK("spi_davinci.3", NULL, &spi3_clk), - CLK("spi_davinci.4", NULL, &spi4_clk), - CLK(NULL, "gpio", &gpio_clk), - CLK(NULL, "aemif", &aemif_clk), - CLK(NULL, "pwm0", &pwm0_clk), - CLK(NULL, "pwm1", &pwm1_clk), - CLK(NULL, "pwm2", &pwm2_clk), - CLK(NULL, "pwm3", &pwm3_clk), - CLK(NULL, "timer0", &timer0_clk), - CLK(NULL, "timer1", &timer1_clk), - CLK("davinci-wdt", NULL, &timer2_clk), - CLK(NULL, "timer3", &timer3_clk), - CLK(NULL, "usb", &usb_clk), - CLK("davinci_emac.1", NULL, &emac_clk), - CLK("davinci_mdio.0", "fck", &emac_clk), - CLK("davinci_voicecodec", NULL, &voicecodec_clk), - CLK("davinci-mcbsp", NULL, &asp0_clk), - CLK(NULL, "rto", &rto_clk), - CLK(NULL, "mjcp", &mjcp_clk), - CLK(NULL, NULL, NULL), -}; +static __init void dm365_clk_init(void) +{ + struct clk *clk; + + clk = davinci_clk_init(&ref_clk); + clk_register_clkdev(clk, "ref", NULL); + clk = davinci_clk_init(&pll1_clk); + clk_register_clkdev(clk, "pll1", NULL); + clk = davinci_clk_init(&pll1_aux_clk); + clk_register_clkdev(clk, "pll1_aux", NULL); + clk = davinci_clk_init(&pll1_sysclkbp); + clk_register_clkdev(clk, "pll1_sysclkbp", NULL); + clk = davinci_clk_init(&clkout0_clk); + clk_register_clkdev(clk, "clkout0", NULL); + clk = davinci_clk_init(&pll1_sysclk1); + clk_register_clkdev(clk, "pll1_sysclk1", NULL); + clk = davinci_clk_init(&pll1_sysclk2); + clk_register_clkdev(clk, "pll1_sysclk2", NULL); + clk = davinci_clk_init(&pll1_sysclk3); + clk_register_clkdev(clk, "pll1_sysclk3", NULL); + clk = davinci_clk_init(&pll1_sysclk4); + clk_register_clkdev(clk, "pll1_sysclk4", NULL); + clk = davinci_clk_init(&pll1_sysclk5); + clk_register_clkdev(clk, "pll1_sysclk5", NULL); + clk = davinci_clk_init(&pll1_sysclk6); + clk_register_clkdev(clk, "pll1_sysclk6", NULL); + clk = davinci_clk_init(&pll1_sysclk7); + clk_register_clkdev(clk, "pll1_sysclk7", NULL); + clk = davinci_clk_init(&pll1_sysclk8); + clk_register_clkdev(clk, "pll1_sysclk8", NULL); + clk = davinci_clk_init(&pll1_sysclk9); + clk_register_clkdev(clk, "pll1_sysclk9", NULL); + clk = davinci_clk_init(&pll2_clk); + clk_register_clkdev(clk, "pll2", NULL); + clk = davinci_clk_init(&pll2_aux_clk); + clk_register_clkdev(clk, "pll2_aux", NULL); + clk = davinci_clk_init(&clkout1_clk); + clk_register_clkdev(clk, "clkout1", NULL); + clk = davinci_clk_init(&pll2_sysclk1); + clk_register_clkdev(clk, "pll2_sysclk1", NULL); + clk = davinci_clk_init(&pll2_sysclk2); + clk_register_clkdev(clk, "pll2_sysclk2", NULL); + clk = davinci_clk_init(&pll2_sysclk3); + clk_register_clkdev(clk, "pll2_sysclk3", NULL); + clk = davinci_clk_init(&pll2_sysclk4); + clk_register_clkdev(clk, "pll2_sysclk4", NULL); + clk = davinci_clk_init(&pll2_sysclk5); + clk_register_clkdev(clk, "pll2_sysclk5", NULL); + clk = davinci_clk_init(&pll2_sysclk6); + clk_register_clkdev(clk, "pll2_sysclk6", NULL); + clk = davinci_clk_init(&pll2_sysclk7); + clk_register_clkdev(clk, "pll2_sysclk7", NULL); + clk = davinci_clk_init(&pll2_sysclk8); + clk_register_clkdev(clk, "pll2_sysclk8", NULL); + clk = davinci_clk_init(&pll2_sysclk9); + clk_register_clkdev(clk, "pll2_sysclk9", NULL); + clk = davinci_clk_init(&vpss_dac_clk); + clk_register_clkdev(clk, "vpss_dac", NULL); + clk = davinci_clk_init(&vpss_master_clk); + clk_register_clkdev(clk, "master", "vpss"); + clk = davinci_clk_init(&vpss_slave_clk); + clk_register_clkdev(clk, "slave", "vpss"); + clk = davinci_clk_init(&arm_clk); + clk_register_clkdev(clk, "arm", NULL); + clk = davinci_clk_init(&uart0_clk); + clk_register_clkdev(clk, NULL, "serial8250.0"); + clk = davinci_clk_init(&uart1_clk); + clk_register_clkdev(clk, NULL, "serial8250.1"); + clk = davinci_clk_init(&i2c_clk); + clk_register_clkdev(clk, NULL, "i2c_davinci.1"); + clk = davinci_clk_init(&mmcsd0_clk); + clk_register_clkdev(clk, NULL, "da830-mmc.0"); + clk = davinci_clk_init(&mmcsd1_clk); + clk_register_clkdev(clk, NULL, "da830-mmc.1"); + clk = davinci_clk_init(&spi0_clk); + clk_register_clkdev(clk, NULL, "spi_davinci.0"); + clk = davinci_clk_init(&spi1_clk); + clk_register_clkdev(clk, NULL, "spi_davinci.1"); + clk = davinci_clk_init(&spi2_clk); + clk_register_clkdev(clk, NULL, "spi_davinci.2"); + clk = davinci_clk_init(&spi3_clk); + clk_register_clkdev(clk, NULL, "spi_davinci.3"); + clk = davinci_clk_init(&spi4_clk); + clk_register_clkdev(clk, NULL, "spi_davinci.4"); + clk = davinci_clk_init(&gpio_clk); + clk_register_clkdev(clk, "gpio", NULL); + clk = davinci_clk_init(&aemif_clk); + clk_register_clkdev(clk, "aemif", NULL); + clk = davinci_clk_init(&pwm0_clk); + clk_register_clkdev(clk, "pwm0", NULL); + clk = davinci_clk_init(&pwm1_clk); + clk_register_clkdev(clk, "pwm1", NULL); + clk = davinci_clk_init(&pwm2_clk); + clk_register_clkdev(clk, "pwm2", NULL); + clk = davinci_clk_init(&pwm3_clk); + clk_register_clkdev(clk, "pwm3", NULL); + clk = davinci_clk_init(&timer0_clk); + clk_register_clkdev(clk, "timer0", NULL); + clk = davinci_clk_init(&timer1_clk); + clk_register_clkdev(clk, "timer1", NULL); + clk = davinci_clk_init(&timer2_clk); + clk_register_clkdev(clk, NULL, "davinci-wdt"); + clk = davinci_clk_init(&timer3_clk); + clk_register_clkdev(clk, "timer3", NULL); + clk = davinci_clk_init(&usb_clk); + clk_register_clkdev(clk, "usb", NULL); + clk = davinci_clk_init(&emac_clk); + clk_register_clkdev(clk, NULL, "davinci_emac.1"); + clk = davinci_clk_init(&emac_clk); + clk_register_clkdev(clk, "fck", "davinci_mdio.0"); + clk = davinci_clk_init(&voicecodec_clk); + clk_register_clkdev(clk, NULL, "davinci_voicecodec"); + clk = davinci_clk_init(&asp0_clk); + clk_register_clkdev(clk, NULL, "davinci-mcbsp"); + clk = davinci_clk_init(&rto_clk); + clk_register_clkdev(clk, "rto", NULL); + clk = davinci_clk_init(&mjcp_clk); + clk_register_clkdev(clk, "mjcp", NULL); +} /*----------------------------------------------------------------------*/ @@ -1116,7 +1175,6 @@ static const struct davinci_soc_info davinci_soc_info_dm365 = { .jtag_id_reg = 0x01c40028, .ids = dm365_ids, .ids_num = ARRAY_SIZE(dm365_ids), - .cpu_clks = dm365_clks, .psc_bases = dm365_psc_bases, .psc_bases_num = ARRAY_SIZE(dm365_psc_bases), .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, @@ -1172,7 +1230,7 @@ void __init dm365_init(void) void __init dm365_init_time(void) { - davinci_clk_init(davinci_soc_info_dm365.cpu_clks); + dm365_clk_init(); davinci_timer_init(); } diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index a1a2433..769ce29 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -285,47 +285,87 @@ static struct clk timer2_clk = { .usecount = 1, /* REVISIT: why can't this be disabled? */ }; -static struct clk_lookup dm644x_clks[] = { - CLK(NULL, "ref", &ref_clk), - CLK(NULL, "pll1", &pll1_clk), - CLK(NULL, "pll1_sysclk1", &pll1_sysclk1), - CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), - CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), - CLK(NULL, "pll1_sysclk5", &pll1_sysclk5), - CLK(NULL, "pll1_aux", &pll1_aux_clk), - CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp), - CLK(NULL, "pll2", &pll2_clk), - CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), - CLK(NULL, "pll2_sysclk2", &pll2_sysclk2), - CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp), - CLK(NULL, "dsp", &dsp_clk), - CLK(NULL, "arm", &arm_clk), - CLK(NULL, "vicp", &vicp_clk), - CLK("vpss", "master", &vpss_master_clk), - CLK("vpss", "slave", &vpss_slave_clk), - CLK(NULL, "arm", &arm_clk), - CLK("serial8250.0", NULL, &uart0_clk), - CLK("serial8250.1", NULL, &uart1_clk), - CLK("serial8250.2", NULL, &uart2_clk), - CLK("davinci_emac.1", NULL, &emac_clk), - CLK("davinci_mdio.0", "fck", &emac_clk), - CLK("i2c_davinci.1", NULL, &i2c_clk), - CLK("palm_bk3710", NULL, &ide_clk), - CLK("davinci-mcbsp", NULL, &asp_clk), - CLK("dm6441-mmc.0", NULL, &mmcsd_clk), - CLK(NULL, "spi", &spi_clk), - CLK(NULL, "gpio", &gpio_clk), - CLK(NULL, "usb", &usb_clk), - CLK(NULL, "vlynq", &vlynq_clk), - CLK(NULL, "aemif", &aemif_clk), - CLK(NULL, "pwm0", &pwm0_clk), - CLK(NULL, "pwm1", &pwm1_clk), - CLK(NULL, "pwm2", &pwm2_clk), - CLK(NULL, "timer0", &timer0_clk), - CLK(NULL, "timer1", &timer1_clk), - CLK("davinci-wdt", NULL, &timer2_clk), - CLK(NULL, NULL, NULL), -}; +static __init void dm644x_clk_init(void) +{ + struct clk *clk; + + clk = davinci_clk_init(&ref_clk); + clk_register_clkdev(clk, "ref", NULL); + clk = davinci_clk_init(&pll1_clk); + clk_register_clkdev(clk, "pll1", NULL); + clk = davinci_clk_init(&pll1_sysclk1); + clk_register_clkdev(clk, "pll1_sysclk1", NULL); + clk = davinci_clk_init(&pll1_sysclk2); + clk_register_clkdev(clk, "pll1_sysclk2", NULL); + clk = davinci_clk_init(&pll1_sysclk3); + clk_register_clkdev(clk, "pll1_sysclk3", NULL); + clk = davinci_clk_init(&pll1_sysclk5); + clk_register_clkdev(clk, "pll1_sysclk5", NULL); + clk = davinci_clk_init(&pll1_aux_clk); + clk_register_clkdev(clk, "pll1_aux", NULL); + clk = davinci_clk_init(&pll1_sysclkbp); + clk_register_clkdev(clk, "pll1_sysclkbp", NULL); + clk = davinci_clk_init(&pll2_clk); + clk_register_clkdev(clk, "pll2", NULL); + clk = davinci_clk_init(&pll2_sysclk1); + clk_register_clkdev(clk, "pll2_sysclk1", NULL); + clk = davinci_clk_init(&pll2_sysclk2); + clk_register_clkdev(clk, "pll2_sysclk2", NULL); + clk = davinci_clk_init(&pll2_sysclkbp); + clk_register_clkdev(clk, "pll2_sysclkbp", NULL); + clk = davinci_clk_init(&dsp_clk); + clk_register_clkdev(clk, "dsp", NULL); + clk = davinci_clk_init(&arm_clk); + clk_register_clkdev(clk, "arm", NULL); + clk = davinci_clk_init(&vicp_clk); + clk_register_clkdev(clk, "vicp", NULL); + clk = davinci_clk_init(&vpss_master_clk); + clk_register_clkdev(clk, "master", "vpss"); + clk = davinci_clk_init(&vpss_slave_clk); + clk_register_clkdev(clk, "slave", "vpss"); + clk = davinci_clk_init(&arm_clk); + clk_register_clkdev(clk, "arm", NULL); + clk = davinci_clk_init(&uart0_clk); + clk_register_clkdev(clk, NULL, "serial8250.0"); + clk = davinci_clk_init(&uart1_clk); + clk_register_clkdev(clk, NULL, "serial8250.1"); + clk = davinci_clk_init(&uart2_clk); + clk_register_clkdev(clk, NULL, "serial8250.2"); + clk = davinci_clk_init(&emac_clk); + clk_register_clkdev(clk, NULL, "davinci_emac.1"); + clk = davinci_clk_init(&emac_clk); + clk_register_clkdev(clk, "fck", "davinci_mdio.0"); + clk = davinci_clk_init(&i2c_clk); + clk_register_clkdev(clk, NULL, "i2c_davinci.1"); + clk = davinci_clk_init(&ide_clk); + clk_register_clkdev(clk, NULL, "palm_bk3710"); + clk = davinci_clk_init(&asp_clk); + clk_register_clkdev(clk, NULL, "davinci-mcbsp"); + clk = davinci_clk_init(&mmcsd_clk); + clk_register_clkdev(clk, NULL, "dm6441-mmc.0"); + clk = davinci_clk_init(&spi_clk); + clk_register_clkdev(clk, "spi", NULL); + clk = davinci_clk_init(&gpio_clk); + clk_register_clkdev(clk, "gpio", NULL); + clk = davinci_clk_init(&usb_clk); + clk_register_clkdev(clk, "usb", NULL); + clk = davinci_clk_init(&vlynq_clk); + clk_register_clkdev(clk, "vlynq", NULL); + clk = davinci_clk_init(&aemif_clk); + clk_register_clkdev(clk, "aemif", NULL); + clk = davinci_clk_init(&pwm0_clk); + clk_register_clkdev(clk, "pwm0", NULL); + clk = davinci_clk_init(&pwm1_clk); + clk_register_clkdev(clk, "pwm1", NULL); + clk = davinci_clk_init(&pwm2_clk); + clk_register_clkdev(clk, "pwm2", NULL); + clk = davinci_clk_init(&timer0_clk); + clk_register_clkdev(clk, "timer0", NULL); + clk = davinci_clk_init(&timer1_clk); + clk_register_clkdev(clk, "timer1", NULL); + clk = davinci_clk_init(&timer2_clk); + clk_register_clkdev(clk, NULL, "davinci-wdt"); +} static struct emac_platform_data dm644x_emac_pdata = { .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET, @@ -905,7 +945,6 @@ static const struct davinci_soc_info davinci_soc_info_dm644x = { .jtag_id_reg = 0x01c40028, .ids = dm644x_ids, .ids_num = ARRAY_SIZE(dm644x_ids), - .cpu_clks = dm644x_clks, .psc_bases = dm644x_psc_bases, .psc_bases_num = ARRAY_SIZE(dm644x_psc_bases), .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, @@ -935,7 +974,7 @@ void __init dm644x_init(void) void __init dm644x_init_time(void) { - davinci_clk_init(davinci_soc_info_dm644x.cpu_clks); + dm644x_clk_init(); davinci_timer_init(); } diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index c518403..d75b4bc09 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -320,49 +320,91 @@ static struct clk vpif1_clk = { .flags = ALWAYS_ENABLED, }; -static struct clk_lookup dm646x_clks[] = { - CLK(NULL, "ref", &ref_clk), - CLK(NULL, "aux", &aux_clkin), - CLK(NULL, "pll1", &pll1_clk), - CLK(NULL, "pll1_sysclk", &pll1_sysclk1), - CLK(NULL, "pll1_sysclk", &pll1_sysclk2), - CLK(NULL, "pll1_sysclk", &pll1_sysclk3), - CLK(NULL, "pll1_sysclk", &pll1_sysclk4), - CLK(NULL, "pll1_sysclk", &pll1_sysclk5), - CLK(NULL, "pll1_sysclk", &pll1_sysclk6), - CLK(NULL, "pll1_sysclk", &pll1_sysclk8), - CLK(NULL, "pll1_sysclk", &pll1_sysclk9), - CLK(NULL, "pll1_sysclk", &pll1_sysclkbp), - CLK(NULL, "pll1_aux", &pll1_aux_clk), - CLK(NULL, "pll2", &pll2_clk), - CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), - CLK(NULL, "dsp", &dsp_clk), - CLK(NULL, "arm", &arm_clk), - CLK(NULL, "edma_cc", &edma_cc_clk), - CLK(NULL, "edma_tc0", &edma_tc0_clk), - CLK(NULL, "edma_tc1", &edma_tc1_clk), - CLK(NULL, "edma_tc2", &edma_tc2_clk), - CLK(NULL, "edma_tc3", &edma_tc3_clk), - CLK("serial8250.0", NULL, &uart0_clk), - CLK("serial8250.1", NULL, &uart1_clk), - CLK("serial8250.2", NULL, &uart2_clk), - CLK("i2c_davinci.1", NULL, &i2c_clk), - CLK(NULL, "gpio", &gpio_clk), - CLK("davinci-mcasp.0", NULL, &mcasp0_clk), - CLK("davinci-mcasp.1", NULL, &mcasp1_clk), - CLK(NULL, "aemif", &aemif_clk), - CLK("davinci_emac.1", NULL, &emac_clk), - CLK("davinci_mdio.0", "fck", &emac_clk), - CLK(NULL, "pwm0", &pwm0_clk), - CLK(NULL, "pwm1", &pwm1_clk), - CLK(NULL, "timer0", &timer0_clk), - CLK(NULL, "timer1", &timer1_clk), - CLK("davinci-wdt", NULL, &timer2_clk), - CLK("palm_bk3710", NULL, &ide_clk), - CLK(NULL, "vpif0", &vpif0_clk), - CLK(NULL, "vpif1", &vpif1_clk), - CLK(NULL, NULL, NULL), -}; +static __init void dm646x_clk_init(void) +{ + struct clk *clk; + + clk = davinci_clk_init(&ref_clk); + clk_register_clkdev(clk, "ref", NULL); + clk = davinci_clk_init(&aux_clkin); + clk_register_clkdev(clk, "aux", NULL); + clk = davinci_clk_init(&pll1_clk); + clk_register_clkdev(clk, "pll1", NULL); + clk = davinci_clk_init(&pll1_sysclk1); + clk_register_clkdev(clk, "pll1_sysclk", NULL); + clk = davinci_clk_init(&pll1_sysclk2); + clk_register_clkdev(clk, "pll1_sysclk", NULL); + clk = davinci_clk_init(&pll1_sysclk3); + clk_register_clkdev(clk, "pll1_sysclk", NULL); + clk = davinci_clk_init(&pll1_sysclk4); + clk_register_clkdev(clk, "pll1_sysclk", NULL); + clk = davinci_clk_init(&pll1_sysclk5); + clk_register_clkdev(clk, "pll1_sysclk", NULL); + clk = davinci_clk_init(&pll1_sysclk6); + clk_register_clkdev(clk, "pll1_sysclk", NULL); + clk = davinci_clk_init(&pll1_sysclk8); + clk_register_clkdev(clk, "pll1_sysclk", NULL); + clk = davinci_clk_init(&pll1_sysclk9); + clk_register_clkdev(clk, "pll1_sysclk", NULL); + clk = davinci_clk_init(&pll1_sysclkbp); + clk_register_clkdev(clk, "pll1_sysclk", NULL); + clk = davinci_clk_init(&pll1_aux_clk); + clk_register_clkdev(clk, "pll1_aux", NULL); + clk = davinci_clk_init(&pll2_clk); + clk_register_clkdev(clk, "pll2", NULL); + clk = davinci_clk_init(&pll2_sysclk1); + clk_register_clkdev(clk, "pll2_sysclk1", NULL); + clk = davinci_clk_init(&dsp_clk); + clk_register_clkdev(clk, "dsp", NULL); + clk = davinci_clk_init(&arm_clk); + clk_register_clkdev(clk, "arm", NULL); + clk = davinci_clk_init(&edma_cc_clk); + clk_register_clkdev(clk, "edma_cc", NULL); + clk = davinci_clk_init(&edma_tc0_clk); + clk_register_clkdev(clk, "edma_tc0", NULL); + clk = davinci_clk_init(&edma_tc1_clk); + clk_register_clkdev(clk, "edma_tc1", NULL); + clk = davinci_clk_init(&edma_tc2_clk); + clk_register_clkdev(clk, "edma_tc2", NULL); + clk = davinci_clk_init(&edma_tc3_clk); + clk_register_clkdev(clk, "edma_tc3", NULL); + clk = davinci_clk_init(&uart0_clk); + clk_register_clkdev(clk, NULL, "serial8250.0"); + clk = davinci_clk_init(&uart1_clk); + clk_register_clkdev(clk, NULL, "serial8250.1"); + clk = davinci_clk_init(&uart2_clk); + clk_register_clkdev(clk, NULL, "serial8250.2"); + clk = davinci_clk_init(&i2c_clk); + clk_register_clkdev(clk, NULL, "i2c_davinci.1"); + clk = davinci_clk_init(&gpio_clk); + clk_register_clkdev(clk, "gpio", NULL); + clk = davinci_clk_init(&mcasp0_clk); + clk_register_clkdev(clk, NULL, "davinci-mcasp.0"); + clk = davinci_clk_init(&mcasp1_clk); + clk_register_clkdev(clk, NULL, "davinci-mcasp.1"); + clk = davinci_clk_init(&aemif_clk); + clk_register_clkdev(clk, "aemif", NULL); + clk = davinci_clk_init(&emac_clk); + clk_register_clkdev(clk, NULL, "davinci_emac.1"); + clk = davinci_clk_init(&emac_clk); + clk_register_clkdev(clk, "fck", "davinci_mdio.0"); + clk = davinci_clk_init(&pwm0_clk); + clk_register_clkdev(clk, "pwm0", NULL); + clk = davinci_clk_init(&pwm1_clk); + clk_register_clkdev(clk, "pwm1", NULL); + clk = davinci_clk_init(&timer0_clk); + clk_register_clkdev(clk, "timer0", NULL); + clk = davinci_clk_init(&timer1_clk); + clk_register_clkdev(clk, "timer1", NULL); + clk = davinci_clk_init(&timer2_clk); + clk_register_clkdev(clk, NULL, "davinci-wdt"); + clk = davinci_clk_init(&ide_clk); + clk_register_clkdev(clk, NULL, "palm_bk3710"); + clk = davinci_clk_init(&vpif0_clk); + clk_register_clkdev(clk, "vpif0", NULL); + clk = davinci_clk_init(&vpif1_clk); + clk_register_clkdev(clk, "vpif1", NULL); +} static struct emac_platform_data dm646x_emac_pdata = { .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET, @@ -888,7 +930,6 @@ static const struct davinci_soc_info davinci_soc_info_dm646x = { .jtag_id_reg = 0x01c40028, .ids = dm646x_ids, .ids_num = ARRAY_SIZE(dm646x_ids), - .cpu_clks = dm646x_clks, .psc_bases = dm646x_psc_bases, .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases), .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, @@ -960,7 +1001,7 @@ void __init dm646x_init(void) void __init dm646x_init_time(void) { - davinci_clk_init(davinci_soc_info_dm646x.cpu_clks); + dm646x_clk_init(); davinci_timer_init(); } diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h index 19b9346..f0d5e858 100644 --- a/arch/arm/mach-davinci/include/mach/common.h +++ b/arch/arm/mach-davinci/include/mach/common.h @@ -53,7 +53,6 @@ struct davinci_soc_info { u32 jtag_id_reg; struct davinci_id *ids; unsigned long ids_num; - struct clk_lookup *cpu_clks; u32 *psc_bases; unsigned long psc_bases_num; u32 pinmux_base; diff --git a/arch/arm/mach-davinci/usb-da8xx.c b/arch/arm/mach-davinci/usb-da8xx.c index d480a02..a2e575e 100644 --- a/arch/arm/mach-davinci/usb-da8xx.c +++ b/arch/arm/mach-davinci/usb-da8xx.c @@ -133,9 +133,6 @@ static struct clk usb_refclkin = { .set_rate = davinci_simple_set_rate, }; -static struct clk_lookup usb_refclkin_lookup = - CLK(NULL, "usb_refclkin", &usb_refclkin); - /** * da8xx_register_usb_refclkin - register USB_REFCLKIN clock * @@ -154,7 +151,7 @@ int __init da8xx_register_usb_refclkin(int rate) if (ret) return ret; - clkdev_add(&usb_refclkin_lookup); + clk_register_clkdev(&usb_refclkin, "usb_refclkin", NULL); return 0; } @@ -262,9 +259,6 @@ static struct clk usb20_phy_clk = { .set_parent = usb20_phy_clk_set_parent, }; -static struct clk_lookup usb20_phy_clk_lookup = - CLK("da8xx-usb-phy", "usb20_phy", &usb20_phy_clk); - /** * da8xx_register_usb20_phy_clk - register USB0PHYCLKMUX clock * @@ -291,7 +285,7 @@ int __init da8xx_register_usb20_phy_clk(bool use_usb_refclkin) usb20_phy_clk.parent = parent; ret = clk_register(&usb20_phy_clk); if (!ret) - clkdev_add(&usb20_phy_clk_lookup); + clk_register_clkdev(&usb20_phy_clk, "usb20_phy", "da8xx-usb-phy"); clk_put(parent); @@ -324,9 +318,6 @@ static struct clk usb11_phy_clk = { .set_parent = usb11_phy_clk_set_parent, }; -static struct clk_lookup usb11_phy_clk_lookup = - CLK("da8xx-usb-phy", "usb11_phy", &usb11_phy_clk); - /** * da8xx_register_usb11_phy_clk - register USB1PHYCLKMUX clock * @@ -348,7 +339,7 @@ int __init da8xx_register_usb11_phy_clk(bool use_usb_refclkin) usb11_phy_clk.parent = parent; ret = clk_register(&usb11_phy_clk); if (!ret) - clkdev_add(&usb11_phy_clk_lookup); + clk_register_clkdev(&usb11_phy_clk, "usb11_phy", "da8xx-usb-phy"); clk_put(parent); -- 2.7.4 ^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v4 2/7] ARM: davinci: don't use static clk_lookup 2017-12-31 23:39 ` [PATCH v4 2/7] ARM: davinci: don't use static clk_lookup David Lechner @ 2018-01-04 11:10 ` Sekhar Nori 2018-01-04 17:43 ` David Lechner 0 siblings, 1 reply; 29+ messages in thread From: Sekhar Nori @ 2018-01-04 11:10 UTC (permalink / raw) To: linux-arm-kernel Hi David, On Monday 01 January 2018 05:09 AM, David Lechner wrote: > In preparation of moving to the common clock framework, usage of static > struct clk_lookup is removed. The common clock framework uses an opaque > struct clk, so we won't be able to use static tables as was previously > done. > > davinci_clk_init() is changed to init a single clock instead of a table > and an individual clk_register_clkdev() is added for each clock. > > Signed-off-by: David Lechner <david@lechnology.com> Is there a need for this considering in 6/7 you end up modifying quite a bit of this patch again? Thanks, Sekhar ^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v4 2/7] ARM: davinci: don't use static clk_lookup 2018-01-04 11:10 ` Sekhar Nori @ 2018-01-04 17:43 ` David Lechner 0 siblings, 0 replies; 29+ messages in thread From: David Lechner @ 2018-01-04 17:43 UTC (permalink / raw) To: linux-arm-kernel On 1/4/18 5:10 AM, Sekhar Nori wrote: > Hi David, > > On Monday 01 January 2018 05:09 AM, David Lechner wrote: >> In preparation of moving to the common clock framework, usage of static >> struct clk_lookup is removed. The common clock framework uses an opaque >> struct clk, so we won't be able to use static tables as was previously >> done. >> >> davinci_clk_init() is changed to init a single clock instead of a table >> and an individual clk_register_clkdev() is added for each clock. >> >> Signed-off-by: David Lechner <david@lechnology.com> > > Is there a need for this considering in 6/7 you end up modifying quite a > bit of this patch again? No, you are right. And I've been working ahead with device tree support so I think I want to do this a bit differently anyway. ^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v4 3/7] ARM: davinci: fix duplicate clocks 2017-12-31 23:39 [PATCH v4 0/7] ARM: davinci: convert to common clock framework David Lechner 2017-12-31 23:39 ` [PATCH v4 1/7] ARM: davinci: move davinci_clk_init() to init_time David Lechner 2017-12-31 23:39 ` [PATCH v4 2/7] ARM: davinci: don't use static clk_lookup David Lechner @ 2017-12-31 23:39 ` David Lechner 2018-01-04 11:12 ` Sekhar Nori 2017-12-31 23:39 ` [PATCH v4 4/7] ARM: davinci: remove davinci_set_refclk_rate() David Lechner ` (4 subsequent siblings) 7 siblings, 1 reply; 29+ messages in thread From: David Lechner @ 2017-12-31 23:39 UTC (permalink / raw) To: linux-arm-kernel There are a number of clocks that were duplicated because they are used by more than one device. It is no longer necessary to do this since we are explicitly calling clk_register_clkdev() for each clock. In da830.c, some clocks were using the same LPSC, which would cause problems with reference counting, so these are combinded into one clock each. In da850.c the duplicate clocks had already been fixed by creating dummy child clocks, so these clocks are removed. Signed-off-by: David Lechner <david@lechnology.com> --- arch/arm/mach-davinci/da830.c | 65 ++++++-------------------------------- arch/arm/mach-davinci/da850.c | 72 ------------------------------------------ arch/arm/mach-davinci/dm365.c | 1 - arch/arm/mach-davinci/dm644x.c | 3 -- arch/arm/mach-davinci/dm646x.c | 1 - 5 files changed, 9 insertions(+), 133 deletions(-) diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c index 73c48f5..b0e54a1 100644 --- a/arch/arm/mach-davinci/da830.c +++ b/arch/arm/mach-davinci/da830.c @@ -213,57 +213,22 @@ static struct clk spi1_clk = { .gpsc = 1, }; -static struct clk ecap0_clk = { - .name = "ecap0", +static struct clk ecap_clk = { + .name = "ecap", .parent = &pll0_sysclk2, .lpsc = DA8XX_LPSC1_ECAP, .gpsc = 1, }; -static struct clk ecap1_clk = { - .name = "ecap1", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC1_ECAP, - .gpsc = 1, -}; - -static struct clk ecap2_clk = { - .name = "ecap2", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC1_ECAP, - .gpsc = 1, -}; - -static struct clk pwm0_clk = { - .name = "pwm0", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC1_PWM, - .gpsc = 1, -}; - -static struct clk pwm1_clk = { - .name = "pwm1", +static struct clk pwm_clk = { + .name = "pwm", .parent = &pll0_sysclk2, .lpsc = DA8XX_LPSC1_PWM, .gpsc = 1, }; -static struct clk pwm2_clk = { - .name = "pwm2", - .parent = &pll0_sysclk2, - .lpsc = DA8XX_LPSC1_PWM, - .gpsc = 1, -}; - -static struct clk eqep0_clk = { - .name = "eqep0", - .parent = &pll0_sysclk2, - .lpsc = DA830_LPSC1_EQEP, - .gpsc = 1, -}; - -static struct clk eqep1_clk = { - .name = "eqep1", +static struct clk eqep_clk = { + .name = "eqep", .parent = &pll0_sysclk2, .lpsc = DA830_LPSC1_EQEP, .gpsc = 1, @@ -304,11 +269,6 @@ static struct clk usb20_clk = { .gpsc = 1, }; -static struct clk cppi41_clk = { - .name = "cppi41", - .parent = &usb20_clk, -}; - static struct clk aemif_clk = { .name = "aemif", .parent = &pll0_sysclk3, @@ -434,21 +394,16 @@ static __init void da830_clk_init(void) clk_register_clkdev(clk, NULL, "spi_davinci.0"); clk = davinci_clk_init(&spi1_clk); clk_register_clkdev(clk, NULL, "spi_davinci.1"); - clk = davinci_clk_init(&ecap0_clk); + clk = davinci_clk_init(&ecap_clk); clk_register_clkdev(clk, "ecap0", NULL); - clk = davinci_clk_init(&ecap1_clk); clk_register_clkdev(clk, "ecap1", NULL); - clk = davinci_clk_init(&ecap2_clk); clk_register_clkdev(clk, "ecap2", NULL); - clk = davinci_clk_init(&pwm0_clk); + clk = davinci_clk_init(&pwm_clk); clk_register_clkdev(clk, "pwm0", NULL); - clk = davinci_clk_init(&pwm1_clk); clk_register_clkdev(clk, "pwm1", NULL); - clk = davinci_clk_init(&pwm2_clk); clk_register_clkdev(clk, "pwm2", NULL); - clk = davinci_clk_init(&eqep0_clk); + clk = davinci_clk_init(&eqep_clk); clk_register_clkdev(clk, NULL, "eqep.0"); - clk = davinci_clk_init(&eqep1_clk); clk_register_clkdev(clk, NULL, "eqep.1"); clk = davinci_clk_init(&lcdc_clk); clk_register_clkdev(clk, "fck", "da8xx_lcdc.0"); @@ -460,7 +415,6 @@ static __init void da830_clk_init(void) clk_register_clkdev(clk, NULL, "davinci-mcasp.2"); clk = davinci_clk_init(&usb20_clk); clk_register_clkdev(clk, "usb20", "musb-da8xx"); - clk = davinci_clk_init(&cppi41_clk); clk_register_clkdev(clk, NULL, "cppi41-dmaengine"); clk = davinci_clk_init(&aemif_clk); clk_register_clkdev(clk, "aemif", NULL); @@ -470,7 +424,6 @@ static __init void da830_clk_init(void) clk_register_clkdev(clk, "secu_mgr", NULL); clk = davinci_clk_init(&emac_clk); clk_register_clkdev(clk, NULL, "davinci_emac.1"); - clk = davinci_clk_init(&emac_clk); clk_register_clkdev(clk, "fck", "davinci_mdio.0"); clk = davinci_clk_init(&gpio_clk); clk_register_clkdev(clk, "gpio", NULL); diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index eaa05ac..0975edb 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -319,16 +319,6 @@ static struct clk emac_clk = { .gpsc = 1, }; -/* - * In order to avoid adding the emac_clk to the clock lookup table twice (and - * screwing up the linked list in the process) create a separate clock for - * mdio inheriting the rate from emac_clk. - */ -static struct clk mdio_clk = { - .name = "mdio", - .parent = &emac_clk, -}; - static struct clk mcasp_clk = { .name = "mcasp", .parent = &async3_clk, @@ -377,16 +367,6 @@ static struct clk aemif_clk = { .flags = ALWAYS_ENABLED, }; -/* - * In order to avoid adding the aemif_clk to the clock lookup table twice (and - * screwing up the linked list in the process) create a separate clock for - * nand inheriting the rate from aemif_clk. - */ -static struct clk aemif_nand_clk = { - .name = "nand", - .parent = &aemif_clk, -}; - static struct clk usb11_clk = { .name = "usb11", .parent = &pll0_sysclk4, @@ -401,11 +381,6 @@ static struct clk usb20_clk = { .gpsc = 1, }; -static struct clk cppi41_clk = { - .name = "cppi41", - .parent = &usb20_clk, -}; - static struct clk spi0_clk = { .name = "spi0", .parent = &pll0_sysclk2, @@ -449,16 +424,6 @@ static struct clk ehrpwm_clk = { .gpsc = 1, }; -static struct clk ehrpwm0_clk = { - .name = "ehrpwm0", - .parent = &ehrpwm_clk, -}; - -static struct clk ehrpwm1_clk = { - .name = "ehrpwm1", - .parent = &ehrpwm_clk, -}; - #define DA8XX_EHRPWM_TBCLKSYNC BIT(12) static void ehrpwm_tblck_enable(struct clk *clk) @@ -486,15 +451,6 @@ static struct clk ehrpwm_tbclk = { .clk_disable = ehrpwm_tblck_disable, }; -static struct clk ehrpwm0_tbclk = { - .name = "ehrpwm0_tbclk", - .parent = &ehrpwm_tbclk, -}; - -static struct clk ehrpwm1_tbclk = { - .name = "ehrpwm1_tbclk", - .parent = &ehrpwm_tbclk, -}; static struct clk ecap_clk = { .name = "ecap", @@ -503,21 +459,6 @@ static struct clk ecap_clk = { .gpsc = 1, }; -static struct clk ecap0_clk = { - .name = "ecap0_clk", - .parent = &ecap_clk, -}; - -static struct clk ecap1_clk = { - .name = "ecap1_clk", - .parent = &ecap_clk, -}; - -static struct clk ecap2_clk = { - .name = "ecap2_clk", - .parent = &ecap_clk, -}; - static __init void da850_clk_init(void) { struct clk *clk; @@ -592,7 +533,6 @@ static __init void da850_clk_init(void) clk_register_clkdev(clk, "rmii", NULL); clk = davinci_clk_init(&emac_clk); clk_register_clkdev(clk, NULL, "davinci_emac.1"); - clk = davinci_clk_init(&mdio_clk); clk_register_clkdev(clk, "fck", "davinci_mdio.0"); clk = davinci_clk_init(&mcasp_clk); clk_register_clkdev(clk, NULL, "davinci-mcasp.0"); @@ -608,13 +548,11 @@ static __init void da850_clk_init(void) clk_register_clkdev(clk, NULL, "da830-mmc.1"); clk = davinci_clk_init(&aemif_clk); clk_register_clkdev(clk, NULL, "ti-aemif"); - clk = davinci_clk_init(&aemif_nand_clk); clk_register_clkdev(clk, "aemif", "davinci-nand.0"); clk = davinci_clk_init(&usb11_clk); clk_register_clkdev(clk, "usb11", "ohci-da8xx"); clk = davinci_clk_init(&usb20_clk); clk_register_clkdev(clk, "usb20", "musb-da8xx"); - clk = davinci_clk_init(&cppi41_clk); clk_register_clkdev(clk, NULL, "cppi41-dmaengine"); clk = davinci_clk_init(&spi0_clk); clk_register_clkdev(clk, NULL, "spi_davinci.0"); @@ -627,24 +565,14 @@ static __init void da850_clk_init(void) clk = davinci_clk_init(&dsp_clk); clk_register_clkdev(clk, NULL, "davinci-rproc.0"); clk = davinci_clk_init(&ehrpwm_clk); - clk_register_clkdev(clk, NULL, NULL); - clk = davinci_clk_init(&ehrpwm0_clk); clk_register_clkdev(clk, "fck", "ehrpwm.0"); - clk = davinci_clk_init(&ehrpwm1_clk); clk_register_clkdev(clk, "fck", "ehrpwm.1"); clk = davinci_clk_init(&ehrpwm_tbclk); - clk_register_clkdev(clk, NULL, NULL); - clk = davinci_clk_init(&ehrpwm0_tbclk); clk_register_clkdev(clk, "tbclk", "ehrpwm.0"); - clk = davinci_clk_init(&ehrpwm1_tbclk); clk_register_clkdev(clk, "tbclk", "ehrpwm.1"); clk = davinci_clk_init(&ecap_clk); - clk_register_clkdev(clk, NULL, NULL); - clk = davinci_clk_init(&ecap0_clk); clk_register_clkdev(clk, "fck", "ecap.0"); - clk = davinci_clk_init(&ecap1_clk); clk_register_clkdev(clk, "fck", "ecap.1"); - clk = davinci_clk_init(&ecap2_clk); clk_register_clkdev(clk, "fck", "ecap.2"); } diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 0cf4ab4..430fb1e 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -533,7 +533,6 @@ static __init void dm365_clk_init(void) clk_register_clkdev(clk, "usb", NULL); clk = davinci_clk_init(&emac_clk); clk_register_clkdev(clk, NULL, "davinci_emac.1"); - clk = davinci_clk_init(&emac_clk); clk_register_clkdev(clk, "fck", "davinci_mdio.0"); clk = davinci_clk_init(&voicecodec_clk); clk_register_clkdev(clk, NULL, "davinci_voicecodec"); diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 769ce29..58120f4 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -323,8 +323,6 @@ static __init void dm644x_clk_init(void) clk_register_clkdev(clk, "master", "vpss"); clk = davinci_clk_init(&vpss_slave_clk); clk_register_clkdev(clk, "slave", "vpss"); - clk = davinci_clk_init(&arm_clk); - clk_register_clkdev(clk, "arm", NULL); clk = davinci_clk_init(&uart0_clk); clk_register_clkdev(clk, NULL, "serial8250.0"); clk = davinci_clk_init(&uart1_clk); @@ -333,7 +331,6 @@ static __init void dm644x_clk_init(void) clk_register_clkdev(clk, NULL, "serial8250.2"); clk = davinci_clk_init(&emac_clk); clk_register_clkdev(clk, NULL, "davinci_emac.1"); - clk = davinci_clk_init(&emac_clk); clk_register_clkdev(clk, "fck", "davinci_mdio.0"); clk = davinci_clk_init(&i2c_clk); clk_register_clkdev(clk, NULL, "i2c_davinci.1"); diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index d75b4bc09..0cd5d51 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -386,7 +386,6 @@ static __init void dm646x_clk_init(void) clk_register_clkdev(clk, "aemif", NULL); clk = davinci_clk_init(&emac_clk); clk_register_clkdev(clk, NULL, "davinci_emac.1"); - clk = davinci_clk_init(&emac_clk); clk_register_clkdev(clk, "fck", "davinci_mdio.0"); clk = davinci_clk_init(&pwm0_clk); clk_register_clkdev(clk, "pwm0", NULL); -- 2.7.4 ^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v4 3/7] ARM: davinci: fix duplicate clocks 2017-12-31 23:39 ` [PATCH v4 3/7] ARM: davinci: fix duplicate clocks David Lechner @ 2018-01-04 11:12 ` Sekhar Nori 2018-01-04 17:44 ` David Lechner 0 siblings, 1 reply; 29+ messages in thread From: Sekhar Nori @ 2018-01-04 11:12 UTC (permalink / raw) To: linux-arm-kernel On Monday 01 January 2018 05:09 AM, David Lechner wrote: > There are a number of clocks that were duplicated because they are used by > more than one device. It is no longer necessary to do this since we are > explicitly calling clk_register_clkdev() for each clock. In da830.c, some > clocks were using the same LPSC, which would cause problems with reference > counting, so these are combinded into one clock each. In da850.c the > duplicate clocks had already been fixed by creating dummy child clocks, so > these clocks are removed. > > Signed-off-by: David Lechner <david@lechnology.com> If we do end up keeping 2/7, this should be done before that - to avoid retouching code that was just introduced. Thanks, Sekhar ^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v4 3/7] ARM: davinci: fix duplicate clocks 2018-01-04 11:12 ` Sekhar Nori @ 2018-01-04 17:44 ` David Lechner 0 siblings, 0 replies; 29+ messages in thread From: David Lechner @ 2018-01-04 17:44 UTC (permalink / raw) To: linux-arm-kernel On 1/4/18 5:12 AM, Sekhar Nori wrote: > On Monday 01 January 2018 05:09 AM, David Lechner wrote: >> There are a number of clocks that were duplicated because they are used by >> more than one device. It is no longer necessary to do this since we are >> explicitly calling clk_register_clkdev() for each clock. In da830.c, some >> clocks were using the same LPSC, which would cause problems with reference >> counting, so these are combinded into one clock each. In da850.c the >> duplicate clocks had already been fixed by creating dummy child clocks, so >> these clocks are removed. >> >> Signed-off-by: David Lechner <david@lechnology.com> > > If we do end up keeping 2/7, this should be done before that - to avoid > retouching code that was just introduced. > FWIW, this can't be done before because it will cause broken linked lists in the davinci clocks. But, as I mentioned already, I am going to try a different approach, so this patch will go away completely. ^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v4 4/7] ARM: davinci: remove davinci_set_refclk_rate() 2017-12-31 23:39 [PATCH v4 0/7] ARM: davinci: convert to common clock framework David Lechner ` (2 preceding siblings ...) 2017-12-31 23:39 ` [PATCH v4 3/7] ARM: davinci: fix duplicate clocks David Lechner @ 2017-12-31 23:39 ` David Lechner 2017-12-31 23:39 ` [PATCH v4 5/7] clk: Introduce davinci clocks David Lechner ` (3 subsequent siblings) 7 siblings, 0 replies; 29+ messages in thread From: David Lechner @ 2017-12-31 23:39 UTC (permalink / raw) To: linux-arm-kernel This removes the davinci_set_refclk_rate() function. This was used to set the ref_clk rate after all clocks had been registered when clocks were registered from a static table. However, now it is possible to modify the rate before registering the clocks in the first place by passing the rate as a function parameter. The aux_clkin rate is also passed as a parameter since technically it is also board-specific. Signed-off-by: David Lechner <david@lechnology.com> --- arch/arm/mach-davinci/board-dm646x-evm.c | 12 +++++++----- arch/arm/mach-davinci/clock.c | 32 -------------------------------- arch/arm/mach-davinci/clock.h | 1 - arch/arm/mach-davinci/davinci.h | 2 +- arch/arm/mach-davinci/dm646x.c | 18 +++++++----------- 5 files changed, 15 insertions(+), 50 deletions(-) diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index dafc852..c8f517b 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c @@ -716,17 +716,19 @@ static void __init evm_init_i2c(void) } #endif -#define DM6467T_EVM_REF_FREQ 33000000 - static void __init davinci_map_io(void) { dm646x_init(); } +static void __init dm6467_evm_init_time(void) +{ + dm646x_init_time(27000000, 24000000); +} + static void __init dm6467t_evm_init_time(void) { - dm646x_init_time(); - davinci_set_refclk_rate(DM6467T_EVM_REF_FREQ); + dm646x_init_time(33000000, 24000000); } #define DM646X_EVM_PHY_ID "davinci_mdio-0:01" @@ -800,7 +802,7 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM") .atag_offset = 0x100, .map_io = davinci_map_io, .init_irq = davinci_irq_init, - .init_time = dm646x_init_time, + .init_time = dm6467_evm_init_time, .init_machine = evm_init, .init_late = davinci_init_late, .dma_zone_size = SZ_128M, diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index f82a90c..52b95e2 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -575,38 +575,6 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, } EXPORT_SYMBOL(davinci_set_pllrate); -/** - * davinci_set_refclk_rate() - Set the reference clock rate - * @rate: The new rate. - * - * Sets the reference clock rate to a given value. This will most likely - * result in the entire clock tree getting updated. - * - * This is used to support boards which use a reference clock different - * than that used by default in <soc>.c file. The reference clock rate - * should be updated early in the boot process; ideally soon after the - * clock tree has been initialized once with the default reference clock - * rate (davinci_clk_init()). - * - * Returns 0 on success, error otherwise. - */ -int davinci_set_refclk_rate(unsigned long rate) -{ - struct clk *refclk; - - refclk = clk_get(NULL, "ref"); - if (IS_ERR(refclk)) { - pr_err("%s: failed to get reference clock\n", __func__); - return PTR_ERR(refclk); - } - - clk_set_rate(refclk, rate); - - clk_put(refclk); - - return 0; -} - struct clk * __init davinci_clk_init(struct clk *clk) { if (!clk->recalc) { diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index 66c40a2..61fcdaa 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -122,7 +122,6 @@ struct clk *davinci_clk_init(struct clk *clk); int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, unsigned int mult, unsigned int postdiv); int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate); -int davinci_set_refclk_rate(unsigned long rate); int davinci_simple_set_rate(struct clk *clk, unsigned long rate); int davinci_clk_reset(struct clk *clk, bool reset); void davinci_clk_enable(struct clk *clk); diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h index d70f4d9..270cef8 100644 --- a/arch/arm/mach-davinci/davinci.h +++ b/arch/arm/mach-davinci/davinci.h @@ -111,7 +111,7 @@ int dm644x_gpio_register(void); /* DM646x function declarations */ void dm646x_init(void); -void dm646x_init_time(void); +void dm646x_init_time(unsigned long ref_clk_rate, unsigned long aux_clkin_rate); void dm646x_init_mcasp0(struct snd_platform_data *pdata); void dm646x_init_mcasp1(struct snd_platform_data *pdata); int dm646x_init_edma(struct edma_rsv_info *rsv); diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index 0cd5d51..31dbe93 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -39,12 +39,6 @@ #define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\ BIT_MASK(8)) -/* - * Device specific clocks - */ -#define DM646X_REF_FREQ 27000000 -#define DM646X_AUX_FREQ 24000000 - #define DM646X_EMAC_BASE 0x01c80000 #define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000) #define DM646X_EMAC_CNTRL_OFFSET 0x0000 @@ -64,13 +58,11 @@ static struct pll_data pll2_data = { static struct clk ref_clk = { .name = "ref_clk", - .rate = DM646X_REF_FREQ, .set_rate = davinci_simple_set_rate, }; static struct clk aux_clkin = { .name = "aux_clkin", - .rate = DM646X_AUX_FREQ, }; static struct clk pll1_clk = { @@ -320,10 +312,13 @@ static struct clk vpif1_clk = { .flags = ALWAYS_ENABLED, }; -static __init void dm646x_clk_init(void) +static __init void dm646x_clk_init(unsigned long ref_clk_rate, + unsigned long aux_clkin_rate) { struct clk *clk; + ref_clk.rate = ref_clk_rate; + aux_clkin.rate = aux_clkin_rate; clk = davinci_clk_init(&ref_clk); clk_register_clkdev(clk, "ref", NULL); clk = davinci_clk_init(&aux_clkin); @@ -998,9 +993,10 @@ void __init dm646x_init(void) davinci_map_sysmod(); } -void __init dm646x_init_time(void) +void __init dm646x_init_time(unsigned long ref_clk_rate, + unsigned long aux_clkin_rate) { - dm646x_clk_init(); + dm646x_clk_init(ref_clk_rate, aux_clkin_rate); davinci_timer_init(); } -- 2.7.4 ^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v4 5/7] clk: Introduce davinci clocks 2017-12-31 23:39 [PATCH v4 0/7] ARM: davinci: convert to common clock framework David Lechner ` (3 preceding siblings ...) 2017-12-31 23:39 ` [PATCH v4 4/7] ARM: davinci: remove davinci_set_refclk_rate() David Lechner @ 2017-12-31 23:39 ` David Lechner 2018-01-01 0:23 ` David Lechner ` (2 more replies) 2017-12-31 23:39 ` [PATCH v4 7/7] ARM: davinci_all_defconfig: remove CONFIG_DAVINCI_RESET_CLOCKS David Lechner ` (2 subsequent siblings) 7 siblings, 3 replies; 29+ messages in thread From: David Lechner @ 2017-12-31 23:39 UTC (permalink / raw) To: linux-arm-kernel This introduces new drivers for arch/arm/mach-davinci. The code is based on the clock drivers from there and adapted to use the common clock framework. Signed-off-by: David Lechner <david@lechnology.com> --- drivers/clk/Makefile | 1 + drivers/clk/davinci/Makefile | 3 + drivers/clk/davinci/da8xx-cfgchip-clk.c | 380 ++++++++++++++++++++++++++++++ drivers/clk/davinci/pll.c | 333 ++++++++++++++++++++++++++ drivers/clk/davinci/psc.c | 217 +++++++++++++++++ include/linux/clk/davinci.h | 46 ++++ include/linux/platform_data/davinci_clk.h | 25 ++ 7 files changed, 1005 insertions(+) create mode 100644 drivers/clk/davinci/Makefile create mode 100644 drivers/clk/davinci/da8xx-cfgchip-clk.c create mode 100644 drivers/clk/davinci/pll.c create mode 100644 drivers/clk/davinci/psc.c create mode 100644 include/linux/clk/davinci.h create mode 100644 include/linux/platform_data/davinci_clk.h diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index f7f761b..c865fd0 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -60,6 +60,7 @@ obj-$(CONFIG_ARCH_ARTPEC) += axis/ obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/ obj-y += bcm/ obj-$(CONFIG_ARCH_BERLIN) += berlin/ +obj-$(CONFIG_ARCH_DAVINCI) += davinci/ obj-$(CONFIG_H8300) += h8300/ obj-$(CONFIG_ARCH_HISI) += hisilicon/ obj-y += imgtec/ diff --git a/drivers/clk/davinci/Makefile b/drivers/clk/davinci/Makefile new file mode 100644 index 0000000..5efbdcd --- /dev/null +++ b/drivers/clk/davinci/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_PHY_DA8XX_USB) += da8xx-cfgchip-clk.o +obj-y += pll.o +obj-y += psc.o \ No newline at end of file diff --git a/drivers/clk/davinci/da8xx-cfgchip-clk.c b/drivers/clk/davinci/da8xx-cfgchip-clk.c new file mode 100644 index 0000000..780bb25 --- /dev/null +++ b/drivers/clk/davinci/da8xx-cfgchip-clk.c @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * da8xx-cfgchip-clk - TI DaVinci DA8xx CFGCHIP clocks driver + * + * Copyright (C) 2017 David Lechner <david@lechnology.com> + * + * This driver exposes the USB PHY clocks on DA8xx/AM18xx/OMAP-L13x SoCs. + * The clocks consist of two muxes and a PLL. The USB 2.0 PHY mux and PLL are + * combined into a single clock in Linux. The USB 1.0 PHY clock just consists + * of a mux. These clocks are controlled through CFGCHIP2, which is accessed + * as a syscon regmap since it is shared with other devices. + */ + +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <linux/clk-provider.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/mfd/da8xx-cfgchip.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/platform_data/davinci_clk.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +/** + * da8xx_cfgchip_clk + * @usb0_hw: The USB 2.0 PHY clock (mux + PLL) + * @usb1_hw: The USB 1.1 PHY clock (mux) + * @usb0_clk: The USB 2.0 subsystem PSC clock + * @regmap: The CFGCHIP syscon regmap + */ +struct da8xx_cfgchip_clk { + struct clk_hw usb0_hw; + struct clk_hw usb1_hw; + struct clk *usb0_clk; + struct regmap *regmap; +}; + +/* The USB 2.0 PHY can use either USB_REFCLKIN or AUXCLK */ +enum usb0_phy_clk_parent { + USB20_PHY_CLK_PARENT_USB_REFCLKIN, + USB20_PHY_CLK_PARENT_PLL0_AUX, +}; + +/* The USB 1.1 PHY can use either the PLL output from the USB 2.0 PHY or + * USB_REFCLKIN + */ +enum usb1_phy_clk_parent { + USB1_PHY_CLK_PARENT_USB_REFCLKIN, + USB1_PHY_CLK_PARENT_USB0_PHY_PLL, +}; + +/* --- USB 2.0 PHY clock --- */ + +static int usb0_phy_clk_prepare(struct clk_hw *hw) +{ + struct da8xx_cfgchip_clk *clk = + container_of(hw, struct da8xx_cfgchip_clk, usb0_hw); + + /* The USB 2.0 PSC clock is only needed temporarily during the USB 2.0 + * PHY clock enable, but since clk_prepare() can't be called in an + * atomic context (i.e. in clk_enable()), we have to prepare it here. + */ + return clk_prepare(clk->usb0_clk); +} + +static void usb0_phy_clk_unprepare(struct clk_hw *hw) +{ + struct da8xx_cfgchip_clk *clk = + container_of(hw, struct da8xx_cfgchip_clk, usb0_hw); + + clk_unprepare(clk->usb0_clk); +} + +static int usb0_phy_clk_enable(struct clk_hw *hw) +{ + struct da8xx_cfgchip_clk *clk = + container_of(hw, struct da8xx_cfgchip_clk, usb0_hw); + unsigned int mask, val; + int ret; + + /* Locking the USB 2.O PLL requires that the USB 2.O PSC is enabled + * temporaily. It can be turned back off once the PLL is locked. + */ + clk_enable(clk->usb0_clk); + + /* Turn on the USB 2.0 PHY, but just the PLL, and not OTG. The USB 1.1 + * PHY may use the USB 2.0 PLL clock without USB 2.0 OTG being used. + */ + mask = CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_PHY_PLLON; + val = CFGCHIP2_PHY_PLLON; + + regmap_write_bits(clk->regmap, CFGCHIP(2), mask, val); + ret = regmap_read_poll_timeout(clk->regmap, CFGCHIP(2), val, + val & CFGCHIP2_PHYCLKGD, 0, 500000); + + clk_disable(clk->usb0_clk); + + return ret; +} + +static void usb0_phy_clk_disable(struct clk_hw *hw) +{ + struct da8xx_cfgchip_clk *clk = + container_of(hw, struct da8xx_cfgchip_clk, usb0_hw); + unsigned int val; + + val = CFGCHIP2_PHYPWRDN; + regmap_write_bits(clk->regmap, CFGCHIP(2), val, val); +} + +static unsigned long usb0_phy_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct da8xx_cfgchip_clk *clk = + container_of(hw, struct da8xx_cfgchip_clk, usb0_hw); + unsigned int mask, val; + + /* The parent clock rate must be one of the following */ + mask = CFGCHIP2_REFFREQ_MASK; + switch (parent_rate) { + case 12000000: + val = CFGCHIP2_REFFREQ_12MHZ; + break; + case 13000000: + val = CFGCHIP2_REFFREQ_13MHZ; + break; + case 19200000: + val = CFGCHIP2_REFFREQ_19_2MHZ; + break; + case 20000000: + val = CFGCHIP2_REFFREQ_20MHZ; + break; + case 24000000: + val = CFGCHIP2_REFFREQ_24MHZ; + break; + case 26000000: + val = CFGCHIP2_REFFREQ_26MHZ; + break; + case 38400000: + val = CFGCHIP2_REFFREQ_38_4MHZ; + break; + case 40000000: + val = CFGCHIP2_REFFREQ_40MHZ; + break; + case 48000000: + val = CFGCHIP2_REFFREQ_48MHZ; + break; + default: + return 0; + } + + regmap_write_bits(clk->regmap, CFGCHIP(2), mask, val); + + /* USB 2.0 PLL always supplies 48MHz */ + return 48000000; +} + +static long usb0_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + return 48000000; +} + +static int usb0_phy_clk_set_parent(struct clk_hw *hw, u8 index) +{ + struct da8xx_cfgchip_clk *clk = + container_of(hw, struct da8xx_cfgchip_clk, usb0_hw); + unsigned int mask, val; + + /* Set the mux depending on the parent clock. */ + mask = CFGCHIP2_USB2PHYCLKMUX; + switch (index) { + case USB20_PHY_CLK_PARENT_USB_REFCLKIN: + val = 0; + break; + case USB20_PHY_CLK_PARENT_PLL0_AUX: + val = CFGCHIP2_USB2PHYCLKMUX; + break; + default: + return -EINVAL; + } + + regmap_write_bits(clk->regmap, CFGCHIP(2), mask, val); + + return 0; +} + +static u8 usb0_phy_clk_get_parent(struct clk_hw *hw) +{ + struct da8xx_cfgchip_clk *clk = + container_of(hw, struct da8xx_cfgchip_clk, usb0_hw); + unsigned int val; + + regmap_read(clk->regmap, CFGCHIP(2), &val); + + if (val & CFGCHIP2_USB2PHYCLKMUX) + return USB20_PHY_CLK_PARENT_PLL0_AUX; + + return USB20_PHY_CLK_PARENT_USB_REFCLKIN; +} + +static const struct clk_ops usb0_phy_clk_ops = { + .prepare = usb0_phy_clk_prepare, + .unprepare = usb0_phy_clk_unprepare, + .enable = usb0_phy_clk_enable, + .disable = usb0_phy_clk_disable, + .recalc_rate = usb0_phy_clk_recalc_rate, + .round_rate = usb0_phy_clk_round_rate, + .set_parent = usb0_phy_clk_set_parent, + .get_parent = usb0_phy_clk_get_parent, +}; + +static const char * const usb0_phy_clk_parent_names[] = { + [USB20_PHY_CLK_PARENT_USB_REFCLKIN] = "usb_refclkin", + [USB20_PHY_CLK_PARENT_PLL0_AUX] = "pll0_aux_clk", +}; + +static const struct clk_init_data usb0_phy_clk_init_data = { + .name = "usb0_phy_clk", + .ops = &usb0_phy_clk_ops, + .parent_names = usb0_phy_clk_parent_names, + .num_parents = ARRAY_SIZE(usb0_phy_clk_parent_names), +}; + +/* --- USB 1.1 PHY clock --- */ + +static int usb1_phy_clk_set_parent(struct clk_hw *hw, u8 index) +{ + struct da8xx_cfgchip_clk *clk = + container_of(hw, struct da8xx_cfgchip_clk, usb1_hw); + unsigned int mask, val; + + /* Set the USB 1.1 PHY clock mux based on the parent clock. */ + mask = CFGCHIP2_USB1PHYCLKMUX; + switch (index) { + case USB1_PHY_CLK_PARENT_USB_REFCLKIN: + val = CFGCHIP2_USB1PHYCLKMUX; + break; + case USB1_PHY_CLK_PARENT_USB0_PHY_PLL: + val = 0; + break; + default: + return -EINVAL; + } + + regmap_write_bits(clk->regmap, CFGCHIP(2), mask, val); + + return 0; +} + +static u8 usb1_phy_clk_get_parent(struct clk_hw *hw) +{ + struct da8xx_cfgchip_clk *clk = + container_of(hw, struct da8xx_cfgchip_clk, usb1_hw); + unsigned int val; + + regmap_read(clk->regmap, CFGCHIP(2), &val); + + if (val & CFGCHIP2_USB1PHYCLKMUX) + return USB1_PHY_CLK_PARENT_USB_REFCLKIN; + + return USB1_PHY_CLK_PARENT_USB0_PHY_PLL; +} + +static const struct clk_ops usb1_phy_clk_ops = { + .set_parent = usb1_phy_clk_set_parent, + .get_parent = usb1_phy_clk_get_parent, +}; + +static const char * const usb1_phy_clk_parent_names[] = { + [USB1_PHY_CLK_PARENT_USB_REFCLKIN] = "usb_refclkin", + [USB1_PHY_CLK_PARENT_USB0_PHY_PLL] = "usb0_phy_clk", +}; + +static struct clk_init_data usb1_phy_clk_init_data = { + .name = "usb1_phy_clk", + .ops = &usb1_phy_clk_ops, + .parent_names = usb1_phy_clk_parent_names, + .num_parents = ARRAY_SIZE(usb1_phy_clk_parent_names), +}; + +/* --- platform driver --- */ + +static int da8xx_cfgchip_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct da8xx_cfgchip_clk_data *pdata = dev->platform_data; + struct da8xx_cfgchip_clk *phy_clk; + const char *parent_name; + struct clk *parent; + int ret; + + if (!pdata) + return -EINVAL; + + phy_clk = devm_kzalloc(dev, sizeof(*phy_clk), GFP_KERNEL); + if (!phy_clk) + return -ENOMEM; + + platform_set_drvdata(pdev, phy_clk); + + phy_clk->regmap = syscon_regmap_lookup_by_pdevname("syscon"); + if (IS_ERR(phy_clk->regmap)) { + dev_err(dev, "Failed to get syscon\n"); + return PTR_ERR(phy_clk->regmap); + } + + /* USB 2.0 subsystem PSC clock - needed to lock PLL */ + phy_clk->usb0_clk = clk_get(dev, "usb20"); + if (IS_ERR(phy_clk->usb0_clk)) { + dev_err(dev, "Failed to get usb20 clock\n"); + return PTR_ERR(phy_clk->usb0_clk); + } + + phy_clk->usb0_hw.init = &usb0_phy_clk_init_data; + ret = devm_clk_hw_register(dev, &phy_clk->usb0_hw); + if (ret) { + dev_err(dev, "Failed to register usb0_phy_clk\n"); + return ret; + } + + phy_clk->usb1_hw.init = &usb1_phy_clk_init_data; + ret = devm_clk_hw_register(dev, &phy_clk->usb1_hw); + if (ret) { + dev_err(dev, "Failed to register usb1_phy_clk\n"); + return ret; + } + + parent_name = pdata->usb0_use_refclkin ? "usb_refclkin" : "pll0_aux"; + parent = devm_clk_get(dev, parent_name); + if (IS_ERR(parent)) { + dev_err(dev, "Failed to get usb0 parent clock %s\n", + parent_name); + return PTR_ERR(parent); + } + + ret = clk_set_parent(phy_clk->usb0_hw.clk, parent); + if (ret) { + dev_err(dev, "Failed to set usb0 parent clock to %s\n", + parent_name); + return ret; + } + + clk_hw_register_clkdev(&phy_clk->usb0_hw, NULL, "da8xx-cfgchip-clk"); + + parent_name = pdata->usb1_use_refclkin ? "usb_refclkin" : "usb0_phy_clk"; + parent = devm_clk_get(dev, parent_name); + if (IS_ERR(parent)) { + dev_err(dev, "Failed to get usb1 parent clock %s\n", + parent_name); + return PTR_ERR(parent); + } + + ret = clk_set_parent(phy_clk->usb1_hw.clk, parent); + if (ret) { + dev_err(dev, "Failed to set usb1 parent clock to %s\n", + parent_name); + return ret; + } + + clk_hw_register_clkdev(&phy_clk->usb0_hw, "usb20_phy", "da8xx-usb-phy"); + clk_hw_register_clkdev(&phy_clk->usb1_hw, "usb11_phy", "da8xx-usb-phy"); + + return 0; +} + +static struct platform_driver da8xx_cfgchip_clk_driver = { + .probe = da8xx_cfgchip_clk_probe, + .driver = { + .name = "da8xx-cfgchip-clk", + }, +}; +module_platform_driver(da8xx_cfgchip_clk_driver); + +MODULE_ALIAS("platform:da8xx-cfgchip-clk"); +MODULE_AUTHOR("David Lechner <david@lechnology.com>"); +MODULE_DESCRIPTION("TI DA8xx CFGCHIP clock driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/davinci/pll.c b/drivers/clk/davinci/pll.c new file mode 100644 index 0000000..035cd91 --- /dev/null +++ b/drivers/clk/davinci/pll.c @@ -0,0 +1,333 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PLL clock driver for Davinci devices + * + * Copyright (C) 2017 David Lechner <david@lechnology.com> + * + * Based on drivers/clk/keystone/pll.c + * Copyright (C) 2013 Texas Instruments Inc. + * Murali Karicheri <m-karicheri2@ti.com> + * Santosh Shilimkar <santosh.shilimkar@ti.com> + */ + +#include <linux/clk-provider.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/slab.h> + +#define REVID 0x000 +#define PLLCTL 0x100 +#define OCSEL 0x104 +#define PLLSECCTL 0x108 +#define PLLM 0x110 +#define PREDIV 0x114 +#define PLLDIV1 0x118 +#define PLLDIV2 0x11c +#define PLLDIV3 0x120 +#define OSCDIV 0x124 +#define POSTDIV 0x128 +#define BPDIV 0x12c +#define PLLCMD 0x138 +#define PLLSTAT 0x13c +#define ALNCTL 0x140 +#define DCHANGE 0x144 +#define CKEN 0x148 +#define CKSTAT 0x14c +#define SYSTAT 0x150 +#define PLLDIV4 0x160 +#define PLLDIV5 0x164 +#define PLLDIV6 0x168 +#define PLLDIV7 0x16c +#define PLLDIV8 0x170 +#define PLLDIV9 0x174 + +#define PLLM_MASK 0x1f +#define PREDIV_RATIO_MASK 0x1f +#define PLLDIV_RATIO_WIDTH 5 +#define PLLDIV_ENABLE_SHIFT 15 +#define OSCDIV_RATIO_WIDTH 5 +#define POSTDIV_RATIO_MASK 0x1f +#define BPDIV_RATIO_SHIFT 0 +#define BPDIV_RATIO_WIDTH 5 +#define CKEN_OBSCLK_SHIFT 1 +#define CKEN_AUXEN_SHIFT 0 + +/** + * struct davinci_pll_clk - Main PLL clock + * @hw: clk_hw for the pll + * @base: Base memory address + * @parent_rate: Saved parent rate used by some child clocks + */ +struct davinci_pll_clk { + struct clk_hw hw; + void __iomem *base; +}; + +#define to_davinci_pll_clk(_hw) container_of((_hw), struct davinci_pll_clk, hw) + +static unsigned long davinci_pll_clk_recalc(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); + unsigned long rate = parent_rate; + u32 prediv, mult, postdiv; + + prediv = readl(pll->base + PREDIV) & PREDIV_RATIO_MASK; + mult = readl(pll->base + PLLM) & PLLM_MASK; + postdiv = readl(pll->base + POSTDIV) & POSTDIV_RATIO_MASK; + + rate /= prediv + 1; + rate *= mult + 1; + rate /= postdiv + 1; + + return rate; +} + +#ifdef CONFIG_DEBUG_FS +#include <linux/debugfs.h> + +#define DEBUG_REG(n) \ +{ \ + .name = #n, \ + .offset = n, \ +} + +static const struct debugfs_reg32 davinci_pll_regs[] = { + DEBUG_REG(REVID), + DEBUG_REG(PLLCTL), + DEBUG_REG(OCSEL), + DEBUG_REG(PLLSECCTL), + DEBUG_REG(PLLM), + DEBUG_REG(PREDIV), + DEBUG_REG(PLLDIV1), + DEBUG_REG(PLLDIV2), + DEBUG_REG(PLLDIV3), + DEBUG_REG(OSCDIV), + DEBUG_REG(POSTDIV), + DEBUG_REG(BPDIV), + DEBUG_REG(PLLCMD), + DEBUG_REG(PLLSTAT), + DEBUG_REG(ALNCTL), + DEBUG_REG(DCHANGE), + DEBUG_REG(CKEN), + DEBUG_REG(CKSTAT), + DEBUG_REG(SYSTAT), + DEBUG_REG(PLLDIV4), + DEBUG_REG(PLLDIV5), + DEBUG_REG(PLLDIV6), + DEBUG_REG(PLLDIV7), + DEBUG_REG(PLLDIV8), + DEBUG_REG(PLLDIV9), +}; + +static int davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry) +{ + struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); + struct debugfs_regset32 *regset; + struct dentry *d; + + regset = kzalloc(sizeof(regset), GFP_KERNEL); + if (!regset) + return -ENOMEM; + + regset->regs = davinci_pll_regs; + regset->nregs = ARRAY_SIZE(davinci_pll_regs); + regset->base = pll->base; + + d = debugfs_create_regset32("registers", 0400, dentry, regset); + if (IS_ERR(d)) { + kfree(regset); + return PTR_ERR(d); + } + + return 0; +} +#else +#define davinci_pll_debug_init NULL +#endif + +static const struct clk_ops davinci_pll_clk_ops = { + .recalc_rate = davinci_pll_clk_recalc, + .debug_init = davinci_pll_debug_init, +}; + +/** + * davinci_pll_clk_register - Register a PLL clock + * @name: The clock name + * @parent_name: The parent clock name + * @base: The PLL's memory region + */ +struct clk *davinci_pll_clk_register(const char *name, + const char *parent_name, + void __iomem *base) +{ + struct clk_init_data init; + struct davinci_pll_clk *pll; + struct clk *clk; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &davinci_pll_clk_ops; + init.parent_names = (parent_name ? &parent_name : NULL); + init.num_parents = (parent_name ? 1 : 0); + + pll->base = base; + pll->hw.init = &init; + + clk = clk_register(NULL, &pll->hw); + if (IS_ERR(clk)) + kfree(pll); + + return clk; +} + +struct davinci_pll_aux_clk { + struct clk_hw hw; + struct davinci_pll_clk *pll; +}; + +/** + * davinci_pll_aux_clk_register - Register bypass clock (AUXCLK) + * @name: The clock name + * @parent_name: The parent clock name (usually "ref_clk" since this bypasses + * the PLL) + * @base: The PLL memory region + */ +struct clk *davinci_pll_aux_clk_register(const char *name, + const char *parent_name, + void __iomem *base) +{ + return clk_register_gate(NULL, name, parent_name, 0, base + CKEN, + CKEN_AUXEN_SHIFT, 0, NULL); +} + +/** + * davinci_pll_bpdiv_clk_register - Register bypass divider clock (SYSCLKBP) + * @name: The clock name + * @parent_name: The parent clock name (usually "ref_clk" since this bypasses + * the PLL) + * @base: The PLL memory region + */ +struct clk *davinci_pll_bpdiv_clk_register(const char *name, + const char *parent_name, + void __iomem *base) +{ + return clk_register_divider(NULL, name, parent_name, 0, base + BPDIV, + BPDIV_RATIO_SHIFT, BPDIV_RATIO_WIDTH, + CLK_DIVIDER_READ_ONLY, NULL); +} + +/** + * davinci_pll_obs_clk_register - Register oscillator divider clock (OBSCLK) + * @name: The clock name + * @parent_names: The parent clock names + * @num_parents: The number of paren clocks + * @base: The PLL memory region + * @table: A table of values cooresponding to the parent clocks (see OCSEL + * register in SRM for values) + */ +struct clk *davinci_pll_obs_clk_register(const char *name, + const char * const *parent_names, + u8 num_parents, + void __iomem *base, + u32 *table) +{ + struct clk_mux *mux; + struct clk_gate *gate; + struct clk_divider *divider; + struct clk *clk; + + mux = kzalloc(sizeof(*mux), GFP_KERNEL); + if (!mux) + return ERR_PTR(-ENOMEM); + + mux->reg = base + OCSEL; + mux->table = table; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) { + kfree(mux); + return ERR_PTR(-ENOMEM); + } + + gate->reg = base + CKEN; + gate->bit_idx = CKEN_OBSCLK_SHIFT; + + divider = kzalloc(sizeof(*divider), GFP_KERNEL); + if (!divider) { + kfree(gate); + kfree(mux); + return ERR_PTR(-ENOMEM); + } + + divider->reg = base + OSCDIV; + divider->width = OSCDIV_RATIO_WIDTH; + + clk = clk_register_composite(NULL, name, parent_names, num_parents, + &mux->hw, &clk_mux_ops, + ÷r->hw, &clk_divider_ops, + &gate->hw, &clk_gate_ops, 0); + if (IS_ERR(clk)) { + kfree(divider); + kfree(gate); + kfree(mux); + } + + return clk; +} + +/** + * davinci_pll_div_clk_register - Register a PLLDIV (SYSCLK) clock + * @name: The clock name + * @parent_name: The parent clock name + * @base: The PLL memory region + * @id: The id of the divider (n in PLLDIVn) + */ +struct clk *davinci_pll_div_clk_register(const char *name, + const char *parent_name, + void __iomem *base, + u32 id) +{ + const char * const *parent_names = (parent_name ? &parent_name : NULL); + int num_parents = (parent_name ? 1 : 0); + struct clk_gate *gate; + struct clk_divider *divider; + struct clk *clk; + u32 reg; + + /* PLLDIVn registers are not entirely consecutive */ + if (id < 4) + reg = PLLDIV1 + 4 * (id - 1); + else + reg = PLLDIV4 + 4 * (id - 4); + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + gate->reg = base + reg; + gate->bit_idx = PLLDIV_ENABLE_SHIFT; + + divider = kzalloc(sizeof(*divider), GFP_KERNEL); + if (!divider) { + kfree(gate); + return ERR_PTR(-ENOMEM); + } + + divider->reg = base + reg; + divider->width = PLLDIV_RATIO_WIDTH; + divider->flags = CLK_DIVIDER_READ_ONLY; + + clk = clk_register_composite(NULL, name, parent_names, num_parents, + NULL, NULL, ÷r->hw, &clk_divider_ops, + &gate->hw, &clk_gate_ops, 0); + if (IS_ERR(clk)) { + kfree(divider); + kfree(gate); + } + + return clk; +} diff --git a/drivers/clk/davinci/psc.c b/drivers/clk/davinci/psc.c new file mode 100644 index 0000000..8ae85ee --- /dev/null +++ b/drivers/clk/davinci/psc.c @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Clock driver for DA8xx/AM17xx/AM18xx/OMAP-L13x PSC controllers + * + * Copyright (C) 2017 David Lechner <david@lechnology.com> + * + * Based on: drivers/clk/keystone/gate.c + * Copyright (C) 2013 Texas Instruments. + * Murali Karicheri <m-karicheri2@ti.com> + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * And: arch/arm/mach-davinci/psc.c + * Copyright (C) 2006 Texas Instruments. + */ + +#include <linux/clk-provider.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/slab.h> + +/* PSC register offsets */ +#define EPCPR 0x070 +#define PTCMD 0x120 +#define PTSTAT 0x128 +#define PDSTAT 0x200 +#define PDCTL 0x300 +#define MDSTAT 0x800 +#define MDCTL 0xa00 + +/* PSC module states */ +enum davinci_psc_state { + PSC_STATE_SWRSTDISABLE = 0, + PSC_STATE_SYNCRST = 1, + PSC_STATE_DISABLE = 2, + PSC_STATE_ENABLE = 3, +}; + +#define MDSTAT_STATE_MASK 0x3f +#define MDSTAT_MCKOUT BIT(12) +#define PDSTAT_STATE_MASK 0x1f +#define MDCTL_FORCE BIT(31) +#define MDCTL_LRESET BIT(8) +#define PDCTL_EPCGOOD BIT(8) +#define PDCTL_NEXT BIT(0) + +/** + * struct davinci_psc_clk - PSC clock structure + * @hw: clk_hw for the psc + * @psc_data: PSC driver specific data + * @lpsc: Local PSC number (module id) + * @pd: Power domain + */ +struct davinci_psc_clk { + struct clk_hw hw; + void __iomem *base; + u32 lpsc; + u32 pd; +}; + +#define to_davinci_psc_clk(_hw) container_of(_hw, struct davinci_psc_clk, hw) + +static void psc_config(struct davinci_psc_clk *psc, + enum davinci_psc_state next_state) +{ + u32 epcpr, ptcmd, pdstat, pdctl, mdstat, mdctl, ptstat; + + mdctl = readl(psc->base + MDCTL + 4 * psc->lpsc); + mdctl &= ~MDSTAT_STATE_MASK; + mdctl |= next_state; + /* TODO: old davinci clocks for da850 set MDCTL_FORCE bit for sata and + * dsp here. Is this really needed? + */ + writel(mdctl, psc->base + MDCTL + 4 * psc->lpsc); + + pdstat = readl(psc->base + PDSTAT + 4 * psc->pd); + if ((pdstat & PDSTAT_STATE_MASK) == 0) { + pdctl = readl(psc->base + PDSTAT + 4 * psc->pd); + pdctl |= PDCTL_NEXT; + writel(pdctl, psc->base + PDSTAT + 4 * psc->pd); + + ptcmd = BIT(psc->pd); + writel(ptcmd, psc->base + PTCMD); + + do { + epcpr = __raw_readl(psc->base + EPCPR); + } while (!(epcpr & BIT(psc->pd))); + + pdctl = __raw_readl(psc->base + PDCTL + 4 * psc->pd); + pdctl |= PDCTL_EPCGOOD; + __raw_writel(pdctl, psc->base + PDCTL + 4 * psc->pd); + } else { + ptcmd = BIT(psc->pd); + writel(ptcmd, psc->base + PTCMD); + } + + do { + ptstat = readl(psc->base + PTSTAT); + } while (ptstat & BIT(psc->pd)); + + do { + mdstat = readl(psc->base + MDSTAT + 4 * psc->lpsc); + } while (!((mdstat & MDSTAT_STATE_MASK) == next_state)); +} + +static int davinci_psc_clk_enable(struct clk_hw *hw) +{ + struct davinci_psc_clk *psc = to_davinci_psc_clk(hw); + + psc_config(psc, PSC_STATE_ENABLE); + + return 0; +} + +static void davinci_psc_clk_disable(struct clk_hw *hw) +{ + struct davinci_psc_clk *psc = to_davinci_psc_clk(hw); + + psc_config(psc, PSC_STATE_DISABLE); +} + +static int davinci_psc_clk_is_enabled(struct clk_hw *hw) +{ + struct davinci_psc_clk *psc = to_davinci_psc_clk(hw); + u32 mdstat; + + mdstat = readl(psc->base + MDSTAT + 4 * psc->lpsc); + + return (mdstat & MDSTAT_MCKOUT) ? 1 : 0; +} + +static const struct clk_ops davinci_psc_clk_ops = { + .enable = davinci_psc_clk_enable, + .disable = davinci_psc_clk_disable, + .is_enabled = davinci_psc_clk_is_enabled, +}; + +/** + * davinci_psc_clk_register - register psc clock + * @dev: device that is registering this clock + * @name: name of this clock + * @parent_name: name of clock's parent + * @base: memory mapped register for the PSC + * @lpsc: local PSC number + * @pd: power domain + */ +struct clk *davinci_psc_clk_register(const char *name, + const char *parent_name, + void __iomem *base, + u32 lpsc, u32 pd) +{ + struct clk_init_data init; + struct davinci_psc_clk *psc; + struct clk *clk; + + psc = kzalloc(sizeof(*psc), GFP_KERNEL); + if (!psc) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &davinci_psc_clk_ops; + init.flags = 0; + init.parent_names = (parent_name ? &parent_name : NULL); + init.num_parents = (parent_name ? 1 : 0); + + psc->base = base; + psc->hw.init = &init; + psc->lpsc = lpsc; + psc->pd = pd; + + clk = clk_register(NULL, &psc->hw); + if (IS_ERR(clk)) + kfree(psc); + + return clk; +} + +/* FIXME: This needs to be converted to a reset controller. But, the reset + * framework is currently device tree only. + */ + +DEFINE_SPINLOCK(davinci_psc_reset_lock); + +static int davinci_psc_clk_reset(struct davinci_psc_clk *psc, bool reset) +{ + unsigned long flags; + u32 mdctl; + + if (IS_ERR_OR_NULL(psc)) + return -EINVAL; + + spin_lock_irqsave(&davinci_psc_reset_lock, flags); + mdctl = readl(psc->base + MDCTL + 4 * psc->lpsc); + if (reset) + mdctl &= ~MDCTL_LRESET; + else + mdctl |= MDCTL_LRESET; + writel(mdctl, psc->base + MDCTL + 4 * psc->lpsc); + spin_unlock_irqrestore(&davinci_psc_reset_lock, flags); + + return 0; +} + +int davinci_clk_reset_assert(struct clk *clk) +{ + struct davinci_psc_clk *psc = to_davinci_psc_clk(__clk_get_hw(clk)); + + return davinci_psc_clk_reset(psc, true); +} +EXPORT_SYMBOL(davinci_clk_reset_assert); + +int davinci_clk_reset_deassert(struct clk *clk) +{ + struct davinci_psc_clk *psc = to_davinci_psc_clk(__clk_get_hw(clk)); + + return davinci_psc_clk_reset(psc, false); +} +EXPORT_SYMBOL(davinci_clk_reset_deassert); diff --git a/include/linux/clk/davinci.h b/include/linux/clk/davinci.h new file mode 100644 index 0000000..c5d2181 --- /dev/null +++ b/include/linux/clk/davinci.h @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * TI Davinci clocks + * + * Copyright (C) 2017 David Lechner <david@lechnology.com> + */ +#ifndef __LINUX_CLK_DAVINCI_H__ +#define __LINUX_CLK_DAVINCI_H__ + +#include <linux/clk-provider.h> +#include <linux/types.h> + +struct clk *davinci_pll_clk_register(const char *name, + const char *parent_name, + void __iomem *base); +struct clk *davinci_pll_aux_clk_register(const char *name, + const char *parent_name, + void __iomem *base); +struct clk *davinci_pll_bpdiv_clk_register(const char *name, + const char *parent_name, + void __iomem *base); +struct clk *davinci_pll_obs_clk_register(const char *name, + const char * const *parent_names, + u8 num_parents, + void __iomem *base, + u32 *table); +struct clk *davinci_pll_div_clk_register(const char *name, + const char *parent_name, + void __iomem *base, + u32 id); +struct clk *davinci_psc_clk_register(const char *name, + const char *parent_name, + void __iomem *base, + u32 lpsc, u32 pd); + +/* convience macros for board declaration files */ +#define EXT_CLK(n, r) clk_register_fixed_rate(NULL, (n), NULL, 0, (r)) +#define FIX_CLK(n, p) clk_register_fixed_factor(NULL, (n), (p), 0, 1, 1) +#define PLL_CLK davinci_pll_clk_register +#define PLL_DIV_CLK davinci_pll_div_clk_register +#define PLL_AUX_CLK davinci_pll_aux_clk_register +#define PLL_BP_CLK davinci_pll_bpdiv_clk_register +#define PLL_OBS_CLK davinci_pll_obs_clk_register +#define PSC_CLK davinci_psc_clk_register + +#endif /* __LINUX_CLK_DAVINCI_H__ */ diff --git a/include/linux/platform_data/davinci_clk.h b/include/linux/platform_data/davinci_clk.h new file mode 100644 index 0000000..7576ace --- /dev/null +++ b/include/linux/platform_data/davinci_clk.h @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * TI DaVinci Clock support + * + * Copyright (C) 2017 David Lechner <david@lechnology.com> + */ + +#ifndef __PLATFORM_DATA_DAVINCI_CLK_H +#define __PLATFORM_DATA_DAVINCI_CLK_H + +#include <linux/types.h> + +/** + * da8xx_cfgchip_clk_data - DA8xx CFGCHIP clock platform data + * @usb0_use_refclkin: when true, use USB_REFCLKIN, otherwise use AUXCLK for + * USB 2.0 PHY clock + * @usb1_use_refclkin: when true, use USB_REFCLKIN, otherwise use USB 2.0 PHY + * PLL for USB 1.1 PHY clock + */ +struct da8xx_cfgchip_clk_data { + bool usb0_use_refclkin; + bool usb1_use_refclkin; +}; + +#endif /* __PLATFORM_DATA_DAVINCI_CLK_H */ -- 2.7.4 ^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v4 5/7] clk: Introduce davinci clocks 2017-12-31 23:39 ` [PATCH v4 5/7] clk: Introduce davinci clocks David Lechner @ 2018-01-01 0:23 ` David Lechner 2018-01-02 21:31 ` David Lechner 2018-01-04 12:43 ` Sekhar Nori 2 siblings, 0 replies; 29+ messages in thread From: David Lechner @ 2018-01-01 0:23 UTC (permalink / raw) To: linux-arm-kernel On 12/31/2017 05:39 PM, David Lechner wrote: > This introduces new drivers for arch/arm/mach-davinci. The code is based > on the clock drivers from there and adapted to use the common clock > framework. > > Signed-off-by: David Lechner <david@lechnology.com> > --- ... > diff --git a/drivers/clk/davinci/da8xx-cfgchip-clk.c b/drivers/clk/davinci/da8xx-cfgchip-clk.c > new file mode 100644 > index 0000000..780bb25 > --- /dev/null > +++ b/drivers/clk/davinci/da8xx-cfgchip-clk.c > @@ -0,0 +1,380 @@ ... > +static int da8xx_cfgchip_clk_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct da8xx_cfgchip_clk_data *pdata = dev->platform_data; > + struct da8xx_cfgchip_clk *phy_clk; > + const char *parent_name; > + struct clk *parent; > + int ret; > + > + if (!pdata) > + return -EINVAL; > + > + phy_clk = devm_kzalloc(dev, sizeof(*phy_clk), GFP_KERNEL); > + if (!phy_clk) > + return -ENOMEM; > + > + platform_set_drvdata(pdev, phy_clk); > + > + phy_clk->regmap = syscon_regmap_lookup_by_pdevname("syscon"); There is a mistake here. Device tree boards will fail to find "syscon". It should be: /* try device tree, then fall back to platform device */ phy_clk->regmap = syscon_regmap_lookup_by_compatible("ti,da830-cfgchip"); if (IS_ERR(phy_clk->regmap)) phy_clk->regmap = syscon_regmap_lookup_by_pdevname("syscon"); > + if (IS_ERR(phy_clk->regmap)) { > + dev_err(dev, "Failed to get syscon\n"); > + return PTR_ERR(phy_clk->regmap); > + } ^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v4 5/7] clk: Introduce davinci clocks 2017-12-31 23:39 ` [PATCH v4 5/7] clk: Introduce davinci clocks David Lechner 2018-01-01 0:23 ` David Lechner @ 2018-01-02 21:31 ` David Lechner 2018-01-04 12:28 ` Sekhar Nori 2018-01-04 12:43 ` Sekhar Nori 2 siblings, 1 reply; 29+ messages in thread From: David Lechner @ 2018-01-02 21:31 UTC (permalink / raw) To: linux-arm-kernel Forgot to cc linux-clk, so doing that now... On 12/31/2017 05:39 PM, David Lechner wrote: > This introduces new drivers for arch/arm/mach-davinci. The code is based > on the clock drivers from there and adapted to use the common clock > framework. > > Signed-off-by: David Lechner <david@lechnology.com> > --- > drivers/clk/Makefile | 1 + > drivers/clk/davinci/Makefile | 3 + > drivers/clk/davinci/da8xx-cfgchip-clk.c | 380 ++++++++++++++++++++++++++++++ > drivers/clk/davinci/pll.c | 333 ++++++++++++++++++++++++++ > drivers/clk/davinci/psc.c | 217 +++++++++++++++++ > include/linux/clk/davinci.h | 46 ++++ > include/linux/platform_data/davinci_clk.h | 25 ++ > 7 files changed, 1005 insertions(+) > create mode 100644 drivers/clk/davinci/Makefile > create mode 100644 drivers/clk/davinci/da8xx-cfgchip-clk.c > create mode 100644 drivers/clk/davinci/pll.c > create mode 100644 drivers/clk/davinci/psc.c > create mode 100644 include/linux/clk/davinci.h > create mode 100644 include/linux/platform_data/davinci_clk.h > > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile > index f7f761b..c865fd0 100644 > --- a/drivers/clk/Makefile > +++ b/drivers/clk/Makefile > @@ -60,6 +60,7 @@ obj-$(CONFIG_ARCH_ARTPEC) += axis/ > obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/ > obj-y += bcm/ > obj-$(CONFIG_ARCH_BERLIN) += berlin/ > +obj-$(CONFIG_ARCH_DAVINCI) += davinci/ > obj-$(CONFIG_H8300) += h8300/ > obj-$(CONFIG_ARCH_HISI) += hisilicon/ > obj-y += imgtec/ > diff --git a/drivers/clk/davinci/Makefile b/drivers/clk/davinci/Makefile > new file mode 100644 > index 0000000..5efbdcd > --- /dev/null > +++ b/drivers/clk/davinci/Makefile > @@ -0,0 +1,3 @@ > +obj-$(CONFIG_PHY_DA8XX_USB) += da8xx-cfgchip-clk.o > +obj-y += pll.o > +obj-y += psc.o > \ No newline at end of file > diff --git a/drivers/clk/davinci/da8xx-cfgchip-clk.c b/drivers/clk/davinci/da8xx-cfgchip-clk.c > new file mode 100644 > index 0000000..780bb25 > --- /dev/null > +++ b/drivers/clk/davinci/da8xx-cfgchip-clk.c > @@ -0,0 +1,380 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * da8xx-cfgchip-clk - TI DaVinci DA8xx CFGCHIP clocks driver > + * > + * Copyright (C) 2017 David Lechner <david@lechnology.com> > + * > + * This driver exposes the USB PHY clocks on DA8xx/AM18xx/OMAP-L13x SoCs. > + * The clocks consist of two muxes and a PLL. The USB 2.0 PHY mux and PLL are > + * combined into a single clock in Linux. The USB 1.0 PHY clock just consists > + * of a mux. These clocks are controlled through CFGCHIP2, which is accessed > + * as a syscon regmap since it is shared with other devices. > + */ > + > +#include <linux/clk.h> > +#include <linux/clkdev.h> > +#include <linux/clk-provider.h> > +#include <linux/io.h> > +#include <linux/of.h> > +#include <linux/mfd/da8xx-cfgchip.h> > +#include <linux/mfd/syscon.h> > +#include <linux/module.h> > +#include <linux/platform_data/davinci_clk.h> > +#include <linux/platform_device.h> > +#include <linux/regmap.h> > + > +/** > + * da8xx_cfgchip_clk > + * @usb0_hw: The USB 2.0 PHY clock (mux + PLL) > + * @usb1_hw: The USB 1.1 PHY clock (mux) > + * @usb0_clk: The USB 2.0 subsystem PSC clock > + * @regmap: The CFGCHIP syscon regmap > + */ > +struct da8xx_cfgchip_clk { > + struct clk_hw usb0_hw; > + struct clk_hw usb1_hw; > + struct clk *usb0_clk; > + struct regmap *regmap; > +}; > + > +/* The USB 2.0 PHY can use either USB_REFCLKIN or AUXCLK */ > +enum usb0_phy_clk_parent { > + USB20_PHY_CLK_PARENT_USB_REFCLKIN, > + USB20_PHY_CLK_PARENT_PLL0_AUX, > +}; > + > +/* The USB 1.1 PHY can use either the PLL output from the USB 2.0 PHY or > + * USB_REFCLKIN > + */ > +enum usb1_phy_clk_parent { > + USB1_PHY_CLK_PARENT_USB_REFCLKIN, > + USB1_PHY_CLK_PARENT_USB0_PHY_PLL, > +}; > + > +/* --- USB 2.0 PHY clock --- */ > + > +static int usb0_phy_clk_prepare(struct clk_hw *hw) > +{ > + struct da8xx_cfgchip_clk *clk = > + container_of(hw, struct da8xx_cfgchip_clk, usb0_hw); > + > + /* The USB 2.0 PSC clock is only needed temporarily during the USB 2.0 > + * PHY clock enable, but since clk_prepare() can't be called in an > + * atomic context (i.e. in clk_enable()), we have to prepare it here. > + */ > + return clk_prepare(clk->usb0_clk); > +} > + > +static void usb0_phy_clk_unprepare(struct clk_hw *hw) > +{ > + struct da8xx_cfgchip_clk *clk = > + container_of(hw, struct da8xx_cfgchip_clk, usb0_hw); > + > + clk_unprepare(clk->usb0_clk); > +} > + > +static int usb0_phy_clk_enable(struct clk_hw *hw) > +{ > + struct da8xx_cfgchip_clk *clk = > + container_of(hw, struct da8xx_cfgchip_clk, usb0_hw); > + unsigned int mask, val; > + int ret; > + > + /* Locking the USB 2.O PLL requires that the USB 2.O PSC is enabled > + * temporaily. It can be turned back off once the PLL is locked. > + */ > + clk_enable(clk->usb0_clk); > + > + /* Turn on the USB 2.0 PHY, but just the PLL, and not OTG. The USB 1.1 > + * PHY may use the USB 2.0 PLL clock without USB 2.0 OTG being used. > + */ > + mask = CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_PHY_PLLON; > + val = CFGCHIP2_PHY_PLLON; > + > + regmap_write_bits(clk->regmap, CFGCHIP(2), mask, val); > + ret = regmap_read_poll_timeout(clk->regmap, CFGCHIP(2), val, > + val & CFGCHIP2_PHYCLKGD, 0, 500000); > + > + clk_disable(clk->usb0_clk); > + > + return ret; > +} > + > +static void usb0_phy_clk_disable(struct clk_hw *hw) > +{ > + struct da8xx_cfgchip_clk *clk = > + container_of(hw, struct da8xx_cfgchip_clk, usb0_hw); > + unsigned int val; > + > + val = CFGCHIP2_PHYPWRDN; > + regmap_write_bits(clk->regmap, CFGCHIP(2), val, val); > +} > + > +static unsigned long usb0_phy_clk_recalc_rate(struct clk_hw *hw, > + unsigned long parent_rate) > +{ > + struct da8xx_cfgchip_clk *clk = > + container_of(hw, struct da8xx_cfgchip_clk, usb0_hw); > + unsigned int mask, val; > + > + /* The parent clock rate must be one of the following */ > + mask = CFGCHIP2_REFFREQ_MASK; > + switch (parent_rate) { > + case 12000000: > + val = CFGCHIP2_REFFREQ_12MHZ; > + break; > + case 13000000: > + val = CFGCHIP2_REFFREQ_13MHZ; > + break; > + case 19200000: > + val = CFGCHIP2_REFFREQ_19_2MHZ; > + break; > + case 20000000: > + val = CFGCHIP2_REFFREQ_20MHZ; > + break; > + case 24000000: > + val = CFGCHIP2_REFFREQ_24MHZ; > + break; > + case 26000000: > + val = CFGCHIP2_REFFREQ_26MHZ; > + break; > + case 38400000: > + val = CFGCHIP2_REFFREQ_38_4MHZ; > + break; > + case 40000000: > + val = CFGCHIP2_REFFREQ_40MHZ; > + break; > + case 48000000: > + val = CFGCHIP2_REFFREQ_48MHZ; > + break; > + default: > + return 0; > + } > + > + regmap_write_bits(clk->regmap, CFGCHIP(2), mask, val); > + > + /* USB 2.0 PLL always supplies 48MHz */ > + return 48000000; > +} > + > +static long usb0_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate, > + unsigned long *parent_rate) > +{ > + return 48000000; > +} > + > +static int usb0_phy_clk_set_parent(struct clk_hw *hw, u8 index) > +{ > + struct da8xx_cfgchip_clk *clk = > + container_of(hw, struct da8xx_cfgchip_clk, usb0_hw); > + unsigned int mask, val; > + > + /* Set the mux depending on the parent clock. */ > + mask = CFGCHIP2_USB2PHYCLKMUX; > + switch (index) { > + case USB20_PHY_CLK_PARENT_USB_REFCLKIN: > + val = 0; > + break; > + case USB20_PHY_CLK_PARENT_PLL0_AUX: > + val = CFGCHIP2_USB2PHYCLKMUX; > + break; > + default: > + return -EINVAL; > + } > + > + regmap_write_bits(clk->regmap, CFGCHIP(2), mask, val); > + > + return 0; > +} > + > +static u8 usb0_phy_clk_get_parent(struct clk_hw *hw) > +{ > + struct da8xx_cfgchip_clk *clk = > + container_of(hw, struct da8xx_cfgchip_clk, usb0_hw); > + unsigned int val; > + > + regmap_read(clk->regmap, CFGCHIP(2), &val); > + > + if (val & CFGCHIP2_USB2PHYCLKMUX) > + return USB20_PHY_CLK_PARENT_PLL0_AUX; > + > + return USB20_PHY_CLK_PARENT_USB_REFCLKIN; > +} > + > +static const struct clk_ops usb0_phy_clk_ops = { > + .prepare = usb0_phy_clk_prepare, > + .unprepare = usb0_phy_clk_unprepare, > + .enable = usb0_phy_clk_enable, > + .disable = usb0_phy_clk_disable, > + .recalc_rate = usb0_phy_clk_recalc_rate, > + .round_rate = usb0_phy_clk_round_rate, > + .set_parent = usb0_phy_clk_set_parent, > + .get_parent = usb0_phy_clk_get_parent, > +}; > + > +static const char * const usb0_phy_clk_parent_names[] = { > + [USB20_PHY_CLK_PARENT_USB_REFCLKIN] = "usb_refclkin", > + [USB20_PHY_CLK_PARENT_PLL0_AUX] = "pll0_aux_clk", > +}; > + > +static const struct clk_init_data usb0_phy_clk_init_data = { > + .name = "usb0_phy_clk", > + .ops = &usb0_phy_clk_ops, > + .parent_names = usb0_phy_clk_parent_names, > + .num_parents = ARRAY_SIZE(usb0_phy_clk_parent_names), > +}; > + > +/* --- USB 1.1 PHY clock --- */ > + > +static int usb1_phy_clk_set_parent(struct clk_hw *hw, u8 index) > +{ > + struct da8xx_cfgchip_clk *clk = > + container_of(hw, struct da8xx_cfgchip_clk, usb1_hw); > + unsigned int mask, val; > + > + /* Set the USB 1.1 PHY clock mux based on the parent clock. */ > + mask = CFGCHIP2_USB1PHYCLKMUX; > + switch (index) { > + case USB1_PHY_CLK_PARENT_USB_REFCLKIN: > + val = CFGCHIP2_USB1PHYCLKMUX; > + break; > + case USB1_PHY_CLK_PARENT_USB0_PHY_PLL: > + val = 0; > + break; > + default: > + return -EINVAL; > + } > + > + regmap_write_bits(clk->regmap, CFGCHIP(2), mask, val); > + > + return 0; > +} > + > +static u8 usb1_phy_clk_get_parent(struct clk_hw *hw) > +{ > + struct da8xx_cfgchip_clk *clk = > + container_of(hw, struct da8xx_cfgchip_clk, usb1_hw); > + unsigned int val; > + > + regmap_read(clk->regmap, CFGCHIP(2), &val); > + > + if (val & CFGCHIP2_USB1PHYCLKMUX) > + return USB1_PHY_CLK_PARENT_USB_REFCLKIN; > + > + return USB1_PHY_CLK_PARENT_USB0_PHY_PLL; > +} > + > +static const struct clk_ops usb1_phy_clk_ops = { > + .set_parent = usb1_phy_clk_set_parent, > + .get_parent = usb1_phy_clk_get_parent, > +}; > + > +static const char * const usb1_phy_clk_parent_names[] = { > + [USB1_PHY_CLK_PARENT_USB_REFCLKIN] = "usb_refclkin", > + [USB1_PHY_CLK_PARENT_USB0_PHY_PLL] = "usb0_phy_clk", > +}; > + > +static struct clk_init_data usb1_phy_clk_init_data = { > + .name = "usb1_phy_clk", > + .ops = &usb1_phy_clk_ops, > + .parent_names = usb1_phy_clk_parent_names, > + .num_parents = ARRAY_SIZE(usb1_phy_clk_parent_names), > +}; > + > +/* --- platform driver --- */ > + > +static int da8xx_cfgchip_clk_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct da8xx_cfgchip_clk_data *pdata = dev->platform_data; > + struct da8xx_cfgchip_clk *phy_clk; > + const char *parent_name; > + struct clk *parent; > + int ret; > + > + if (!pdata) > + return -EINVAL; > + > + phy_clk = devm_kzalloc(dev, sizeof(*phy_clk), GFP_KERNEL); > + if (!phy_clk) > + return -ENOMEM; > + > + platform_set_drvdata(pdev, phy_clk); > + > + phy_clk->regmap = syscon_regmap_lookup_by_pdevname("syscon"); > + if (IS_ERR(phy_clk->regmap)) { > + dev_err(dev, "Failed to get syscon\n"); > + return PTR_ERR(phy_clk->regmap); > + } > + > + /* USB 2.0 subsystem PSC clock - needed to lock PLL */ > + phy_clk->usb0_clk = clk_get(dev, "usb20"); > + if (IS_ERR(phy_clk->usb0_clk)) { > + dev_err(dev, "Failed to get usb20 clock\n"); > + return PTR_ERR(phy_clk->usb0_clk); > + } > + > + phy_clk->usb0_hw.init = &usb0_phy_clk_init_data; > + ret = devm_clk_hw_register(dev, &phy_clk->usb0_hw); > + if (ret) { > + dev_err(dev, "Failed to register usb0_phy_clk\n"); > + return ret; > + } > + > + phy_clk->usb1_hw.init = &usb1_phy_clk_init_data; > + ret = devm_clk_hw_register(dev, &phy_clk->usb1_hw); > + if (ret) { > + dev_err(dev, "Failed to register usb1_phy_clk\n"); > + return ret; > + } > + > + parent_name = pdata->usb0_use_refclkin ? "usb_refclkin" : "pll0_aux"; > + parent = devm_clk_get(dev, parent_name); > + if (IS_ERR(parent)) { > + dev_err(dev, "Failed to get usb0 parent clock %s\n", > + parent_name); > + return PTR_ERR(parent); > + } > + > + ret = clk_set_parent(phy_clk->usb0_hw.clk, parent); > + if (ret) { > + dev_err(dev, "Failed to set usb0 parent clock to %s\n", > + parent_name); > + return ret; > + } > + > + clk_hw_register_clkdev(&phy_clk->usb0_hw, NULL, "da8xx-cfgchip-clk"); > + > + parent_name = pdata->usb1_use_refclkin ? "usb_refclkin" : "usb0_phy_clk"; > + parent = devm_clk_get(dev, parent_name); > + if (IS_ERR(parent)) { > + dev_err(dev, "Failed to get usb1 parent clock %s\n", > + parent_name); > + return PTR_ERR(parent); > + } > + > + ret = clk_set_parent(phy_clk->usb1_hw.clk, parent); > + if (ret) { > + dev_err(dev, "Failed to set usb1 parent clock to %s\n", > + parent_name); > + return ret; > + } > + > + clk_hw_register_clkdev(&phy_clk->usb0_hw, "usb20_phy", "da8xx-usb-phy"); > + clk_hw_register_clkdev(&phy_clk->usb1_hw, "usb11_phy", "da8xx-usb-phy"); > + > + return 0; > +} > + > +static struct platform_driver da8xx_cfgchip_clk_driver = { > + .probe = da8xx_cfgchip_clk_probe, > + .driver = { > + .name = "da8xx-cfgchip-clk", > + }, > +}; > +module_platform_driver(da8xx_cfgchip_clk_driver); > + > +MODULE_ALIAS("platform:da8xx-cfgchip-clk"); > +MODULE_AUTHOR("David Lechner <david@lechnology.com>"); > +MODULE_DESCRIPTION("TI DA8xx CFGCHIP clock driver"); > +MODULE_LICENSE("GPL v2"); > diff --git a/drivers/clk/davinci/pll.c b/drivers/clk/davinci/pll.c > new file mode 100644 > index 0000000..035cd91 > --- /dev/null > +++ b/drivers/clk/davinci/pll.c > @@ -0,0 +1,333 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * PLL clock driver for Davinci devices > + * > + * Copyright (C) 2017 David Lechner <david@lechnology.com> > + * > + * Based on drivers/clk/keystone/pll.c > + * Copyright (C) 2013 Texas Instruments Inc. > + * Murali Karicheri <m-karicheri2@ti.com> > + * Santosh Shilimkar <santosh.shilimkar@ti.com> > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/err.h> > +#include <linux/io.h> > +#include <linux/slab.h> > + > +#define REVID 0x000 > +#define PLLCTL 0x100 > +#define OCSEL 0x104 > +#define PLLSECCTL 0x108 > +#define PLLM 0x110 > +#define PREDIV 0x114 > +#define PLLDIV1 0x118 > +#define PLLDIV2 0x11c > +#define PLLDIV3 0x120 > +#define OSCDIV 0x124 > +#define POSTDIV 0x128 > +#define BPDIV 0x12c > +#define PLLCMD 0x138 > +#define PLLSTAT 0x13c > +#define ALNCTL 0x140 > +#define DCHANGE 0x144 > +#define CKEN 0x148 > +#define CKSTAT 0x14c > +#define SYSTAT 0x150 > +#define PLLDIV4 0x160 > +#define PLLDIV5 0x164 > +#define PLLDIV6 0x168 > +#define PLLDIV7 0x16c > +#define PLLDIV8 0x170 > +#define PLLDIV9 0x174 > + > +#define PLLM_MASK 0x1f > +#define PREDIV_RATIO_MASK 0x1f > +#define PLLDIV_RATIO_WIDTH 5 > +#define PLLDIV_ENABLE_SHIFT 15 > +#define OSCDIV_RATIO_WIDTH 5 > +#define POSTDIV_RATIO_MASK 0x1f > +#define BPDIV_RATIO_SHIFT 0 > +#define BPDIV_RATIO_WIDTH 5 > +#define CKEN_OBSCLK_SHIFT 1 > +#define CKEN_AUXEN_SHIFT 0 > + > +/** > + * struct davinci_pll_clk - Main PLL clock > + * @hw: clk_hw for the pll > + * @base: Base memory address > + * @parent_rate: Saved parent rate used by some child clocks > + */ > +struct davinci_pll_clk { > + struct clk_hw hw; > + void __iomem *base; > +}; > + > +#define to_davinci_pll_clk(_hw) container_of((_hw), struct davinci_pll_clk, hw) > + > +static unsigned long davinci_pll_clk_recalc(struct clk_hw *hw, > + unsigned long parent_rate) > +{ > + struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); > + unsigned long rate = parent_rate; > + u32 prediv, mult, postdiv; > + > + prediv = readl(pll->base + PREDIV) & PREDIV_RATIO_MASK; > + mult = readl(pll->base + PLLM) & PLLM_MASK; > + postdiv = readl(pll->base + POSTDIV) & POSTDIV_RATIO_MASK; > + > + rate /= prediv + 1; > + rate *= mult + 1; > + rate /= postdiv + 1; > + > + return rate; > +} > + > +#ifdef CONFIG_DEBUG_FS > +#include <linux/debugfs.h> > + > +#define DEBUG_REG(n) \ > +{ \ > + .name = #n, \ > + .offset = n, \ > +} > + > +static const struct debugfs_reg32 davinci_pll_regs[] = { > + DEBUG_REG(REVID), > + DEBUG_REG(PLLCTL), > + DEBUG_REG(OCSEL), > + DEBUG_REG(PLLSECCTL), > + DEBUG_REG(PLLM), > + DEBUG_REG(PREDIV), > + DEBUG_REG(PLLDIV1), > + DEBUG_REG(PLLDIV2), > + DEBUG_REG(PLLDIV3), > + DEBUG_REG(OSCDIV), > + DEBUG_REG(POSTDIV), > + DEBUG_REG(BPDIV), > + DEBUG_REG(PLLCMD), > + DEBUG_REG(PLLSTAT), > + DEBUG_REG(ALNCTL), > + DEBUG_REG(DCHANGE), > + DEBUG_REG(CKEN), > + DEBUG_REG(CKSTAT), > + DEBUG_REG(SYSTAT), > + DEBUG_REG(PLLDIV4), > + DEBUG_REG(PLLDIV5), > + DEBUG_REG(PLLDIV6), > + DEBUG_REG(PLLDIV7), > + DEBUG_REG(PLLDIV8), > + DEBUG_REG(PLLDIV9), > +}; > + > +static int davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry) > +{ > + struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); > + struct debugfs_regset32 *regset; > + struct dentry *d; > + > + regset = kzalloc(sizeof(regset), GFP_KERNEL); > + if (!regset) > + return -ENOMEM; > + > + regset->regs = davinci_pll_regs; > + regset->nregs = ARRAY_SIZE(davinci_pll_regs); > + regset->base = pll->base; > + > + d = debugfs_create_regset32("registers", 0400, dentry, regset); > + if (IS_ERR(d)) { > + kfree(regset); > + return PTR_ERR(d); > + } > + > + return 0; > +} > +#else > +#define davinci_pll_debug_init NULL > +#endif > + > +static const struct clk_ops davinci_pll_clk_ops = { > + .recalc_rate = davinci_pll_clk_recalc, > + .debug_init = davinci_pll_debug_init, > +}; > + > +/** > + * davinci_pll_clk_register - Register a PLL clock > + * @name: The clock name > + * @parent_name: The parent clock name > + * @base: The PLL's memory region > + */ > +struct clk *davinci_pll_clk_register(const char *name, > + const char *parent_name, > + void __iomem *base) > +{ > + struct clk_init_data init; > + struct davinci_pll_clk *pll; > + struct clk *clk; > + > + pll = kzalloc(sizeof(*pll), GFP_KERNEL); > + if (!pll) > + return ERR_PTR(-ENOMEM); > + > + init.name = name; > + init.ops = &davinci_pll_clk_ops; > + init.parent_names = (parent_name ? &parent_name : NULL); > + init.num_parents = (parent_name ? 1 : 0); > + > + pll->base = base; > + pll->hw.init = &init; > + > + clk = clk_register(NULL, &pll->hw); > + if (IS_ERR(clk)) > + kfree(pll); > + > + return clk; > +} > + > +struct davinci_pll_aux_clk { > + struct clk_hw hw; > + struct davinci_pll_clk *pll; > +}; > + > +/** > + * davinci_pll_aux_clk_register - Register bypass clock (AUXCLK) > + * @name: The clock name > + * @parent_name: The parent clock name (usually "ref_clk" since this bypasses > + * the PLL) > + * @base: The PLL memory region > + */ > +struct clk *davinci_pll_aux_clk_register(const char *name, > + const char *parent_name, > + void __iomem *base) > +{ > + return clk_register_gate(NULL, name, parent_name, 0, base + CKEN, > + CKEN_AUXEN_SHIFT, 0, NULL); > +} > + > +/** > + * davinci_pll_bpdiv_clk_register - Register bypass divider clock (SYSCLKBP) > + * @name: The clock name > + * @parent_name: The parent clock name (usually "ref_clk" since this bypasses > + * the PLL) > + * @base: The PLL memory region > + */ > +struct clk *davinci_pll_bpdiv_clk_register(const char *name, > + const char *parent_name, > + void __iomem *base) > +{ > + return clk_register_divider(NULL, name, parent_name, 0, base + BPDIV, > + BPDIV_RATIO_SHIFT, BPDIV_RATIO_WIDTH, > + CLK_DIVIDER_READ_ONLY, NULL); > +} > + > +/** > + * davinci_pll_obs_clk_register - Register oscillator divider clock (OBSCLK) > + * @name: The clock name > + * @parent_names: The parent clock names > + * @num_parents: The number of paren clocks > + * @base: The PLL memory region > + * @table: A table of values cooresponding to the parent clocks (see OCSEL > + * register in SRM for values) > + */ > +struct clk *davinci_pll_obs_clk_register(const char *name, > + const char * const *parent_names, > + u8 num_parents, > + void __iomem *base, > + u32 *table) > +{ > + struct clk_mux *mux; > + struct clk_gate *gate; > + struct clk_divider *divider; > + struct clk *clk; > + > + mux = kzalloc(sizeof(*mux), GFP_KERNEL); > + if (!mux) > + return ERR_PTR(-ENOMEM); > + > + mux->reg = base + OCSEL; > + mux->table = table; > + > + gate = kzalloc(sizeof(*gate), GFP_KERNEL); > + if (!gate) { > + kfree(mux); > + return ERR_PTR(-ENOMEM); > + } > + > + gate->reg = base + CKEN; > + gate->bit_idx = CKEN_OBSCLK_SHIFT; > + > + divider = kzalloc(sizeof(*divider), GFP_KERNEL); > + if (!divider) { > + kfree(gate); > + kfree(mux); > + return ERR_PTR(-ENOMEM); > + } > + > + divider->reg = base + OSCDIV; > + divider->width = OSCDIV_RATIO_WIDTH; > + > + clk = clk_register_composite(NULL, name, parent_names, num_parents, > + &mux->hw, &clk_mux_ops, > + ÷r->hw, &clk_divider_ops, > + &gate->hw, &clk_gate_ops, 0); > + if (IS_ERR(clk)) { > + kfree(divider); > + kfree(gate); > + kfree(mux); > + } > + > + return clk; > +} > + > +/** > + * davinci_pll_div_clk_register - Register a PLLDIV (SYSCLK) clock > + * @name: The clock name > + * @parent_name: The parent clock name > + * @base: The PLL memory region > + * @id: The id of the divider (n in PLLDIVn) > + */ > +struct clk *davinci_pll_div_clk_register(const char *name, > + const char *parent_name, > + void __iomem *base, > + u32 id) > +{ > + const char * const *parent_names = (parent_name ? &parent_name : NULL); > + int num_parents = (parent_name ? 1 : 0); > + struct clk_gate *gate; > + struct clk_divider *divider; > + struct clk *clk; > + u32 reg; > + > + /* PLLDIVn registers are not entirely consecutive */ > + if (id < 4) > + reg = PLLDIV1 + 4 * (id - 1); > + else > + reg = PLLDIV4 + 4 * (id - 4); > + > + gate = kzalloc(sizeof(*gate), GFP_KERNEL); > + if (!gate) > + return ERR_PTR(-ENOMEM); > + > + gate->reg = base + reg; > + gate->bit_idx = PLLDIV_ENABLE_SHIFT; > + > + divider = kzalloc(sizeof(*divider), GFP_KERNEL); > + if (!divider) { > + kfree(gate); > + return ERR_PTR(-ENOMEM); > + } > + > + divider->reg = base + reg; > + divider->width = PLLDIV_RATIO_WIDTH; > + divider->flags = CLK_DIVIDER_READ_ONLY; > + > + clk = clk_register_composite(NULL, name, parent_names, num_parents, > + NULL, NULL, ÷r->hw, &clk_divider_ops, > + &gate->hw, &clk_gate_ops, 0); > + if (IS_ERR(clk)) { > + kfree(divider); > + kfree(gate); > + } > + > + return clk; > +} > diff --git a/drivers/clk/davinci/psc.c b/drivers/clk/davinci/psc.c > new file mode 100644 > index 0000000..8ae85ee > --- /dev/null > +++ b/drivers/clk/davinci/psc.c > @@ -0,0 +1,217 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Clock driver for DA8xx/AM17xx/AM18xx/OMAP-L13x PSC controllers > + * > + * Copyright (C) 2017 David Lechner <david@lechnology.com> > + * > + * Based on: drivers/clk/keystone/gate.c > + * Copyright (C) 2013 Texas Instruments. > + * Murali Karicheri <m-karicheri2@ti.com> > + * Santosh Shilimkar <santosh.shilimkar@ti.com> > + * > + * And: arch/arm/mach-davinci/psc.c > + * Copyright (C) 2006 Texas Instruments. > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/err.h> > +#include <linux/io.h> > +#include <linux/slab.h> > + > +/* PSC register offsets */ > +#define EPCPR 0x070 > +#define PTCMD 0x120 > +#define PTSTAT 0x128 > +#define PDSTAT 0x200 > +#define PDCTL 0x300 > +#define MDSTAT 0x800 > +#define MDCTL 0xa00 > + > +/* PSC module states */ > +enum davinci_psc_state { > + PSC_STATE_SWRSTDISABLE = 0, > + PSC_STATE_SYNCRST = 1, > + PSC_STATE_DISABLE = 2, > + PSC_STATE_ENABLE = 3, > +}; > + > +#define MDSTAT_STATE_MASK 0x3f > +#define MDSTAT_MCKOUT BIT(12) > +#define PDSTAT_STATE_MASK 0x1f > +#define MDCTL_FORCE BIT(31) > +#define MDCTL_LRESET BIT(8) > +#define PDCTL_EPCGOOD BIT(8) > +#define PDCTL_NEXT BIT(0) > + > +/** > + * struct davinci_psc_clk - PSC clock structure > + * @hw: clk_hw for the psc > + * @psc_data: PSC driver specific data > + * @lpsc: Local PSC number (module id) > + * @pd: Power domain > + */ > +struct davinci_psc_clk { > + struct clk_hw hw; > + void __iomem *base; > + u32 lpsc; > + u32 pd; > +}; > + > +#define to_davinci_psc_clk(_hw) container_of(_hw, struct davinci_psc_clk, hw) > + > +static void psc_config(struct davinci_psc_clk *psc, > + enum davinci_psc_state next_state) > +{ > + u32 epcpr, ptcmd, pdstat, pdctl, mdstat, mdctl, ptstat; > + > + mdctl = readl(psc->base + MDCTL + 4 * psc->lpsc); > + mdctl &= ~MDSTAT_STATE_MASK; > + mdctl |= next_state; > + /* TODO: old davinci clocks for da850 set MDCTL_FORCE bit for sata and > + * dsp here. Is this really needed? > + */ > + writel(mdctl, psc->base + MDCTL + 4 * psc->lpsc); > + > + pdstat = readl(psc->base + PDSTAT + 4 * psc->pd); > + if ((pdstat & PDSTAT_STATE_MASK) == 0) { > + pdctl = readl(psc->base + PDSTAT + 4 * psc->pd); > + pdctl |= PDCTL_NEXT; > + writel(pdctl, psc->base + PDSTAT + 4 * psc->pd); > + > + ptcmd = BIT(psc->pd); > + writel(ptcmd, psc->base + PTCMD); > + > + do { > + epcpr = __raw_readl(psc->base + EPCPR); > + } while (!(epcpr & BIT(psc->pd))); > + > + pdctl = __raw_readl(psc->base + PDCTL + 4 * psc->pd); > + pdctl |= PDCTL_EPCGOOD; > + __raw_writel(pdctl, psc->base + PDCTL + 4 * psc->pd); > + } else { > + ptcmd = BIT(psc->pd); > + writel(ptcmd, psc->base + PTCMD); > + } > + > + do { > + ptstat = readl(psc->base + PTSTAT); > + } while (ptstat & BIT(psc->pd)); > + > + do { > + mdstat = readl(psc->base + MDSTAT + 4 * psc->lpsc); > + } while (!((mdstat & MDSTAT_STATE_MASK) == next_state)); > +} > + > +static int davinci_psc_clk_enable(struct clk_hw *hw) > +{ > + struct davinci_psc_clk *psc = to_davinci_psc_clk(hw); > + > + psc_config(psc, PSC_STATE_ENABLE); > + > + return 0; > +} > + > +static void davinci_psc_clk_disable(struct clk_hw *hw) > +{ > + struct davinci_psc_clk *psc = to_davinci_psc_clk(hw); > + > + psc_config(psc, PSC_STATE_DISABLE); > +} > + > +static int davinci_psc_clk_is_enabled(struct clk_hw *hw) > +{ > + struct davinci_psc_clk *psc = to_davinci_psc_clk(hw); > + u32 mdstat; > + > + mdstat = readl(psc->base + MDSTAT + 4 * psc->lpsc); > + > + return (mdstat & MDSTAT_MCKOUT) ? 1 : 0; > +} > + > +static const struct clk_ops davinci_psc_clk_ops = { > + .enable = davinci_psc_clk_enable, > + .disable = davinci_psc_clk_disable, > + .is_enabled = davinci_psc_clk_is_enabled, > +}; > + > +/** > + * davinci_psc_clk_register - register psc clock > + * @dev: device that is registering this clock > + * @name: name of this clock > + * @parent_name: name of clock's parent > + * @base: memory mapped register for the PSC > + * @lpsc: local PSC number > + * @pd: power domain > + */ > +struct clk *davinci_psc_clk_register(const char *name, > + const char *parent_name, > + void __iomem *base, > + u32 lpsc, u32 pd) > +{ > + struct clk_init_data init; > + struct davinci_psc_clk *psc; > + struct clk *clk; > + > + psc = kzalloc(sizeof(*psc), GFP_KERNEL); > + if (!psc) > + return ERR_PTR(-ENOMEM); > + > + init.name = name; > + init.ops = &davinci_psc_clk_ops; > + init.flags = 0; > + init.parent_names = (parent_name ? &parent_name : NULL); > + init.num_parents = (parent_name ? 1 : 0); > + > + psc->base = base; > + psc->hw.init = &init; > + psc->lpsc = lpsc; > + psc->pd = pd; > + > + clk = clk_register(NULL, &psc->hw); > + if (IS_ERR(clk)) > + kfree(psc); > + > + return clk; > +} > + > +/* FIXME: This needs to be converted to a reset controller. But, the reset > + * framework is currently device tree only. > + */ > + > +DEFINE_SPINLOCK(davinci_psc_reset_lock); > + > +static int davinci_psc_clk_reset(struct davinci_psc_clk *psc, bool reset) > +{ > + unsigned long flags; > + u32 mdctl; > + > + if (IS_ERR_OR_NULL(psc)) > + return -EINVAL; > + > + spin_lock_irqsave(&davinci_psc_reset_lock, flags); > + mdctl = readl(psc->base + MDCTL + 4 * psc->lpsc); > + if (reset) > + mdctl &= ~MDCTL_LRESET; > + else > + mdctl |= MDCTL_LRESET; > + writel(mdctl, psc->base + MDCTL + 4 * psc->lpsc); > + spin_unlock_irqrestore(&davinci_psc_reset_lock, flags); > + > + return 0; > +} > + > +int davinci_clk_reset_assert(struct clk *clk) > +{ > + struct davinci_psc_clk *psc = to_davinci_psc_clk(__clk_get_hw(clk)); > + > + return davinci_psc_clk_reset(psc, true); > +} > +EXPORT_SYMBOL(davinci_clk_reset_assert); > + > +int davinci_clk_reset_deassert(struct clk *clk) > +{ > + struct davinci_psc_clk *psc = to_davinci_psc_clk(__clk_get_hw(clk)); > + > + return davinci_psc_clk_reset(psc, false); > +} > +EXPORT_SYMBOL(davinci_clk_reset_deassert); > diff --git a/include/linux/clk/davinci.h b/include/linux/clk/davinci.h > new file mode 100644 > index 0000000..c5d2181 > --- /dev/null > +++ b/include/linux/clk/davinci.h > @@ -0,0 +1,46 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * TI Davinci clocks > + * > + * Copyright (C) 2017 David Lechner <david@lechnology.com> > + */ > +#ifndef __LINUX_CLK_DAVINCI_H__ > +#define __LINUX_CLK_DAVINCI_H__ > + > +#include <linux/clk-provider.h> > +#include <linux/types.h> > + > +struct clk *davinci_pll_clk_register(const char *name, > + const char *parent_name, > + void __iomem *base); > +struct clk *davinci_pll_aux_clk_register(const char *name, > + const char *parent_name, > + void __iomem *base); > +struct clk *davinci_pll_bpdiv_clk_register(const char *name, > + const char *parent_name, > + void __iomem *base); > +struct clk *davinci_pll_obs_clk_register(const char *name, > + const char * const *parent_names, > + u8 num_parents, > + void __iomem *base, > + u32 *table); > +struct clk *davinci_pll_div_clk_register(const char *name, > + const char *parent_name, > + void __iomem *base, > + u32 id); > +struct clk *davinci_psc_clk_register(const char *name, > + const char *parent_name, > + void __iomem *base, > + u32 lpsc, u32 pd); > + > +/* convience macros for board declaration files */ > +#define EXT_CLK(n, r) clk_register_fixed_rate(NULL, (n), NULL, 0, (r)) > +#define FIX_CLK(n, p) clk_register_fixed_factor(NULL, (n), (p), 0, 1, 1) > +#define PLL_CLK davinci_pll_clk_register > +#define PLL_DIV_CLK davinci_pll_div_clk_register > +#define PLL_AUX_CLK davinci_pll_aux_clk_register > +#define PLL_BP_CLK davinci_pll_bpdiv_clk_register > +#define PLL_OBS_CLK davinci_pll_obs_clk_register > +#define PSC_CLK davinci_psc_clk_register > + > +#endif /* __LINUX_CLK_DAVINCI_H__ */ > diff --git a/include/linux/platform_data/davinci_clk.h b/include/linux/platform_data/davinci_clk.h > new file mode 100644 > index 0000000..7576ace > --- /dev/null > +++ b/include/linux/platform_data/davinci_clk.h > @@ -0,0 +1,25 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * TI DaVinci Clock support > + * > + * Copyright (C) 2017 David Lechner <david@lechnology.com> > + */ > + > +#ifndef __PLATFORM_DATA_DAVINCI_CLK_H > +#define __PLATFORM_DATA_DAVINCI_CLK_H > + > +#include <linux/types.h> > + > +/** > + * da8xx_cfgchip_clk_data - DA8xx CFGCHIP clock platform data > + * @usb0_use_refclkin: when true, use USB_REFCLKIN, otherwise use AUXCLK for > + * USB 2.0 PHY clock > + * @usb1_use_refclkin: when true, use USB_REFCLKIN, otherwise use USB 2.0 PHY > + * PLL for USB 1.1 PHY clock > + */ > +struct da8xx_cfgchip_clk_data { > + bool usb0_use_refclkin; > + bool usb1_use_refclkin; > +}; > + > +#endif /* __PLATFORM_DATA_DAVINCI_CLK_H */ > ^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v4 5/7] clk: Introduce davinci clocks 2018-01-02 21:31 ` David Lechner @ 2018-01-04 12:28 ` Sekhar Nori 2018-01-04 17:46 ` David Lechner 0 siblings, 1 reply; 29+ messages in thread From: Sekhar Nori @ 2018-01-04 12:28 UTC (permalink / raw) To: linux-arm-kernel On Wednesday 03 January 2018 03:01 AM, David Lechner wrote: > Forgot to cc linux-clk, so doing that now... > > > On 12/31/2017 05:39 PM, David Lechner wrote: >> This introduces new drivers for arch/arm/mach-davinci. The code is based >> on the clock drivers from there and adapted to use the common clock >> framework. >> >> Signed-off-by: David Lechner <david@lechnology.com> >> --- >> ? drivers/clk/Makefile????????????????????? |?? 1 + >> ? drivers/clk/davinci/Makefile????????????? |?? 3 + >> ? drivers/clk/davinci/da8xx-cfgchip-clk.c?? | 380 >> ++++++++++++++++++++++++++++++ >> ? drivers/clk/davinci/pll.c???????????????? | 333 >> ++++++++++++++++++++++++++ >> ? drivers/clk/davinci/psc.c???????????????? | 217 +++++++++++++++++ >> ? include/linux/clk/davinci.h?????????????? |? 46 ++++ >> ? include/linux/platform_data/davinci_clk.h |? 25 ++ >> ? 7 files changed, 1005 insertions(+) This is a pretty huge patch and I think each of cfgchip, pll and PSC clocks deserve a patch of their own. On the PLL patch, please describe how the PLL implementation on DaVinci is different from Keystone, so no reuse is really possible. Similarly for the PSC patch (no non-DT support in keystone etc). >> diff --git a/drivers/clk/davinci/psc.c b/drivers/clk/davinci/psc.c >> new file mode 100644 >> index 0000000..8ae85ee >> --- /dev/null >> +++ b/drivers/clk/davinci/psc.c >> @@ -0,0 +1,217 @@ >> +static void psc_config(struct davinci_psc_clk *psc, >> +?????????????? enum davinci_psc_state next_state) >> +{ >> +??? u32 epcpr, ptcmd, pdstat, pdctl, mdstat, mdctl, ptstat; >> + >> +??? mdctl = readl(psc->base + MDCTL + 4 * psc->lpsc); >> +??? mdctl &= ~MDSTAT_STATE_MASK; >> +??? mdctl |= next_state; >> +??? /* TODO: old davinci clocks for da850 set MDCTL_FORCE bit for >> sata and >> +???? * dsp here. Is this really needed? >> +???? */ >> +??? writel(mdctl, psc->base + MDCTL + 4 * psc->lpsc); >> + >> +??? pdstat = readl(psc->base + PDSTAT + 4 * psc->pd); >> +??? if ((pdstat & PDSTAT_STATE_MASK) == 0) { >> +??????? pdctl = readl(psc->base + PDSTAT + 4 * psc->pd); >> +??????? pdctl |= PDCTL_NEXT; >> +??????? writel(pdctl, psc->base + PDSTAT + 4 * psc->pd); >> + >> +??????? ptcmd = BIT(psc->pd); >> +??????? writel(ptcmd, psc->base + PTCMD); >> + >> +??????? do { >> +??????????? epcpr = __raw_readl(psc->base + EPCPR); >> +??????? } while (!(epcpr & BIT(psc->pd))); >> + >> +??????? pdctl = __raw_readl(psc->base + PDCTL + 4 * psc->pd); >> +??????? pdctl |= PDCTL_EPCGOOD; >> +??????? __raw_writel(pdctl, psc->base + PDCTL + 4 * psc->pd); Can we shift to regmap here too? Then the polling loops like above can be converted to regmap_read_poll_timeout() too like you have done elsewhere. Thanks, Sekhar ^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v4 5/7] clk: Introduce davinci clocks 2018-01-04 12:28 ` Sekhar Nori @ 2018-01-04 17:46 ` David Lechner 0 siblings, 0 replies; 29+ messages in thread From: David Lechner @ 2018-01-04 17:46 UTC (permalink / raw) To: linux-arm-kernel On 1/4/18 6:28 AM, Sekhar Nori wrote: > On Wednesday 03 January 2018 03:01 AM, David Lechner wrote: >> Forgot to cc linux-clk, so doing that now... >> >> >> On 12/31/2017 05:39 PM, David Lechner wrote: >>> This introduces new drivers for arch/arm/mach-davinci. The code is based >>> on the clock drivers from there and adapted to use the common clock >>> framework. >>> >>> Signed-off-by: David Lechner <david@lechnology.com> >>> --- >>> ? drivers/clk/Makefile????????????????????? |?? 1 + >>> ? drivers/clk/davinci/Makefile????????????? |?? 3 + >>> ? drivers/clk/davinci/da8xx-cfgchip-clk.c?? | 380 >>> ++++++++++++++++++++++++++++++ >>> ? drivers/clk/davinci/pll.c???????????????? | 333 >>> ++++++++++++++++++++++++++ >>> ? drivers/clk/davinci/psc.c???????????????? | 217 +++++++++++++++++ >>> ? include/linux/clk/davinci.h?????????????? |? 46 ++++ >>> ? include/linux/platform_data/davinci_clk.h |? 25 ++ >>> ? 7 files changed, 1005 insertions(+) > > This is a pretty huge patch and I think each of cfgchip, pll and PSC > clocks deserve a patch of their own. Will do. > > On the PLL patch, please describe how the PLL implementation on DaVinci > is different from Keystone, so no reuse is really possible. Similarly > for the PSC patch (no non-DT support in keystone etc). OK. > >>> diff --git a/drivers/clk/davinci/psc.c b/drivers/clk/davinci/psc.c >>> new file mode 100644 >>> index 0000000..8ae85ee >>> --- /dev/null >>> +++ b/drivers/clk/davinci/psc.c >>> @@ -0,0 +1,217 @@ > >>> +static void psc_config(struct davinci_psc_clk *psc, >>> +?????????????? enum davinci_psc_state next_state) >>> +{ >>> +??? u32 epcpr, ptcmd, pdstat, pdctl, mdstat, mdctl, ptstat; >>> + >>> +??? mdctl = readl(psc->base + MDCTL + 4 * psc->lpsc); >>> +??? mdctl &= ~MDSTAT_STATE_MASK; >>> +??? mdctl |= next_state; >>> +??? /* TODO: old davinci clocks for da850 set MDCTL_FORCE bit for >>> sata and >>> +???? * dsp here. Is this really needed? >>> +???? */ >>> +??? writel(mdctl, psc->base + MDCTL + 4 * psc->lpsc); >>> + >>> +??? pdstat = readl(psc->base + PDSTAT + 4 * psc->pd); >>> +??? if ((pdstat & PDSTAT_STATE_MASK) == 0) { >>> +??????? pdctl = readl(psc->base + PDSTAT + 4 * psc->pd); >>> +??????? pdctl |= PDCTL_NEXT; >>> +??????? writel(pdctl, psc->base + PDSTAT + 4 * psc->pd); >>> + >>> +??????? ptcmd = BIT(psc->pd); >>> +??????? writel(ptcmd, psc->base + PTCMD); >>> + >>> +??????? do { >>> +??????????? epcpr = __raw_readl(psc->base + EPCPR); >>> +??????? } while (!(epcpr & BIT(psc->pd))); >>> + >>> +??????? pdctl = __raw_readl(psc->base + PDCTL + 4 * psc->pd); >>> +??????? pdctl |= PDCTL_EPCGOOD; >>> +??????? __raw_writel(pdctl, psc->base + PDCTL + 4 * psc->pd); > > Can we shift to regmap here too? Then the polling loops like above can > be converted to regmap_read_poll_timeout() too like you have done elsewhere. > I'll give it a try. ^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v4 5/7] clk: Introduce davinci clocks 2017-12-31 23:39 ` [PATCH v4 5/7] clk: Introduce davinci clocks David Lechner 2018-01-01 0:23 ` David Lechner 2018-01-02 21:31 ` David Lechner @ 2018-01-04 12:43 ` Sekhar Nori 2018-01-04 17:47 ` David Lechner 2 siblings, 1 reply; 29+ messages in thread From: Sekhar Nori @ 2018-01-04 12:43 UTC (permalink / raw) To: linux-arm-kernel Hi David, On Monday 01 January 2018 05:09 AM, David Lechner wrote: > + /* TODO: old davinci clocks for da850 set MDCTL_FORCE bit for sata and > + * dsp here. Is this really needed? > + */ The commit that introduced this flag suggests so. commit aad70de20fc69970a3080e7e8f02b54a4a3fe3e6 Author: Sekhar Nori <nsekhar@ti.com> AuthorDate: Wed Jul 6 06:01:22 2011 +0000 Commit: Sekhar Nori <nsekhar@ti.com> CommitDate: Fri Jul 8 11:10:09 2011 +0530 davinci: enable forced transitions on PSC Some DaVinci modules like the SATA on DA850 need forced module state transitions. Define a "force" flag which can be passed to the PSC config function to enable it to make forced transitions. Forced transitions shouldn't normally be attempted, unless the TRM explicitly specifies its usage. ChangeLog: v2: Modified to take care of the fact that davinci_psc_config() now takes the flags directly. Signed-off-by: Sekhar Nori <nsekhar@ti.com> I can check without that flag again, but I do recall it being needed. Thanks, Sekhar ^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v4 5/7] clk: Introduce davinci clocks 2018-01-04 12:43 ` Sekhar Nori @ 2018-01-04 17:47 ` David Lechner 0 siblings, 0 replies; 29+ messages in thread From: David Lechner @ 2018-01-04 17:47 UTC (permalink / raw) To: linux-arm-kernel On 1/4/18 6:43 AM, Sekhar Nori wrote: > Hi David, > > On Monday 01 January 2018 05:09 AM, David Lechner wrote: >> + /* TODO: old davinci clocks for da850 set MDCTL_FORCE bit for sata and >> + * dsp here. Is this really needed? >> + */ > > The commit that introduced this flag suggests so. > > commit aad70de20fc69970a3080e7e8f02b54a4a3fe3e6 > Author: Sekhar Nori <nsekhar@ti.com> > AuthorDate: Wed Jul 6 06:01:22 2011 +0000 > Commit: Sekhar Nori <nsekhar@ti.com> > CommitDate: Fri Jul 8 11:10:09 2011 +0530 > > davinci: enable forced transitions on PSC > > Some DaVinci modules like the SATA on DA850 > need forced module state transitions. > > Define a "force" flag which can be passed to > the PSC config function to enable it to make > forced transitions. > > Forced transitions shouldn't normally be attempted, > unless the TRM explicitly specifies its usage. > > ChangeLog: > v2: > Modified to take care of the fact that > davinci_psc_config() now takes the flags > directly. > > Signed-off-by: Sekhar Nori <nsekhar@ti.com> > > I can check without that flag again, but I do recall it being needed. > OK, I will add it back. I need to add some other flags as well anyway. ^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v4 7/7] ARM: davinci_all_defconfig: remove CONFIG_DAVINCI_RESET_CLOCKS 2017-12-31 23:39 [PATCH v4 0/7] ARM: davinci: convert to common clock framework David Lechner ` (4 preceding siblings ...) 2017-12-31 23:39 ` [PATCH v4 5/7] clk: Introduce davinci clocks David Lechner @ 2017-12-31 23:39 ` David Lechner 2018-01-02 15:10 ` [PATCH v4 0/7] ARM: davinci: convert to common clock framework Adam Ford [not found] ` <1514763588-31560-7-git-send-email-david@lechnology.com> 7 siblings, 0 replies; 29+ messages in thread From: David Lechner @ 2017-12-31 23:39 UTC (permalink / raw) To: linux-arm-kernel This removes CONFIG_DAVINCI_RESET_CLOCKS. The option has been removed from the kernel. Signed-off-by: David Lechner <david@lechnology.com> --- arch/arm/configs/davinci_all_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig index 026154c..94d8946 100644 --- a/arch/arm/configs/davinci_all_defconfig +++ b/arch/arm/configs/davinci_all_defconfig @@ -31,7 +31,6 @@ CONFIG_MACH_MITYOMAPL138=y CONFIG_MACH_OMAPL138_HAWKBOARD=y CONFIG_DAVINCI_MUX_DEBUG=y CONFIG_DAVINCI_MUX_WARNINGS=y -CONFIG_DAVINCI_RESET_CLOCKS=y CONFIG_PREEMPT=y CONFIG_AEABI=y CONFIG_CMA=y -- 2.7.4 ^ permalink raw reply related [flat|nested] 29+ messages in thread
* Re: [PATCH v4 0/7] ARM: davinci: convert to common clock framework 2017-12-31 23:39 [PATCH v4 0/7] ARM: davinci: convert to common clock framework David Lechner ` (5 preceding siblings ...) 2017-12-31 23:39 ` [PATCH v4 7/7] ARM: davinci_all_defconfig: remove CONFIG_DAVINCI_RESET_CLOCKS David Lechner @ 2018-01-02 15:10 ` Adam Ford 2018-01-02 17:10 ` David Lechner 2018-01-03 16:57 ` Sekhar Nori [not found] ` <1514763588-31560-7-git-send-email-david@lechnology.com> 7 siblings, 2 replies; 29+ messages in thread From: Adam Ford @ 2018-01-02 15:10 UTC (permalink / raw) To: linux-arm-kernel On Sun, Dec 31, 2017 at 5:39 PM, David Lechner <david@lechnology.com> wrote: > This series converts mach-davinci to use the common clock framework. > > Basically, this series does some cleanup and rearranging to get things > ready for the conversion. Then there is a patch to add new driver in > drivers/clk and finally a patch to make the conversion from the mach > clock drivers to the new drivers. > > I have tested this on LEGO MINDSTORMS EV3 (TI AM1808), so I am confident > that I haven't broken anything (too badly) in da850. But, I don't have > other hardware to test. I tested this on a DA850-EVM, but I was not able to successfully get it to boot. It hangs during boot with no errors, oops's, or panics, but the standard 4.15.0-rc5 from linux-stable booted just fine. Maybe one of the TI guys will have some suggestions, but as-is, it appears to break at least the DA850-evm. > > The one thing that I know I have broken is CPU frequency scaling on da850. > I don't think it was working with device tree anyway, so I can't really test > it with the hardware I have. I'm hoping that it will be OK to defer fixing > it and add device tree support at the same time. > I agree with you that it's broken in the device tree, but I don't think it ever worked. > Dependencies: > * This series applies on top of "ARM: davinici: move watchdog restart from > mach to drivers" [1][2] > * On da850, you will also need a patch to prevent problems with the USB PHY > clocks [3] > * Or get it all at once: > git fetch https://github.com/dlech/ev3dev-kernel.git common-clk-v4 That is what I pulled to test. adam > > [1]: https://patchwork.kernel.org/patch/10105623/ > [2]: https://patchwork.kernel.org/patch/10105613/ > [3]: https://patchwork.kernel.org/patch/10133193/ > > > v4 changes: > * Basically, the whole series is new/reworked except for the first patch. > * Instead of having an intermediate conversion of the clocks in mach-davinci, > new clock drivers are introduced in drivers/clk. > * There are a few more cleanup patches added before making the conversion. > > v3 changes: > * Remove leftovers from rebasing in "ARM: davinci: don't use static clk_lookup" > (fixes compile error) > > v2 changes: > * Dropped "ARM: davinci: clean up map_io functions" - will resend as separate > patch series > * Reworked remaining patches so that there is less shuffling around > > > > David Lechner (7): > ARM: davinci: move davinci_clk_init() to init_time > ARM: davinci: don't use static clk_lookup > ARM: davinci: fix duplicate clocks > ARM: davinci: remove davinci_set_refclk_rate() > clk: Introduce davinci clocks > ARM: davinci: convert to common clock framework > ARM: davinci_all_defconfig: remove CONFIG_DAVINCI_RESET_CLOCKS > > arch/arm/Kconfig | 2 +- > arch/arm/configs/davinci_all_defconfig | 1 - > arch/arm/mach-davinci/Kconfig | 12 - > arch/arm/mach-davinci/Makefile | 2 +- > arch/arm/mach-davinci/board-da830-evm.c | 17 +- > arch/arm/mach-davinci/board-da850-evm.c | 2 +- > arch/arm/mach-davinci/board-dm355-evm.c | 2 +- > arch/arm/mach-davinci/board-dm355-leopard.c | 2 +- > arch/arm/mach-davinci/board-dm365-evm.c | 2 +- > arch/arm/mach-davinci/board-dm644x-evm.c | 2 +- > arch/arm/mach-davinci/board-dm646x-evm.c | 17 +- > arch/arm/mach-davinci/board-mityomapl138.c | 2 +- > arch/arm/mach-davinci/board-neuros-osd2.c | 2 +- > arch/arm/mach-davinci/board-omapl138-hawk.c | 17 +- > arch/arm/mach-davinci/board-sffsdr.c | 2 +- > arch/arm/mach-davinci/clock.c | 745 -------------------------- > arch/arm/mach-davinci/clock.h | 72 --- > arch/arm/mach-davinci/common.c | 1 - > arch/arm/mach-davinci/da830.c | 536 +++++-------------- > arch/arm/mach-davinci/da850.c | 785 ++++++---------------------- > arch/arm/mach-davinci/da8xx-dt.c | 17 +- > arch/arm/mach-davinci/davinci.h | 4 + > arch/arm/mach-davinci/devices-da8xx.c | 46 +- > arch/arm/mach-davinci/dm355.c | 452 ++++------------ > arch/arm/mach-davinci/dm365.c | 594 ++++++--------------- > arch/arm/mach-davinci/dm644x.c | 401 ++++---------- > arch/arm/mach-davinci/dm646x.c | 451 +++++----------- > arch/arm/mach-davinci/include/mach/clock.h | 3 - > arch/arm/mach-davinci/include/mach/common.h | 9 - > arch/arm/mach-davinci/include/mach/da8xx.h | 11 +- > arch/arm/mach-davinci/psc.c | 137 ----- > arch/arm/mach-davinci/psc.h | 14 - > arch/arm/mach-davinci/usb-da8xx.c | 225 +------- > drivers/clk/Makefile | 1 + > drivers/clk/davinci/Makefile | 3 + > drivers/clk/davinci/da8xx-cfgchip-clk.c | 380 ++++++++++++++ > drivers/clk/davinci/pll.c | 333 ++++++++++++ > drivers/clk/davinci/psc.c | 217 ++++++++ > include/linux/clk/davinci.h | 46 ++ > include/linux/platform_data/davinci_clk.h | 25 + > 40 files changed, 1875 insertions(+), 3717 deletions(-) > delete mode 100644 arch/arm/mach-davinci/clock.c > delete mode 100644 arch/arm/mach-davinci/psc.c > create mode 100644 drivers/clk/davinci/Makefile > create mode 100644 drivers/clk/davinci/da8xx-cfgchip-clk.c > create mode 100644 drivers/clk/davinci/pll.c > create mode 100644 drivers/clk/davinci/psc.c > create mode 100644 include/linux/clk/davinci.h > create mode 100644 include/linux/platform_data/davinci_clk.h > > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v4 0/7] ARM: davinci: convert to common clock framework 2018-01-02 15:10 ` [PATCH v4 0/7] ARM: davinci: convert to common clock framework Adam Ford @ 2018-01-02 17:10 ` David Lechner 2018-01-02 18:31 ` David Lechner 2018-01-03 16:57 ` Sekhar Nori 1 sibling, 1 reply; 29+ messages in thread From: David Lechner @ 2018-01-02 17:10 UTC (permalink / raw) To: linux-arm-kernel On 01/02/2018 09:10 AM, Adam Ford wrote: > On Sun, Dec 31, 2017 at 5:39 PM, David Lechner <david@lechnology.com> wrote: >> This series converts mach-davinci to use the common clock framework. >> >> Basically, this series does some cleanup and rearranging to get things >> ready for the conversion. Then there is a patch to add new driver in >> drivers/clk and finally a patch to make the conversion from the mach >> clock drivers to the new drivers. >> >> I have tested this on LEGO MINDSTORMS EV3 (TI AM1808), so I am confident >> that I haven't broken anything (too badly) in da850. But, I don't have >> other hardware to test. > > I tested this on a DA850-EVM, but I was not able to successfully get it to boot. > > It hangs during boot with no errors, oops's, or panics, but the > standard 4.15.0-rc5 from linux-stable booted just fine. > > Maybe one of the TI guys will have some suggestions, but as-is, it > appears to break at least the DA850-evm. > Thanks for testing. Unfortunately, the only hardware I have is the LEGO MINDSTORMS, so I will have to rely on others to help with the debugging. If you or anyone else with one of these boards can make the time, please compile with: CONFIG_DEBUG_LL=y CONFIG_EARLY_PRINTK=y and add "earlyprintk" to the kernel command line options. You may need to select a different UART for this depending on your board. I think UART1 is the default in the kernel configuration. On da850 devices comment out the line: clk_set_parent(clk, pll1_sysclk2_clk); in da850.c when doing earlyprintk, otherwise the UART1 and UART2 clock source will change during boot and cause garbled output after a point. >> >> The one thing that I know I have broken is CPU frequency scaling on da850. >> I don't think it was working with device tree anyway, so I can't really test >> it with the hardware I have. I'm hoping that it will be OK to defer fixing >> it and add device tree support at the same time. >> > > I agree with you that it's broken in the device tree, but I don't > think it ever worked. > >> Dependencies: >> * This series applies on top of "ARM: davinici: move watchdog restart from >> mach to drivers" [1][2] >> * On da850, you will also need a patch to prevent problems with the USB PHY >> clocks [3] >> * Or get it all at once: >> git fetch https://github.com/dlech/ev3dev-kernel.git common-clk-v4 > > That is what I pulled to test. > > adam > ^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v4 0/7] ARM: davinci: convert to common clock framework 2018-01-02 17:10 ` David Lechner @ 2018-01-02 18:31 ` David Lechner 0 siblings, 0 replies; 29+ messages in thread From: David Lechner @ 2018-01-02 18:31 UTC (permalink / raw) To: linux-arm-kernel On 01/02/2018 11:10 AM, David Lechner wrote: > > and add "earlyprintk" to the kernel command line options. The "clk_ignore_unused" command line option could be useful as well ^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v4 0/7] ARM: davinci: convert to common clock framework 2018-01-02 15:10 ` [PATCH v4 0/7] ARM: davinci: convert to common clock framework Adam Ford 2018-01-02 17:10 ` David Lechner @ 2018-01-03 16:57 ` Sekhar Nori 1 sibling, 0 replies; 29+ messages in thread From: Sekhar Nori @ 2018-01-03 16:57 UTC (permalink / raw) To: linux-arm-kernel On Tuesday 02 January 2018 08:40 PM, Adam Ford wrote: > On Sun, Dec 31, 2017 at 5:39 PM, David Lechner <david@lechnology.com> wrote: >> This series converts macreqh-davinci to use the common clock framework. >> >> Basically, this series does some cleanup and rearranging to get things >> ready for the conversion. Then there is a patch to add new driver in >> drivers/clk and finally a patch to make the conversion from the mach >> clock drivers to the new drivers. >> >> I have tested this on LEGO MINDSTORMS EV3 (TI AM1808), so I am confident >> that I haven't broken anything (too badly) in da850. But, I don't have >> other hardware to test. > > I tested this on a DA850-EVM, but I was not able to successfully get it to boot. > > It hangs during boot with no errors, oops's, or panics, but the > standard 4.15.0-rc5 from linux-stable booted just fine. > > Maybe one of the TI guys will have some suggestions, but as-is, it > appears to break at least the DA850-evm. I haven't gotten to looking into this series yet. Should happen by Friday this week. >> The one thing that I know I have broken is CPU frequency scaling on da850. >> I don't think it was working with device tree anyway, so I can't really test >> it with the hardware I have. I'm hoping that it will be OK to defer fixing >> it and add device tree support at the same time. >> > > I agree with you that it's broken in the device tree, but I don't > think it ever worked. It was working with legacy board file method. Its not supported with DT, yes. Most probably, the generic cpufreq-dt support needs to be used for the DT case. Thanks, Sekhar ^ permalink raw reply [flat|nested] 29+ messages in thread
[parent not found: <1514763588-31560-7-git-send-email-david@lechnology.com>]
* [PATCH v4 6/7] ARM: davinci: convert to common clock framework [not found] ` <1514763588-31560-7-git-send-email-david@lechnology.com> @ 2018-01-04 12:39 ` Sekhar Nori 2018-01-04 17:50 ` David Lechner 0 siblings, 1 reply; 29+ messages in thread From: Sekhar Nori @ 2018-01-04 12:39 UTC (permalink / raw) To: linux-arm-kernel On Monday 01 January 2018 05:09 AM, David Lechner wrote: > This converts all of arch/arm/mach-davinci to the common clock framework. > The clock drivers from clock.c and psc.c have been moved to drivers/clk, > so these files are removed. > > There is one subtle change in the clock trees. AUX, BPDIV and OSCDIV > clocks now have "ref_clk" as a parent instead of the PLL clock. These > clocks are part of the PLL's MMIO block, but they bypass the PLL and > therefore it makes more sense to have "ref_clk" as their parent since > "ref_clk" is the input clock of the PLL. > > CONFIG_DAVINCI_RESET_CLOCKS is removed since the common clock frameworks > takes care of disabling unused clocks. > > Known issue: This breaks CPU frequency scaling on da850. This functionality needs to be restored as part of this series since we cannot commit anything with regressions. > > Also, the order of #includes are cleaned up in files while we are touching > this code. > > Signed-off-by: David Lechner <david@lechnology.com> This is a pretty huge patch again and I hope it can be broken down. Ideally one per SoC converted and then the unused code removal. Thanks, Sekhar ^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v4 6/7] ARM: davinci: convert to common clock framework 2018-01-04 12:39 ` [PATCH v4 6/7] ARM: davinci: convert to common clock framework Sekhar Nori @ 2018-01-04 17:50 ` David Lechner 2018-01-04 19:26 ` Adam Ford 2018-01-05 2:59 ` David Lechner 0 siblings, 2 replies; 29+ messages in thread From: David Lechner @ 2018-01-04 17:50 UTC (permalink / raw) To: linux-arm-kernel On 1/4/18 6:39 AM, Sekhar Nori wrote: > On Monday 01 January 2018 05:09 AM, David Lechner wrote: >> This converts all of arch/arm/mach-davinci to the common clock framework. >> The clock drivers from clock.c and psc.c have been moved to drivers/clk, >> so these files are removed. >> >> There is one subtle change in the clock trees. AUX, BPDIV and OSCDIV >> clocks now have "ref_clk" as a parent instead of the PLL clock. These >> clocks are part of the PLL's MMIO block, but they bypass the PLL and >> therefore it makes more sense to have "ref_clk" as their parent since >> "ref_clk" is the input clock of the PLL. >> >> CONFIG_DAVINCI_RESET_CLOCKS is removed since the common clock frameworks >> takes care of disabling unused clocks. >> >> Known issue: This breaks CPU frequency scaling on da850. > > This functionality needs to be restored as part of this series since we > cannot commit anything with regressions. > Do you have a suggestion on how to accomplish this? I don't have a board for testing, so I don't have a way of knowing if my changes will work or not. >> >> Also, the order of #includes are cleaned up in files while we are touching >> this code. >> >> Signed-off-by: David Lechner <david@lechnology.com> > > This is a pretty huge patch again and I hope it can be broken down. > Ideally one per SoC converted and then the unused code removal. > Will do. ^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v4 6/7] ARM: davinci: convert to common clock framework 2018-01-04 17:50 ` David Lechner @ 2018-01-04 19:26 ` Adam Ford 2018-01-04 21:22 ` David Lechner 2018-01-05 2:59 ` David Lechner 1 sibling, 1 reply; 29+ messages in thread From: Adam Ford @ 2018-01-04 19:26 UTC (permalink / raw) To: linux-arm-kernel On Thu, Jan 4, 2018 at 11:50 AM, David Lechner <david@lechnology.com> wrote: > > > On 1/4/18 6:39 AM, Sekhar Nori wrote: >> >> On Monday 01 January 2018 05:09 AM, David Lechner wrote: >>> >>> This converts all of arch/arm/mach-davinci to the common clock framework. >>> The clock drivers from clock.c and psc.c have been moved to drivers/clk, >>> so these files are removed. >>> >>> There is one subtle change in the clock trees. AUX, BPDIV and OSCDIV >>> clocks now have "ref_clk" as a parent instead of the PLL clock. These >>> clocks are part of the PLL's MMIO block, but they bypass the PLL and >>> therefore it makes more sense to have "ref_clk" as their parent since >>> "ref_clk" is the input clock of the PLL. >>> >>> CONFIG_DAVINCI_RESET_CLOCKS is removed since the common clock frameworks >>> takes care of disabling unused clocks. >>> >>> Known issue: This breaks CPU frequency scaling on da850. >> >> >> This functionality needs to be restored as part of this series since we >> cannot commit anything with regressions. >> > > Do you have a suggestion on how to accomplish this? I don't have a board for > testing, so I don't have a way of knowing if my changes will work or not. I work for Logic PD who makes the original da850-evm. I can help if you want to send me patches. It would be better if you had a git repo setup where I could just clone the repo and tests. Having a larger collection of smaller the patches would also give me the ability to bisect down to help determine what actually breaks the da850-evm vs a few large patches. Do you still need me to run the board with some of the extra debugging enabled, or should I wait for the next round of patches? adam > >>> >>> Also, the order of #includes are cleaned up in files while we are >>> touching >>> this code. >>> >>> Signed-off-by: David Lechner <david@lechnology.com> >> >> >> This is a pretty huge patch again and I hope it can be broken down. >> Ideally one per SoC converted and then the unused code removal. >> > > Will do. ^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v4 6/7] ARM: davinci: convert to common clock framework 2018-01-04 19:26 ` Adam Ford @ 2018-01-04 21:22 ` David Lechner 0 siblings, 0 replies; 29+ messages in thread From: David Lechner @ 2018-01-04 21:22 UTC (permalink / raw) To: linux-arm-kernel On 01/04/2018 01:26 PM, Adam Ford wrote: > On Thu, Jan 4, 2018 at 11:50 AM, David Lechner <david@lechnology.com> wrote: >> >> >> On 1/4/18 6:39 AM, Sekhar Nori wrote: >>> >>> On Monday 01 January 2018 05:09 AM, David Lechner wrote: >>>> >>>> This converts all of arch/arm/mach-davinci to the common clock framework. >>>> The clock drivers from clock.c and psc.c have been moved to drivers/clk, >>>> so these files are removed. >>>> >>>> There is one subtle change in the clock trees. AUX, BPDIV and OSCDIV >>>> clocks now have "ref_clk" as a parent instead of the PLL clock. These >>>> clocks are part of the PLL's MMIO block, but they bypass the PLL and >>>> therefore it makes more sense to have "ref_clk" as their parent since >>>> "ref_clk" is the input clock of the PLL. >>>> >>>> CONFIG_DAVINCI_RESET_CLOCKS is removed since the common clock frameworks >>>> takes care of disabling unused clocks. >>>> >>>> Known issue: This breaks CPU frequency scaling on da850. >>> >>> >>> This functionality needs to be restored as part of this series since we >>> cannot commit anything with regressions. >>> >> >> Do you have a suggestion on how to accomplish this? I don't have a board for >> testing, so I don't have a way of knowing if my changes will work or not. > > I work for Logic PD who makes the original da850-evm. I can help if > you want to send me patches. It would be better if you had a git repo > setup where I could just clone the repo and tests. > > Having a larger collection of smaller the patches would also give me > the ability to bisect down to help determine what actually breaks the > da850-evm vs a few large patches. > > Do you still need me to run the board with some of the extra debugging > enabled, or should I wait for the next round of patches? > You might as well wait until I resubmit. There are going to be some significant changes. ^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v4 6/7] ARM: davinci: convert to common clock framework 2018-01-04 17:50 ` David Lechner 2018-01-04 19:26 ` Adam Ford @ 2018-01-05 2:59 ` David Lechner 2018-01-05 10:42 ` Sekhar Nori 1 sibling, 1 reply; 29+ messages in thread From: David Lechner @ 2018-01-05 2:59 UTC (permalink / raw) To: linux-arm-kernel On 01/04/2018 11:50 AM, David Lechner wrote: > > > On 1/4/18 6:39 AM, Sekhar Nori wrote: >> On Monday 01 January 2018 05:09 AM, David Lechner wrote: >>> This converts all of arch/arm/mach-davinci to the common clock framework. >>> The clock drivers from clock.c and psc.c have been moved to drivers/clk, >>> so these files are removed. >>> >>> There is one subtle change in the clock trees. AUX, BPDIV and OSCDIV >>> clocks now have "ref_clk" as a parent instead of the PLL clock. These >>> clocks are part of the PLL's MMIO block, but they bypass the PLL and >>> therefore it makes more sense to have "ref_clk" as their parent since >>> "ref_clk" is the input clock of the PLL. >>> >>> CONFIG_DAVINCI_RESET_CLOCKS is removed since the common clock frameworks >>> takes care of disabling unused clocks. >>> >>> Known issue: This breaks CPU frequency scaling on da850. >> >> This functionality needs to be restored as part of this series since we >> cannot commit anything with regressions. >> > > Do you have a suggestion on how to accomplish this? I don't have a board for testing, so I don't have a way of knowing if my changes will work or not. > >>> >>> Also, the order of #includes are cleaned up in files while we are touching >>> this code. >>> >>> Signed-off-by: David Lechner <david@lechnology.com> >> >> This is a pretty huge patch again and I hope it can be broken down. >> Ideally one per SoC converted and then the unused code removal. >> > > Will do. Well, I can do this, but I don't think it will compile or run. We can't have the common clock framework and the legacy davinci clocks enabled at the same time. ^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v4 6/7] ARM: davinci: convert to common clock framework 2018-01-05 2:59 ` David Lechner @ 2018-01-05 10:42 ` Sekhar Nori 2018-01-06 1:42 ` David Lechner 0 siblings, 1 reply; 29+ messages in thread From: Sekhar Nori @ 2018-01-05 10:42 UTC (permalink / raw) To: linux-arm-kernel On Friday 05 January 2018 08:29 AM, David Lechner wrote: > On 01/04/2018 11:50 AM, David Lechner wrote: >> On 1/4/18 6:39 AM, Sekhar Nori wrote: >>> This is a pretty huge patch again and I hope it can be broken down. >>> Ideally one per SoC converted and then the unused code removal. >>> >> >> Will do. > > Well, I can do this, but I don't think it will compile or run. We can't > have the common clock framework and the legacy davinci clocks enabled at > the same time. I see. Can you at least hive off the code removal into a separate patch for next submission. I will then take a closer look at this. Thanks, Sekhar ^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v4 6/7] ARM: davinci: convert to common clock framework 2018-01-05 10:42 ` Sekhar Nori @ 2018-01-06 1:42 ` David Lechner 2018-01-08 5:36 ` Sekhar Nori 0 siblings, 1 reply; 29+ messages in thread From: David Lechner @ 2018-01-06 1:42 UTC (permalink / raw) To: linux-arm-kernel On 01/05/2018 04:42 AM, Sekhar Nori wrote: > On Friday 05 January 2018 08:29 AM, David Lechner wrote: >> On 01/04/2018 11:50 AM, David Lechner wrote: >>> On 1/4/18 6:39 AM, Sekhar Nori wrote: > >>>> This is a pretty huge patch again and I hope it can be broken down. >>>> Ideally one per SoC converted and then the unused code removal. >>>> >>> >>> Will do. >> >> Well, I can do this, but I don't think it will compile or run. We can't >> have the common clock framework and the legacy davinci clocks enabled at >> the same time. > > I see. Can you at least hive off the code removal into a separate patch > for next submission. I will then take a closer look at this. > I've realized that I can accomplish this if I use some #if 0/#endif blocks temporarily if that sounds OK. ^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v4 6/7] ARM: davinci: convert to common clock framework 2018-01-06 1:42 ` David Lechner @ 2018-01-08 5:36 ` Sekhar Nori 0 siblings, 0 replies; 29+ messages in thread From: Sekhar Nori @ 2018-01-08 5:36 UTC (permalink / raw) To: linux-arm-kernel On Saturday 06 January 2018 07:12 AM, David Lechner wrote: > On 01/05/2018 04:42 AM, Sekhar Nori wrote: >> On Friday 05 January 2018 08:29 AM, David Lechner wrote: >>> On 01/04/2018 11:50 AM, David Lechner wrote: >>>> On 1/4/18 6:39 AM, Sekhar Nori wrote: >> >>>>> This is a pretty huge patch again and I hope it can be broken down. >>>>> Ideally one per SoC converted and then the unused code removal. >>>>> >>>> >>>> Will do. >>> >>> Well, I can do this, but I don't think it will compile or run. We can't >>> have the common clock framework and the legacy davinci clocks enabled at >>> the same time. >> >> I see. Can you at least hive off the code removal into a separate patch >> for next submission. I will then take a closer look at this. >> > > I've realized that I can accomplish this if I use some #if 0/#endif blocks > temporarily if that sounds OK. I haven't looked at your latest submission, but this wont be acceptable. Even as a temporary measure. If the patch cannot be broken down any, thats fine. I just wanted to explore the possibility to ease review. Thanks, Sekhar ^ permalink raw reply [flat|nested] 29+ messages in thread
end of thread, other threads:[~2018-01-08 5:36 UTC | newest]
Thread overview: 29+ messages (download: mbox.gz follow: Atom feed
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2017-12-31 23:39 [PATCH v4 0/7] ARM: davinci: convert to common clock framework David Lechner
2017-12-31 23:39 ` [PATCH v4 1/7] ARM: davinci: move davinci_clk_init() to init_time David Lechner
2017-12-31 23:39 ` [PATCH v4 2/7] ARM: davinci: don't use static clk_lookup David Lechner
2018-01-04 11:10 ` Sekhar Nori
2018-01-04 17:43 ` David Lechner
2017-12-31 23:39 ` [PATCH v4 3/7] ARM: davinci: fix duplicate clocks David Lechner
2018-01-04 11:12 ` Sekhar Nori
2018-01-04 17:44 ` David Lechner
2017-12-31 23:39 ` [PATCH v4 4/7] ARM: davinci: remove davinci_set_refclk_rate() David Lechner
2017-12-31 23:39 ` [PATCH v4 5/7] clk: Introduce davinci clocks David Lechner
2018-01-01 0:23 ` David Lechner
2018-01-02 21:31 ` David Lechner
2018-01-04 12:28 ` Sekhar Nori
2018-01-04 17:46 ` David Lechner
2018-01-04 12:43 ` Sekhar Nori
2018-01-04 17:47 ` David Lechner
2017-12-31 23:39 ` [PATCH v4 7/7] ARM: davinci_all_defconfig: remove CONFIG_DAVINCI_RESET_CLOCKS David Lechner
2018-01-02 15:10 ` [PATCH v4 0/7] ARM: davinci: convert to common clock framework Adam Ford
2018-01-02 17:10 ` David Lechner
2018-01-02 18:31 ` David Lechner
2018-01-03 16:57 ` Sekhar Nori
[not found] ` <1514763588-31560-7-git-send-email-david@lechnology.com>
2018-01-04 12:39 ` [PATCH v4 6/7] ARM: davinci: convert to common clock framework Sekhar Nori
2018-01-04 17:50 ` David Lechner
2018-01-04 19:26 ` Adam Ford
2018-01-04 21:22 ` David Lechner
2018-01-05 2:59 ` David Lechner
2018-01-05 10:42 ` Sekhar Nori
2018-01-06 1:42 ` David Lechner
2018-01-08 5:36 ` Sekhar Nori
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