From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 10/11] arm64: cputype: Add missing MIDR values for Cortex-A72 and Cortex-A75
Date: Thu, 4 Jan 2018 15:08:34 +0000 [thread overview]
Message-ID: <1515078515-13723-11-git-send-email-will.deacon@arm.com> (raw)
In-Reply-To: <1515078515-13723-1-git-send-email-will.deacon@arm.com>
Hook up MIDR values for the Cortex-A72 and Cortex-A75 CPUs, since they
will soon need MIDR matches for hardening the branch predictor.
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
arch/arm64/include/asm/cputype.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 235e77d98261..84385b94e70b 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -79,8 +79,10 @@
#define ARM_CPU_PART_AEM_V8 0xD0F
#define ARM_CPU_PART_FOUNDATION 0xD00
#define ARM_CPU_PART_CORTEX_A57 0xD07
+#define ARM_CPU_PART_CORTEX_A72 0xD08
#define ARM_CPU_PART_CORTEX_A53 0xD03
#define ARM_CPU_PART_CORTEX_A73 0xD09
+#define ARM_CPU_PART_CORTEX_A75 0xD0A
#define APM_CPU_PART_POTENZA 0x000
@@ -94,7 +96,9 @@
#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
+#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)
+#define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75)
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
--
2.1.4
next prev parent reply other threads:[~2018-01-04 15:08 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-04 15:08 [PATCH 00/11] arm64 kpti hardening and variant 2 workarounds Will Deacon
2018-01-04 15:08 ` [PATCH 01/11] arm64: use RET instruction for exiting the trampoline Will Deacon
2018-01-04 16:24 ` Ard Biesheuvel
2018-01-04 18:31 ` Will Deacon
2018-01-04 18:35 ` Ard Biesheuvel
2018-01-04 15:08 ` [PATCH 02/11] arm64: Kconfig: Reword UNMAP_KERNEL_AT_EL0 kconfig entry Will Deacon
2018-01-04 15:39 ` Christoph Hellwig
2018-01-04 15:08 ` [PATCH 03/11] arm64: Take into account ID_AA64PFR0_EL1.CSV3 Will Deacon
2018-01-04 23:15 ` Laura Abbott
2018-01-05 10:24 ` Suzuki K Poulose
2018-01-04 15:08 ` [PATCH 04/11] arm64: cpufeature: Pass capability structure to ->enable callback Will Deacon
2018-01-05 10:29 ` Suzuki K Poulose
2018-01-04 15:08 ` [PATCH 05/11] drivers/firmware: Expose psci_get_version through psci_ops structure Will Deacon
2018-01-04 16:10 ` Lorenzo Pieralisi
2018-01-04 15:08 ` [PATCH 06/11] arm64: Move post_ttbr_update_workaround to C code Will Deacon
2018-01-04 16:25 ` Ard Biesheuvel
2018-01-04 15:08 ` [PATCH 07/11] arm64: Add skeleton to harden the branch predictor against aliasing attacks Will Deacon
2018-01-04 15:08 ` [PATCH 08/11] arm64: KVM: Use per-CPU vector when BP hardening is enabled Will Deacon
2018-01-04 16:28 ` Ard Biesheuvel
2018-01-04 17:04 ` Marc Zyngier
2018-01-04 17:05 ` Ard Biesheuvel
2018-01-04 15:08 ` [PATCH 09/11] arm64: KVM: Make PSCI_VERSION a fast path Will Deacon
2018-01-04 15:08 ` Will Deacon [this message]
2018-01-04 15:08 ` [PATCH 11/11] arm64: Implement branch predictor hardening for affected Cortex-A CPUs Will Deacon
2018-01-04 16:31 ` Ard Biesheuvel
2018-01-04 17:14 ` Marc Zyngier
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