From: ckadabi@codeaurora.org (Channagoud Kadabi)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/2] dt-bindings: Documentation for qcom,llcc
Date: Thu, 25 Jan 2018 15:55:12 -0800 [thread overview]
Message-ID: <1516924513-20183-2-git-send-email-ckadabi@codeaurora.org> (raw)
In-Reply-To: <1516924513-20183-1-git-send-email-ckadabi@codeaurora.org>
Documentation for last level cache controller device tree bindings,
client bindings usage examples.
Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org>
---
.../devicetree/bindings/arm/msm/qcom,llcc.txt | 93 ++++++++++++++++++++++
1 file changed, 93 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
new file mode 100644
index 0000000..d433b0c
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
@@ -0,0 +1,93 @@
+* LLCC (Last Level Cache Controller)
+
+Properties:
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be "qcom,llcc-core"
+
+- reg:
+ Usage: required
+ Value Type: <prop-encoded-array>
+ Definition: must be addresses and sizes of the LLCC registers
+
+- llcc-bank-off:
+ Usage: required
+ Value Type: <u32 array>
+ Definition: Offsets of llcc banks from llcc base address starting from
+ LLCC bank0.
+
+- llcc-broadcast-off:
+ Usage: required
+ Value Type: <u32>
+ Definition: Offset of broadcast register from LLCC bank0 address.
+
+- #cache-cells:
+ Usage: required
+ Value Type: <u32>
+ Definition: Number of cache cells, must be 1
+
+- max-slices:
+ usage: required
+ Value Type: <u32>
+ Definition: Number of cache slices supported by hardware
+
+- status:
+ Usage: optional
+ Value type: <string>
+ Definition: Property to enable or disable the driver
+
+== llcc amon device ==
+
+Properties:
+-qcom,fg-cnt : The value of fine grained counter of activity monitor
+ block.
+
+compatible devices:
+ qcom,sdm845-llcc
+
+Example:
+
+ qcom,system-cache at 1300000 {
+ compatible = "qcom,llcc-core", "syscon", "simple-mfd";
+ reg = <0x1300000 0x50000>;
+ reg-names = "llcc_base";
+
+ llcc: qcom,sdm845-llcc {
+ compatible = "qcom,sdm845-llcc";
+ #cache-cells = <1>;
+ max-slices = <32>;
+ };
+
+ qcom,llcc-ecc {
+ compatible = "qcom,llcc-ecc";
+ };
+
+ qcom,llcc-amon {
+ compatible = "qcom,llcc-amon";
+ qcom,fg-cnt = <0x7>;
+ };
+
+ };
+
+== Client ==
+
+Properties:
+- cache-slice-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: A set of names that identify the usecase names of a client that uses
+ cache slice. These strings are used to look up the cache slice
+ entries by name.
+
+- cache-slices:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: The tuple has phandle to llcc device as the first argument and the
+ second argument is the usecase id of the client.
+For example:
+
+ video-decoder-encoder {
+ cache-slice-names = "vidsc0", "vidsc1";
+ cache-slices = <&llcc 2>, <&llcc 3>;
+ };
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2018-01-25 23:55 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-25 23:55 [PATCH 0/2] SDM845 System Cache Driver Channagoud Kadabi
2018-01-25 23:55 ` Channagoud Kadabi [this message]
2018-02-01 10:44 ` [PATCH 1/2] dt-bindings: Documentation for qcom,llcc Mark Rutland
2018-02-01 20:39 ` Channa
2018-02-02 11:05 ` Mark Rutland
2018-02-06 19:56 ` Channa
2018-02-13 14:37 ` Mark Rutland
2018-02-13 17:38 ` Channa
2018-02-01 10:48 ` Mark Rutland
2018-02-01 20:47 ` Channa
2018-02-02 11:08 ` Mark Rutland
2018-02-08 16:52 ` Matt Sealey
2018-02-09 0:24 ` Channa
2018-02-13 14:33 ` Mark Rutland
2018-01-25 23:55 ` [PATCH 2/2] drivers: soc: Add LLCC driver Channagoud Kadabi
2018-03-19 14:55 ` Jordan Crouse
2018-03-23 23:57 ` Channa
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