From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 6/9] arm64: assembler: Change order of macro arguments in phys_to_ttbr
Date: Mon, 29 Jan 2018 11:59:57 +0000 [thread overview]
Message-ID: <1517227200-20412-7-git-send-email-will.deacon@arm.com> (raw)
In-Reply-To: <1517227200-20412-1-git-send-email-will.deacon@arm.com>
Since AArch64 assembly instructions take the destination register as
their first operand, do the same thing for the phys_to_ttbr macro.
Acked-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
arch/arm64/include/asm/assembler.h | 2 +-
arch/arm64/kernel/head.S | 4 ++--
arch/arm64/kernel/hibernate-asm.S | 4 ++--
arch/arm64/kvm/hyp-init.S | 2 +-
arch/arm64/mm/proc.S | 6 +++---
5 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
index 23251eae6e8a..e4495ef96058 100644
--- a/arch/arm64/include/asm/assembler.h
+++ b/arch/arm64/include/asm/assembler.h
@@ -514,7 +514,7 @@ alternative_endif
* phys: physical address, preserved
* ttbr: returns the TTBR value
*/
- .macro phys_to_ttbr, phys, ttbr
+ .macro phys_to_ttbr, ttbr, phys
#ifdef CONFIG_ARM64_PA_BITS_52
orr \ttbr, \phys, \phys, lsr #46
and \ttbr, \ttbr, #TTBR_BADDR_MASK_52
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index ba3ab04788dc..341649c08337 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -776,8 +776,8 @@ ENTRY(__enable_mmu)
update_early_cpu_boot_status 0, x1, x2
adrp x1, idmap_pg_dir
adrp x2, swapper_pg_dir
- phys_to_ttbr x1, x3
- phys_to_ttbr x2, x4
+ phys_to_ttbr x3, x1
+ phys_to_ttbr x4, x2
msr ttbr0_el1, x3 // load TTBR0
msr ttbr1_el1, x4 // load TTBR1
isb
diff --git a/arch/arm64/kernel/hibernate-asm.S b/arch/arm64/kernel/hibernate-asm.S
index 84f5d52fddda..dd14ab8c9f72 100644
--- a/arch/arm64/kernel/hibernate-asm.S
+++ b/arch/arm64/kernel/hibernate-asm.S
@@ -34,12 +34,12 @@
* each stage of the walk.
*/
.macro break_before_make_ttbr_switch zero_page, page_table, tmp
- phys_to_ttbr \zero_page, \tmp
+ phys_to_ttbr \tmp, \zero_page
msr ttbr1_el1, \tmp
isb
tlbi vmalle1
dsb nsh
- phys_to_ttbr \page_table, \tmp
+ phys_to_ttbr \tmp, \page_table
msr ttbr1_el1, \tmp
isb
.endm
diff --git a/arch/arm64/kvm/hyp-init.S b/arch/arm64/kvm/hyp-init.S
index e086c6eff8c6..5aa9ccf6db99 100644
--- a/arch/arm64/kvm/hyp-init.S
+++ b/arch/arm64/kvm/hyp-init.S
@@ -63,7 +63,7 @@ __do_hyp_init:
cmp x0, #HVC_STUB_HCALL_NR
b.lo __kvm_handle_stub_hvc
- phys_to_ttbr x0, x4
+ phys_to_ttbr x4, x0
msr ttbr0_el2, x4
mrs x4, tcr_el1
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index ab8660eb55ca..cfd22ba9b510 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -153,7 +153,7 @@ ENDPROC(cpu_do_resume)
ENTRY(cpu_do_switch_mm)
mrs x2, ttbr1_el1
mmid x1, x1 // get mm->context.id
- phys_to_ttbr x0, x3
+ phys_to_ttbr x3, x0
#ifdef CONFIG_ARM64_SW_TTBR0_PAN
bfi x3, x1, #48, #16 // set the ASID field in TTBR0
#endif
@@ -169,7 +169,7 @@ ENDPROC(cpu_do_switch_mm)
.macro __idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
adrp \tmp1, empty_zero_page
- phys_to_ttbr \tmp1, \tmp2
+ phys_to_ttbr \tmp2, \tmp1
msr ttbr1_el1, \tmp2
isb
tlbi vmalle1
@@ -188,7 +188,7 @@ ENTRY(idmap_cpu_replace_ttbr1)
__idmap_cpu_set_reserved_ttbr1 x1, x3
- phys_to_ttbr x0, x3
+ phys_to_ttbr x3, x0
msr ttbr1_el1, x3
isb
--
2.1.4
next prev parent reply other threads:[~2018-01-29 11:59 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-29 11:59 [PATCH v2 0/9] Fix kpti-enabled kernels for Cavium ThunderX Will Deacon
2018-01-29 11:59 ` [PATCH v2 1/9] arm64: Add software workaround for Falkor erratum 1041 Will Deacon
2018-01-29 11:59 ` [PATCH v2 2/9] arm64: kpti: Make use of nG dependent on arm64_kernel_unmapped_at_el0() Will Deacon
2018-01-29 11:59 ` [PATCH v2 3/9] arm64: mm: Permit transitioning from Global to Non-Global without BBM Will Deacon
2018-01-29 11:59 ` [PATCH v2 4/9] arm64: kpti: Add ->enable callback to remap swapper using nG mappings Will Deacon
2018-01-30 10:30 ` Will Deacon
2018-01-29 11:59 ` [PATCH v2 5/9] arm64: Force KPTI to be disabled on Cavium ThunderX Will Deacon
2018-01-29 11:59 ` Will Deacon [this message]
2018-01-29 11:59 ` [PATCH v2 7/9] arm64: entry: Reword comment about post_ttbr_update_workaround Will Deacon
2018-02-03 11:15 ` Ard Biesheuvel
2018-02-05 16:41 ` Will Deacon
2018-01-29 11:59 ` [PATCH v2 8/9] arm64: assembler: Align phys_to_pte with pte_to_phys Will Deacon
2018-01-29 12:00 ` [PATCH v2 9/9] arm64: idmap: Use "awx" flags for .idmap.text .pushsection directives Will Deacon
2018-02-03 11:36 ` [PATCH v2 0/9] Fix kpti-enabled kernels for Cavium ThunderX Ard Biesheuvel
2018-02-05 16:41 ` Will Deacon
2018-02-05 19:21 ` Ard Biesheuvel
2018-02-06 22:31 ` Catalin Marinas
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