[PATCH 1/2] arm64: dts: fsl: imx8mq: add watchdog devices

[PATCH 1/2] arm64: dts: fsl: imx8mq: add watchdog devices

[Baruch Siach]

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
 arch/arm64/boot/dts/freescale/imx8mq.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 50ed302d299a..740457e2a0bf 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -250,6 +250,30 @@
 				              "clk_ext1", "clk_ext2",
 				              "clk_ext3", "clk_ext4";
 			};
+
+			wdog1: wdog at 30280000 {
+				compatible = "fsl,imx21-wdt";
+				reg = <0x30280000 0x10000>;
+				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
+				status = "disabled";
+			};
+
+			wdog2: wdog at 30290000 {
+				compatible = "fsl,imx21-wdt";
+				reg = <0x30290000 0x10000>;
+				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
+				status = "disabled";
+			};
+
+			wdog3: wdog at 302a0000 {
+				compatible = "fsl,imx21-wdt";
+				reg = <0x302a0000 0x10000>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
+				status = "disabled";
+			};
 		};
 
 		bus at 30400000 { /* AIPS2 */
-- 
2.15.1

[PATCH 2/2] arm64: dts: fsl: imx8mq-evk: enable watchdog

[Baruch Siach]

The external nWDOG signal connects to the EVK board reset circuit.

Tested on the i.MX8MQ EVK rev B3.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
 arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index c0e5ee5d6243..757ba226a2fc 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -170,6 +170,13 @@
 	status = "okay";
 };
 
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
 &iomuxc {
 	pinctrl_fec1_mdc: fec1mdcgrp {
 		pinmux = <MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC>;
@@ -402,4 +409,12 @@
 		bias-pull-up;
 		input-schmitt-enable;
 	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B>;
+		drive-strength = <6>;
+		slew-rate = <0>;
+		bias-pull-up;
+		input-schmitt-enable;
+	};
 };
-- 
2.15.1

[PATCH 1/2] arm64: dts: fsl: imx8mq: add watchdog devices

[Fabio Estevam]

Hi Baruch,

On Mon, Feb 5, 2018 at 5:45 AM, Baruch Siach <baruch@tkos.co.il> wrote:
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> ---
>  arch/arm64/boot/dts/freescale/imx8mq.dtsi | 24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 50ed302d299a..740457e2a0bf 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -250,6 +250,30 @@
>                                               "clk_ext1", "clk_ext2",
>                                               "clk_ext3", "clk_ext4";
>                         };
> +
> +                       wdog1: wdog at 30280000 {
> +                               compatible = "fsl,imx21-wdt";

Please use:

compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; instead.

This is the preferred way as it allows us to apply specific mx8qm
fixes if needed.

Thanks

[PATCH 2/2] arm64: dts: fsl: imx8mq-evk: enable watchdog

[Lucas Stach]

Am Montag, den 05.02.2018, 09:45 +0200 schrieb Baruch Siach:
> The external nWDOG signal connects to the EVK board reset circuit.
> 
> Tested on the i.MX8MQ EVK rev B3.
> 
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> ---
> ?arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 15 +++++++++++++++
> ?1 file changed, 15 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> index c0e5ee5d6243..757ba226a2fc 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> @@ -170,6 +170,13 @@
> ?	status = "okay";
> ?};
> ?
> +&wdog1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_wdog>;
> +	fsl,ext-reset-output;
> +	status = "okay";
> +};
> +
> ?&iomuxc {
> ?	pinctrl_fec1_mdc: fec1mdcgrp {
> ?		pinmux = <MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC>;
> @@ -402,4 +409,12 @@
> ?		bias-pull-up;
> ?		input-schmitt-enable;
> ?	};
> +
> +	pinctrl_wdog: wdoggrp {
> +		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B>;
> +		drive-strength = <6>;
> +		slew-rate = <0>;
> +		bias-pull-up;
> +		input-schmitt-enable;

This might be a plain copy of the downstream pinctrl, but the watchdog
pin being an output, does it really make sense to enable the schmitt-
trigger?

Regards,
Lucas

[PATCH 1/2] arm64: dts: fsl: imx8mq: add watchdog devices

[Lucas Stach]

Am Montag, den 05.02.2018, 09:45 +0200 schrieb Baruch Siach:
> > Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> ---
> ?arch/arm64/boot/dts/freescale/imx8mq.dtsi | 24 ++++++++++++++++++++++++
> ?1 file changed, 24 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 50ed302d299a..740457e2a0bf 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -250,6 +250,30 @@
> > ?				??????????????"clk_ext1", "clk_ext2",
> > ?				??????????????"clk_ext3", "clk_ext4";
> > ?			};
> +
> +			wdog1: wdog at 30280000 {

watchdog@, please.

Otherwise looks good to me, so with this fixed:
Reviewed-by: Lucas Stach <l.stach@pengutronix.de

> +				compatible = "fsl,imx21-wdt";
> > +				reg = <0x30280000 0x10000>;
> > +				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
> > +				status = "disabled";
> > +			};
> +
> > > +			wdog2: wdog at 30290000 {
> > +				compatible = "fsl,imx21-wdt";
> > +				reg = <0x30290000 0x10000>;
> > +				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
> > +				status = "disabled";
> > +			};
> +
> > > +			wdog3: wdog at 302a0000 {
> > +				compatible = "fsl,imx21-wdt";
> > +				reg = <0x302a0000 0x10000>;
> > +				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
> > +				status = "disabled";
> > +			};
> > ?		};
> ?
> > ?		bus at 30400000 { /* AIPS2 */