From: cpandya@codeaurora.org (Chintan Pandya)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 2/4] arm64: tlbflush: Introduce __flush_tlb_kernel_pgtable
Date: Tue, 27 Mar 2018 18:54:58 +0530 [thread overview]
Message-ID: <1522157100-16879-3-git-send-email-cpandya@codeaurora.org> (raw)
In-Reply-To: <1522157100-16879-1-git-send-email-cpandya@codeaurora.org>
Add an interface to invalidate intermediate page tables
from TLB for kernel.
Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>
---
Introduced in v5
arch/arm64/include/asm/tlbflush.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index 9e82dd7..6a4816d 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -209,6 +209,12 @@ static inline void __flush_tlb_pgtable(struct mm_struct *mm,
dsb(ish);
}
+static inline void __flush_tlb_kernel_pgtable(unsigned long addr)
+{
+ addr >>= 12;
+ __tlbi(vaae1is, addr);
+ dsb(ish);
+}
#endif
#endif
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation
Center, Inc., is a member of Code Aurora Forum, a Linux Foundation
Collaborative Project
next prev parent reply other threads:[~2018-03-27 13:24 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-27 13:24 [PATCH v5 0/4] Fix issues with huge mapping in ioremap for ARM64 Chintan Pandya
2018-03-27 13:24 ` [PATCH v5 1/4] ioremap: Update pgtable free interfaces with addr Chintan Pandya
2018-03-28 11:50 ` kbuild test robot
2018-03-28 12:22 ` Chintan Pandya
2018-03-28 13:12 ` kbuild test robot
2018-03-27 13:24 ` Chintan Pandya [this message]
2018-03-27 13:24 ` [PATCH v5 3/4] arm64: Implement page table free interfaces Chintan Pandya
2018-03-27 18:00 ` Will Deacon
2018-03-28 6:59 ` Chintan Pandya
2018-03-27 13:25 ` [PATCH v5 4/4] Revert "arm64: Enforce BBM for huge IO/VMAP mappings" Chintan Pandya
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