From mboxrd@z Thu Jan 1 00:00:00 1970 From: cpandya@codeaurora.org (Chintan Pandya) Date: Tue, 27 Mar 2018 18:54:58 +0530 Subject: [PATCH v5 2/4] arm64: tlbflush: Introduce __flush_tlb_kernel_pgtable In-Reply-To: <1522157100-16879-1-git-send-email-cpandya@codeaurora.org> References: <1522157100-16879-1-git-send-email-cpandya@codeaurora.org> Message-ID: <1522157100-16879-3-git-send-email-cpandya@codeaurora.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Add an interface to invalidate intermediate page tables from TLB for kernel. Signed-off-by: Chintan Pandya --- Introduced in v5 arch/arm64/include/asm/tlbflush.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index 9e82dd7..6a4816d 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -209,6 +209,12 @@ static inline void __flush_tlb_pgtable(struct mm_struct *mm, dsb(ish); } +static inline void __flush_tlb_kernel_pgtable(unsigned long addr) +{ + addr >>= 12; + __tlbi(vaae1is, addr); + dsb(ish); +} #endif #endif -- Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project