From mboxrd@z Thu Jan 1 00:00:00 1970 From: michel.pollet@bp.renesas.com (Michel Pollet) Date: Tue, 17 Apr 2018 12:04:19 +0100 Subject: [PATCH v5 4/6] ARM: dts: Renesas RZ/N1 SoC base device tree file In-Reply-To: <1523963101-56725-1-git-send-email-michel.pollet@bp.renesas.com> References: <1523963101-56725-1-git-send-email-michel.pollet@bp.renesas.com> Message-ID: <1523963101-56725-5-git-send-email-michel.pollet@bp.renesas.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare bone support. This currently only handles generic parts (gic, architected timer) and a UART. For simplicity sake, this also relies on the bootloader to set the pinctrl and clocks. Signed-off-by: Michel Pollet --- arch/arm/boot/dts/r9a06g032.dtsi | 89 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) create mode 100644 arch/arm/boot/dts/r9a06g032.dtsi diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi new file mode 100644 index 0000000..23c56d7 --- /dev/null +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032) + * + * Copyright (C) 2018 Renesas Electronics Europe Limited + * + */ + +#include + +/ { + compatible = "renesas,r9a06g032", "renesas,rzn1"; + #address-cells = <1>; + #size-cells = <1>; + + clkuarts: clkuarts { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <47619047>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0>; + }; + + cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <1>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + ranges; + + reboot at 4000c120 { + compatible = "renesas,r9a06g032-reboot", + "renesas,rzn1-reboot"; + reg = <0x4000c120 4>, + <0x4000c198 4>; + }; + + uart0: serial at 40060000 { + compatible = "snps,dw-apb-uart"; + reg = <0x40060000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&clkuarts>; + clock-names = "baudclk"; + status = "disabled"; + }; + + gic: gic at 44101000 { + compatible = "arm,cortex-a7-gic", "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x44101000 0x1000>, /* Distributer */ + <0x44102000 0x2000>, /* CPU interface */ + <0x44104000 0x2000>, /* Virt interface control */ + <0x44106000 0x2000>; /* Virt CPU interface */ + interrupts = + ; + }; + }; + + timer { + compatible = "arm,cortex-a7-timer", + "arm,armv7-timer"; + interrupt-parent = <&gic>; + arm,cpu-registers-not-fw-configured; + always-on; + interrupts = + , + , + , + ; + }; +}; -- 2.7.4