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From: ryder.lee@mediatek.com (Ryder Lee)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] clk: mediatek: correct the clocks for MT2701 HDMI PHY module
Date: Tue, 17 Apr 2018 20:35:05 +0800	[thread overview]
Message-ID: <1523968505.23886.2.camel@mtkswgap22> (raw)
In-Reply-To: <152389649546.51482.15378110712126175925@swboyd.mtv.corp.google.com>

On Mon, 2018-04-16 at 09:34 -0700, Stephen Boyd wrote:
> Quoting Ryder Lee (2018-04-15 19:31:58)
> > The hdmitx_dig_cts clock signal is not a child of clk26m,
> > and the actual output of the PLL block is derived from
> > the tvdpll via a configurable PLL post-divider.
> > 
> > It is used as the PLL reference input to the HDMI PHY module.
> > 
> > Signed-off-by: Chunhui Dai <chunhui.dai@mediatek.com>
> > Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
> 
> Any sort of Fixes: tag here?
> 

Yes, I've already sent a new one.

Thanks

      reply	other threads:[~2018-04-17 12:35 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-16  2:31 [PATCH] clk: mediatek: correct the clocks for MT2701 HDMI PHY module Ryder Lee
2018-04-16 16:34 ` Stephen Boyd
2018-04-17 12:35   ` Ryder Lee [this message]

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