From mboxrd@z Thu Jan 1 00:00:00 1970 From: cpandya@codeaurora.org (Chintan Pandya) Date: Thu, 24 May 2018 19:27:28 +0530 Subject: [PATCH v10 2/4] arm64: tlbflush: Introduce __flush_tlb_kernel_pgtable In-Reply-To: <1527170250-5291-1-git-send-email-cpandya@codeaurora.org> References: <1527170250-5291-1-git-send-email-cpandya@codeaurora.org> Message-ID: <1527170250-5291-3-git-send-email-cpandya@codeaurora.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Add an interface to invalidate intermediate page tables from TLB for kernel. Signed-off-by: Chintan Pandya --- arch/arm64/include/asm/tlbflush.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index dfc61d7..a4a1901 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -218,6 +218,13 @@ static inline void __flush_tlb_pgtable(struct mm_struct *mm, dsb(ish); } +static inline void __flush_tlb_kernel_pgtable(unsigned long kaddr) +{ + unsigned long addr = __TLBI_VADDR(kaddr, 0); + + __tlbi(vaae1is, addr); + dsb(ish); +} #endif #endif -- Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project