* [PATCH v9 2/5] clk: imx: add fractional PLL output clock
[not found] <1537785597-26499-1-git-send-email-abel.vesa@nxp.com>
@ 2018-09-24 10:39 ` Abel Vesa
2018-10-17 19:59 ` Stephen Boyd
2018-09-24 10:39 ` [PATCH v9 3/5] clk: imx: add SCCG PLL type Abel Vesa
` (2 subsequent siblings)
3 siblings, 1 reply; 23+ messages in thread
From: Abel Vesa @ 2018-09-24 10:39 UTC (permalink / raw)
To: linux-arm-kernel
From: Lucas Stach <l.stach@pengutronix.de>
This is a new clock type introduced on i.MX8.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-frac-pll.c | 215 +++++++++++++++++++++++++++++++++++++++++
drivers/clk/imx/clk.h | 3 +
3 files changed, 219 insertions(+)
create mode 100644 drivers/clk/imx/clk-frac-pll.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 8c3baa7..4893c1f 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -6,6 +6,7 @@ obj-y += \
clk-cpu.o \
clk-fixup-div.o \
clk-fixup-mux.o \
+ clk-frac-pll.o \
clk-gate-exclusive.o \
clk-gate2.o \
clk-pllv1.o \
diff --git a/drivers/clk/imx/clk-frac-pll.c b/drivers/clk/imx/clk-frac-pll.c
new file mode 100644
index 0000000..030df76
--- /dev/null
+++ b/drivers/clk/imx/clk-frac-pll.c
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018 NXP.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/jiffies.h>
+#include <linux/slab.h>
+#include <linux/bitfield.h>
+
+#include "clk.h"
+
+#define PLL_CFG0 0x0
+#define PLL_CFG1 0x4
+
+#define PLL_LOCK_STATUS BIT(31)
+#define PLL_PD_MASK BIT(19)
+#define PLL_BYPASS_MASK BIT(14)
+#define PLL_NEWDIV_VAL BIT(12)
+#define PLL_NEWDIV_ACK BIT(11)
+#define PLL_FRAC_DIV_MASK GENMASK(30, 7)
+#define PLL_INT_DIV_MASK GENMASK(6, 0)
+#define PLL_OUTPUT_DIV_MASK GENMASK(4, 0)
+#define PLL_FRAC_DENOM 0x1000000
+
+#define PLL_FRAC_LOCK_TIMEOUT 10000
+#define PLL_FRAC_ACK_TIMEOUT 500000
+
+struct clk_frac_pll {
+ struct clk_hw hw;
+ void __iomem *base;
+};
+
+#define to_clk_frac_pll(_hw) container_of(_hw, struct clk_frac_pll, hw)
+
+static int clk_wait_lock(struct clk_frac_pll *pll)
+{
+ u32 val;
+
+ return readl_poll_timeout(pll->base, val, val & PLL_LOCK_STATUS, 0,
+ PLL_FRAC_LOCK_TIMEOUT);
+}
+
+static int clk_wait_ack(struct clk_frac_pll *pll)
+{
+ u32 val;
+
+ /* return directly if the pll is in powerdown or in bypass */
+ if (readl_relaxed(pll->base) & (PLL_PD_MASK | PLL_BYPASS_MASK))
+ return 0;
+
+ /* Wait for the pll's divfi and divff to be reloaded */
+ return readl_poll_timeout(pll->base, val, val & PLL_NEWDIV_ACK, 0,
+ PLL_FRAC_ACK_TIMEOUT);
+}
+
+static int clk_pll_prepare(struct clk_hw *hw)
+{
+ struct clk_frac_pll *pll = to_clk_frac_pll(hw);
+ u32 val;
+
+ val = readl_relaxed(pll->base + PLL_CFG0);
+ val &= ~PLL_PD_MASK;
+ writel_relaxed(val, pll->base + PLL_CFG0);
+
+ return clk_wait_lock(pll);
+}
+
+static void clk_pll_unprepare(struct clk_hw *hw)
+{
+ struct clk_frac_pll *pll = to_clk_frac_pll(hw);
+ u32 val;
+
+ val = readl_relaxed(pll->base + PLL_CFG0);
+ val |= PLL_PD_MASK;
+ writel_relaxed(val, pll->base + PLL_CFG0);
+}
+
+static int clk_pll_is_prepared(struct clk_hw *hw)
+{
+ struct clk_frac_pll *pll = to_clk_frac_pll(hw);
+ u32 val;
+
+ val = readl_relaxed(pll->base + PLL_CFG0);
+ return (val & PLL_PD_MASK) ? 0 : 1;
+}
+
+static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_frac_pll *pll = to_clk_frac_pll(hw);
+ u32 val, divff, divfi, divq;
+ u64 temp64;
+
+ val = readl_relaxed(pll->base + PLL_CFG0);
+ divq = ((val & PLL_OUTPUT_DIV_MASK) + 1) * 2;
+ val = readl_relaxed(pll->base + PLL_CFG1);
+ divff = FIELD_GET(PLL_FRAC_DIV_MASK, val);
+ divfi = (val & PLL_INT_DIV_MASK);
+
+ temp64 = (u64)parent_rate * 8;
+ temp64 *= divff;
+ do_div(temp64, PLL_FRAC_DENOM);
+ temp64 /= divq;
+
+ return parent_rate * 8 * (divfi + 1) / divq + (unsigned long)temp64;
+}
+
+static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ unsigned long parent_rate = *prate;
+ u32 divff, divfi;
+ u64 temp64;
+
+ parent_rate *= 8;
+ rate *= 2;
+ divfi = rate / parent_rate;
+ temp64 = (u64)(rate - divfi * parent_rate);
+ temp64 *= PLL_FRAC_DENOM;
+ do_div(temp64, parent_rate);
+ divff = temp64;
+
+ temp64 = (u64)parent_rate;
+ temp64 *= divff;
+ do_div(temp64, PLL_FRAC_DENOM);
+
+ return (parent_rate * divfi + (unsigned long)temp64) / 2;
+}
+
+/*
+ * To simplify the clock calculation, we can keep the 'PLL_OUTPUT_VAL' at zero
+ * (means the PLL output will be divided by 2). So the PLL output can use
+ * the below formula:
+ * pllout = parent_rate * 8 / 2 * DIVF_VAL;
+ * where DIVF_VAL = 1 + DIVFI + DIVFF / 2^24.
+ */
+static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_frac_pll *pll = to_clk_frac_pll(hw);
+ u32 val, divfi, divff;
+ u64 temp64;
+ int ret;
+
+ parent_rate *= 8;
+ rate *= 2;
+ divfi = rate / parent_rate;
+ temp64 = (u64) (rate - divfi * parent_rate);
+ temp64 *= PLL_FRAC_DENOM;
+ do_div(temp64, parent_rate);
+ divff = temp64;
+
+ val = readl_relaxed(pll->base + PLL_CFG1);
+ val &= ~(PLL_FRAC_DIV_MASK | PLL_INT_DIV_MASK);
+ val |= ((divff << 7) | (divfi - 1));
+ writel_relaxed(val, pll->base + PLL_CFG1);
+
+ val = readl_relaxed(pll->base + PLL_CFG0);
+ val &= ~0x1f;
+ writel_relaxed(val, pll->base + PLL_CFG0);
+
+ /* Set the NEV_DIV_VAL to reload the DIVFI and DIVFF */
+ val = readl_relaxed(pll->base + PLL_CFG0);
+ val |= PLL_NEWDIV_VAL;
+ writel_relaxed(val, pll->base + PLL_CFG0);
+
+ ret = clk_wait_ack(pll);
+
+ /* clear the NEV_DIV_VAL */
+ val = readl_relaxed(pll->base + PLL_CFG0);
+ val &= ~PLL_NEWDIV_VAL;
+ writel_relaxed(val, pll->base + PLL_CFG0);
+
+ return ret;
+}
+
+static const struct clk_ops clk_frac_pll_ops = {
+ .prepare = clk_pll_prepare,
+ .unprepare = clk_pll_unprepare,
+ .is_prepared = clk_pll_is_prepared,
+ .recalc_rate = clk_pll_recalc_rate,
+ .round_rate = clk_pll_round_rate,
+ .set_rate = clk_pll_set_rate,
+};
+
+struct clk *imx_clk_frac_pll(const char *name, const char *parent_name,
+ void __iomem *base)
+{
+ struct clk_init_data init;
+ struct clk_frac_pll *pll;
+ struct clk *clk;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ pll->base = base;
+ init.name = name;
+ init.ops = &clk_frac_pll_ops;
+ init.flags = 0;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+ pll->hw.init = &init;
+
+ clk = clk_register(NULL, &pll->hw);
+ if (IS_ERR(clk))
+ kfree(pll);
+
+ return clk;
+}
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 8076ec0..13daf1c 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -27,6 +27,9 @@ struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name,
struct clk *imx_clk_pllv2(const char *name, const char *parent,
void __iomem *base);
+struct clk *imx_clk_frac_pll(const char *name, const char *parent_name,
+ void __iomem *base);
+
enum imx_pllv3_type {
IMX_PLLV3_GENERIC,
IMX_PLLV3_SYS,
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v9 3/5] clk: imx: add SCCG PLL type
[not found] <1537785597-26499-1-git-send-email-abel.vesa@nxp.com>
2018-09-24 10:39 ` [PATCH v9 2/5] clk: imx: add fractional PLL output clock Abel Vesa
@ 2018-09-24 10:39 ` Abel Vesa
2018-10-17 19:55 ` Stephen Boyd
2018-09-24 10:39 ` [PATCH v9 4/5] clk: imx: add imx composite clock Abel Vesa
2018-09-24 10:39 ` [PATCH v9 5/5] clk: imx: add clock driver for i.MX8MQ CCM Abel Vesa
3 siblings, 1 reply; 23+ messages in thread
From: Abel Vesa @ 2018-09-24 10:39 UTC (permalink / raw)
To: linux-arm-kernel
From: Lucas Stach <l.stach@pengutronix.de>
The SCCG is a new PLL type introduced on i.MX8. Add support for this.
The driver currently misses the PLL lock check, as the preliminary
documentation mentions lock configurations, but is quiet about where
to find the actual lock status signal.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
drivers/clk/imx/Makefile | 3 +-
drivers/clk/imx/clk-sccg-pll.c | 237 +++++++++++++++++++++++++++++++++++++++++
drivers/clk/imx/clk.h | 9 ++
3 files changed, 248 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/imx/clk-sccg-pll.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 4893c1f..b87513c 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -12,7 +12,8 @@ obj-y += \
clk-pllv1.o \
clk-pllv2.o \
clk-pllv3.o \
- clk-pfd.o
+ clk-pfd.o \
+ clk-sccg-pll.o
obj-$(CONFIG_SOC_IMX1) += clk-imx1.o
obj-$(CONFIG_SOC_IMX21) += clk-imx21.o
diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pll.c
new file mode 100644
index 0000000..a9837fa
--- /dev/null
+++ b/drivers/clk/imx/clk-sccg-pll.c
@@ -0,0 +1,237 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2018 NXP.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/bitfield.h>
+
+#include "clk.h"
+
+/* PLL CFGs */
+#define PLL_CFG0 0x0
+#define PLL_CFG1 0x4
+#define PLL_CFG2 0x8
+
+#define PLL_DIVF1_MASK GENMASK(18, 13)
+#define PLL_DIVF2_MASK GENMASK(12, 7)
+#define PLL_DIVR1_MASK GENMASK(27, 25)
+#define PLL_DIVR2_MASK GENMASK(24, 19)
+#define PLL_REF_MASK GENMASK(2, 0)
+
+#define PLL_LOCK_MASK BIT(31)
+#define PLL_PD_MASK BIT(7)
+
+#define OSC_25M 25000000
+#define OSC_27M 27000000
+
+#define PLL_SCCG_LOCK_TIMEOUT 70
+
+struct clk_sccg_pll {
+ struct clk_hw hw;
+ void __iomem *base;
+};
+
+#define to_clk_sccg_pll(_hw) container_of(_hw, struct clk_sccg_pll, hw)
+
+static int clk_pll_wait_lock(struct clk_sccg_pll *pll)
+{
+ u32 val;
+
+ return readl_poll_timeout(pll->base, val, val & PLL_LOCK_MASK, 0,
+ PLL_SCCG_LOCK_TIMEOUT);
+}
+
+static int clk_pll1_is_prepared(struct clk_hw *hw)
+{
+ struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
+ u32 val;
+
+ val = readl_relaxed(pll->base + PLL_CFG0);
+ return (val & PLL_PD_MASK) ? 0 : 1;
+}
+
+static unsigned long clk_pll1_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
+ u32 val, divf;
+
+ val = readl_relaxed(pll->base + PLL_CFG2);
+ divf = FIELD_GET(PLL_DIVF1_MASK, val);
+
+ return parent_rate * 2 * (divf + 1);
+}
+
+static long clk_pll1_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ unsigned long parent_rate = *prate;
+ u32 div;
+
+ div = rate / (parent_rate * 2);
+
+ return parent_rate * div * 2;
+}
+
+static int clk_pll1_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
+ u32 val;
+ u32 divf;
+
+ divf = rate / (parent_rate * 2);
+
+ val = readl_relaxed(pll->base + PLL_CFG2);
+ val &= ~PLL_DIVF1_MASK;
+ val |= FIELD_PREP(PLL_DIVF1_MASK, divf - 1);
+ writel_relaxed(val, pll->base + PLL_CFG2);
+
+ return clk_pll_wait_lock(pll);
+}
+
+static int clk_pll1_prepare(struct clk_hw *hw)
+{
+ struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
+ u32 val;
+
+ val = readl_relaxed(pll->base + PLL_CFG0);
+ val &= ~PLL_PD_MASK;
+ writel_relaxed(val, pll->base + PLL_CFG0);
+
+ return clk_pll_wait_lock(pll);
+}
+
+static void clk_pll1_unprepare(struct clk_hw *hw)
+{
+ struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
+ u32 val;
+
+ val = readl_relaxed(pll->base + PLL_CFG0);
+ val |= PLL_PD_MASK;
+ writel_relaxed(val, pll->base + PLL_CFG0);
+
+}
+
+static unsigned long clk_pll2_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
+ u32 val, ref, divr1, divf1, divr2, divf2;
+ u64 temp64;
+
+ val = readl_relaxed(pll->base + PLL_CFG0);
+ switch (FIELD_GET(PLL_REF_MASK, val)) {
+ case 0:
+ ref = OSC_25M;
+ break;
+ case 1:
+ ref = OSC_27M;
+ break;
+ default:
+ ref = OSC_25M;
+ break;
+ }
+
+ val = readl_relaxed(pll->base + PLL_CFG2);
+ divr1 = FIELD_GET(PLL_DIVR1_MASK, val);
+ divr2 = FIELD_GET(PLL_DIVR2_MASK, val);
+ divf1 = FIELD_GET(PLL_DIVF1_MASK, val);
+ divf2 = FIELD_GET(PLL_DIVF2_MASK, val);
+
+ temp64 = ref * 2;
+ temp64 *= (divf1 + 1) * (divf2 + 1);
+
+ do_div(temp64, (divr1 + 1) * (divr2 + 1));
+
+ return (unsigned long)temp64;
+}
+
+static long clk_pll2_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ u32 div;
+ unsigned long parent_rate = *prate;
+
+ div = rate / (parent_rate);
+
+ return parent_rate * div;
+}
+
+static int clk_pll2_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ u32 val;
+ u32 divf;
+ struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
+
+ divf = rate / (parent_rate);
+
+ val = readl_relaxed(pll->base + PLL_CFG2);
+ val &= ~PLL_DIVF2_MASK;
+ val |= FIELD_PREP(PLL_DIVF2_MASK, divf - 1);
+ writel_relaxed(val, pll->base + PLL_CFG2);
+
+ return clk_pll_wait_lock(pll);
+}
+
+static const struct clk_ops clk_sccg_pll1_ops = {
+ .is_prepared = clk_pll1_is_prepared,
+ .recalc_rate = clk_pll1_recalc_rate,
+ .round_rate = clk_pll1_round_rate,
+ .set_rate = clk_pll1_set_rate,
+};
+
+static const struct clk_ops clk_sccg_pll2_ops = {
+ .prepare = clk_pll1_prepare,
+ .unprepare = clk_pll1_unprepare,
+ .recalc_rate = clk_pll2_recalc_rate,
+ .round_rate = clk_pll2_round_rate,
+ .set_rate = clk_pll2_set_rate,
+};
+
+struct clk *imx_clk_sccg_pll(const char *name,
+ const char *parent_name,
+ void __iomem *base,
+ enum imx_sccg_pll_type pll_type)
+{
+ struct clk_sccg_pll *pll;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ pll->base = base;
+ init.name = name;
+ switch (pll_type) {
+ case SCCG_PLL1:
+ init.ops = &clk_sccg_pll1_ops;
+ break;
+ case SCCG_PLL2:
+ init.ops = &clk_sccg_pll2_ops;
+ break;
+ default:
+ kfree(pll);
+ return ERR_PTR(-EINVAL);
+ }
+
+ init.flags = 0;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+ pll->hw.init = &init;
+
+ clk = clk_register(NULL, &pll->hw);
+ if (IS_ERR(clk))
+ kfree(pll);
+
+ return clk;
+}
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 13daf1c..12b3fd6 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -21,6 +21,11 @@ enum imx_pllv1_type {
IMX_PLLV1_IMX35,
};
+enum imx_sccg_pll_type {
+ SCCG_PLL1,
+ SCCG_PLL2,
+};
+
struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name,
const char *parent, void __iomem *base);
@@ -30,6 +35,10 @@ struct clk *imx_clk_pllv2(const char *name, const char *parent,
struct clk *imx_clk_frac_pll(const char *name, const char *parent_name,
void __iomem *base);
+struct clk *imx_clk_sccg_pll(const char *name, const char *parent_name,
+ void __iomem *base,
+ enum imx_sccg_pll_type pll_type);
+
enum imx_pllv3_type {
IMX_PLLV3_GENERIC,
IMX_PLLV3_SYS,
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v9 4/5] clk: imx: add imx composite clock
[not found] <1537785597-26499-1-git-send-email-abel.vesa@nxp.com>
2018-09-24 10:39 ` [PATCH v9 2/5] clk: imx: add fractional PLL output clock Abel Vesa
2018-09-24 10:39 ` [PATCH v9 3/5] clk: imx: add SCCG PLL type Abel Vesa
@ 2018-09-24 10:39 ` Abel Vesa
2018-09-25 16:42 ` Fabio Estevam
2018-10-17 19:51 ` Stephen Boyd
2018-09-24 10:39 ` [PATCH v9 5/5] clk: imx: add clock driver for i.MX8MQ CCM Abel Vesa
3 siblings, 2 replies; 23+ messages in thread
From: Abel Vesa @ 2018-09-24 10:39 UTC (permalink / raw)
To: linux-arm-kernel
Since a lot of clocks on imx8 are formed by a mux, gate, predivider and
divider, the idea here is to combine all of those into one composite clock,
but we need to deal with both predivider and divider at the same time and
therefore we add the imx_clk_composite_divider_ops and register
the composite clock with those.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Suggested-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-composite.c | 181 ++++++++++++++++++++++++++++++++++++++++
drivers/clk/imx/clk.h | 14 ++++
3 files changed, 196 insertions(+)
create mode 100644 drivers/clk/imx/clk-composite.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index b87513c..4fabb0a 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -3,6 +3,7 @@
obj-y += \
clk.o \
clk-busy.o \
+ clk-composite.o \
clk-cpu.o \
clk-fixup-div.o \
clk-fixup-mux.o \
diff --git a/drivers/clk/imx/clk-composite.c b/drivers/clk/imx/clk-composite.c
new file mode 100644
index 0000000..4b03107
--- /dev/null
+++ b/drivers/clk/imx/clk-composite.c
@@ -0,0 +1,181 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <linux/errno.h>
+#include <linux/slab.h>
+#include <linux/clk-provider.h>
+#include <linux/clk.h>
+
+#include "clk.h"
+
+#define PCG_PREDIV_SHIFT 16
+#define PCG_PREDIV_WIDTH 3
+#define PCG_PREDIV_MAX 8
+
+#define PCG_DIV_SHIFT 0
+#define PCG_DIV_WIDTH 6
+#define PCG_DIV_MAX 64
+
+#define PCG_PCS_SHIFT 24
+#define PCG_PCS_MASK 0x7
+
+#define PCG_CGC_SHIFT 28
+
+static unsigned long imx_clk_composite_divider_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned long prediv_rate;
+ unsigned int prediv_value;
+ unsigned int div_value;
+
+ prediv_value = clk_readl(divider->reg) >> divider->shift;
+ prediv_value &= clk_div_mask(divider->width);
+
+ prediv_rate = divider_recalc_rate(hw, parent_rate, prediv_value,
+ NULL, divider->flags,
+ divider->width);
+
+ div_value = clk_readl(divider->reg) >> PCG_DIV_SHIFT;
+ div_value &= clk_div_mask(PCG_DIV_WIDTH);
+
+ return divider_recalc_rate(hw, prediv_rate, div_value, NULL,
+ divider->flags, PCG_DIV_WIDTH);
+}
+
+static int imx_clk_composite_compute_dividers(unsigned long rate,
+ unsigned long parent_rate,
+ int *prediv, int *postdiv)
+{
+ int div1, div2;
+ int error = INT_MAX;
+ int ret = -EINVAL;
+
+ /* default values */
+ *prediv = 1;
+ *postdiv = 1;
+
+ for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) {
+ for (div2 = 1; div2 <= PCG_DIV_MAX; div2++) {
+ int new_error = ((parent_rate / div1) / div2) - rate;
+
+ if (abs(new_error) < abs(error)) {
+ *prediv = div1;
+ *postdiv = div2;
+ error = new_error;
+ ret = 0;
+ }
+ }
+ }
+ return ret;
+}
+
+static long imx_clk_composite_divider_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
+{
+ int prediv_value;
+ int div_value;
+
+ imx_clk_composite_compute_dividers(rate, *prate,
+ &prediv_value, &div_value);
+
+ rate = DIV_ROUND_UP_ULL((u64)*prate, prediv_value);
+ rate = DIV_ROUND_UP_ULL((u64)rate, div_value);
+
+ return rate;
+}
+
+static int imx_clk_composite_divider_set_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned long flags = 0;
+ int prediv_value;
+ int div_value;
+ int ret = 0;
+ u32 val;
+
+ ret = imx_clk_composite_compute_dividers(rate, parent_rate,
+ &prediv_value, &div_value);
+ if (ret)
+ return -EINVAL;
+
+ spin_lock_irqsave(divider->lock, flags);
+
+ val = clk_readl(divider->reg);
+ val &= ~((clk_div_mask(divider->width) << divider->shift) |
+ (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
+
+ val |= (u32)(prediv_value - 1) << divider->shift;
+ val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;
+ clk_writel(val, divider->reg);
+
+ spin_unlock_irqrestore(divider->lock, flags);
+
+ return ret;
+}
+
+static const struct clk_ops imx_clk_composite_divider_ops = {
+ .recalc_rate = imx_clk_composite_divider_recalc_rate,
+ .round_rate = imx_clk_composite_divider_round_rate,
+ .set_rate = imx_clk_composite_divider_set_rate,
+};
+
+struct clk *imx_clk_composite_flags(const char *name,
+ const char **parent_names,
+ int num_parents, void __iomem *reg,
+ unsigned long flags)
+{
+ struct clk_hw *mux_hw = NULL, *div_hw = NULL, *gate_hw = NULL;
+ struct clk_divider *div = NULL;
+ struct clk_gate *gate = NULL;
+ struct clk_mux *mux = NULL;
+ struct clk *clk = ERR_PTR(-ENOMEM);
+
+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ goto fail;
+
+ mux_hw = &mux->hw;
+ mux->reg = reg;
+ mux->shift = PCG_PCS_SHIFT;
+ mux->mask = PCG_PCS_MASK;
+
+ div = kzalloc(sizeof(*div), GFP_KERNEL);
+ if (!div)
+ goto fail;
+
+ div_hw = &div->hw;
+ div->reg = reg;
+ div->shift = PCG_PREDIV_SHIFT;
+ div->width = PCG_PREDIV_WIDTH;
+ div->lock = &imx_ccm_lock;
+ div->flags = CLK_DIVIDER_ROUND_CLOSEST;
+
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate)
+ goto fail;
+
+ gate_hw = &gate->hw;
+ gate->reg = reg;
+ gate->bit_idx = PCG_CGC_SHIFT;
+
+ clk = clk_register_composite(NULL, name, parent_names, num_parents,
+ mux_hw, &clk_mux_ops, div_hw,
+ &imx_clk_composite_divider_ops, gate_hw,
+ &clk_gate_ops, flags);
+ if (IS_ERR(clk))
+ goto fail;
+
+ return clk;
+
+fail:
+ kfree(gate);
+ kfree(div);
+ kfree(mux);
+ return clk;
+}
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 12b3fd6..9d7c9c8 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -232,4 +232,18 @@ struct clk *imx_clk_cpu(const char *name, const char *parent_name,
struct clk *div, struct clk *mux, struct clk *pll,
struct clk *step);
+struct clk *imx_clk_composite_flags(const char *name, const char **parent_names,
+ int num_parents, void __iomem *reg, unsigned long flags);
+
+#define __imx_clk_composite(name, parent_names, reg, flags) \
+ imx_clk_composite_flags(name, parent_names, \
+ ARRAY_SIZE(parent_names), reg, \
+ flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
+
+#define imx_clk_composite(name, parent_names, reg) \
+ __imx_clk_composite(name, parent_names, reg, 0)
+
+#define imx_clk_composite_critical(name, parent_names, reg) \
+ __imx_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)
+
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v9 5/5] clk: imx: add clock driver for i.MX8MQ CCM
[not found] <1537785597-26499-1-git-send-email-abel.vesa@nxp.com>
` (2 preceding siblings ...)
2018-09-24 10:39 ` [PATCH v9 4/5] clk: imx: add imx composite clock Abel Vesa
@ 2018-09-24 10:39 ` Abel Vesa
2018-10-17 19:44 ` Stephen Boyd
3 siblings, 1 reply; 23+ messages in thread
From: Abel Vesa @ 2018-09-24 10:39 UTC (permalink / raw)
To: linux-arm-kernel
From: Lucas Stach <l.stach@pengutronix.de>
Add driver for the Clock Control Module found on i.MX8MQ.
This is largely based on the downstream driver from Anson Huang and
Bai Ping at NXP, plus the imx composite clock from Abel Vesa at NXP,
with only some small adaptions to mainline from me.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-imx8mq.c | 602 +++++++++++++++++++++++++++++++++++++++++++
drivers/clk/imx/clk.h | 36 +++
3 files changed, 639 insertions(+)
create mode 100644 drivers/clk/imx/clk-imx8mq.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 4fabb0a..64e695c 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -30,3 +30,4 @@ obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o
obj-$(CONFIG_SOC_IMX6UL) += clk-imx6ul.o
obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o
obj-$(CONFIG_SOC_VF610) += clk-vf610.o
+obj-$(CONFIG_SOC_IMX8MQ) += clk-imx8mq.o
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
new file mode 100644
index 0000000..aadb523
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -0,0 +1,602 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018 NXP.
+ * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
+ */
+
+#include <dt-bindings/clock/imx8mq-clock.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/types.h>
+
+#include "clk.h"
+
+static u32 share_count_sai1;
+static u32 share_count_sai2;
+static u32 share_count_sai3;
+static u32 share_count_sai4;
+static u32 share_count_sai5;
+static u32 share_count_sai6;
+static u32 share_count_dcss;
+static u32 share_count_nand;
+
+static struct clk *clks[IMX8MQ_CLK_END];
+
+static const char *pll_ref_sels[] = { "osc_25m", "osc_27m", "dummy", "dummy", };
+static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
+static const char *gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
+static const char *vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
+static const char *audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
+static const char *audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
+static const char *video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
+
+static const char *sys1_pll1_out_sels[] = {"sys1_pll1", "sys1_pll1_ref_sel", };
+static const char *sys2_pll1_out_sels[] = {"sys2_pll1", "sys1_pll1_ref_sel", };
+static const char *sys3_pll1_out_sels[] = {"sys3_pll1", "sys3_pll1_ref_sel", };
+static const char *dram_pll1_out_sels[] = {"dram_pll1", "dram_pll1_ref_sel", };
+
+static const char *sys1_pll2_out_sels[] = {"sys1_pll2_div", "sys1_pll1_ref_sel", };
+static const char *sys2_pll2_out_sels[] = {"sys2_pll2_div", "sys2_pll1_ref_sel", };
+static const char *sys3_pll2_out_sels[] = {"sys3_pll2_div", "sys2_pll1_ref_sel", };
+static const char *dram_pll2_out_sels[] = {"dram_pll2_div", "dram_pll1_ref_sel", };
+
+/* CCM ROOT */
+static const char *imx8mq_a53_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m",
+ "sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "sys3_pll2_out", };
+
+static const char *imx8mq_vpu_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m",
+ "sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "vpu_pll_out", };
+
+static const char *imx8mq_gpu_core_sels[] = {"osc_25m", "gpu_pll_out", "sys1_pll_800m", "sys3_pll2_out",
+ "sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
+
+static const char *imx8mq_gpu_shader_sels[] = {"osc_25m", "gpu_pll_out", "sys1_pll_800m", "sys3_pll2_out",
+ "sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
+
+static const char *imx8mq_main_axi_sels[] = {"osc_25m", "sys2_pll_333m", "sys1_pll_800m", "sys2_pll_250m",
+ "sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "sys1_pll_100m",};
+
+static const char *imx8mq_enet_axi_sels[] = {"osc_25m", "sys1_pll_266m", "sys1_pll_800m", "sys2_pll_250m",
+ "sys2_pll_200m", "audio_pll1_out", "video_pll1_out", "sys3_pll2_out", };
+
+static const char *imx8mq_nand_usdhc_sels[] = {"osc_25m", "sys1_pll_266m", "sys1_pll_800m", "sys2_pll_200m",
+ "sys1_pll_133m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll1_out", };
+
+static const char *imx8mq_vpu_bus_sels[] = {"osc_25m", "sys1_pll_800m", "vpu_pll_out", "audio_pll2_out", "sys3_pll2_out", "sys2_pll_1000m", "sys2_pll_200m", "sys1_pll_100m", };
+
+static const char *imx8mq_disp_axi_sels[] = {"osc_25m", "sys2_pll_125m", "sys1_pll_800m", "sys3_pll2_out", "sys1_pll_400m", "audio_pll2_out", "clk_ext1", "clk_ext4", };
+
+static const char *imx8mq_disp_apb_sels[] = {"osc_25m", "sys2_pll_125m", "sys1_pll_800m", "sys3_pll2_out",
+ "sys1_pll_40m", "audio_pll2_out", "clk_ext1", "clk_ext3", };
+
+static const char *imx8mq_disp_rtrm_sels[] = {"osc_25m", "sys1_pll_800m", "sys2_pll_200m", "sys1_pll_400m",
+ "audio_pll1_out", "video_pll1_out", "clk_ext2", "clk_ext3", };
+
+static const char *imx8mq_usb_bus_sels[] = {"osc_25m", "sys2_pll_500m", "sys1_pll_800m", "sys2_pll_100m",
+ "sys2_pll_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", };
+
+static const char *imx8mq_gpu_axi_sels[] = {"osc_25m", "sys1_pll_800m", "gpu_pll_out", "sys3_pll2_out", "sys2_pll_1000m",
+ "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
+
+static const char *imx8mq_gpu_ahb_sels[] = {"osc_25m", "sys1_pll_800m", "gpu_pll_out", "sys3_pll2_out", "sys2_pll_1000m",
+ "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
+
+static const char *imx8mq_noc_sels[] = {"osc_25m", "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_1000m", "sys2_pll_500m",
+ "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
+
+static const char *imx8mq_noc_apb_sels[] = {"osc_25m", "sys1_pll_400m", "sys3_pll2_out", "sys2_pll_333m", "sys2_pll_200m",
+ "sys1_pll_800m", "audio_pll1_out", "video_pll1_out", };
+
+static const char *imx8mq_ahb_sels[] = {"osc_25m", "sys1_pll_133m", "sys1_pll_800m", "sys1_pll_400m",
+ "sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", "video_pll1_out", };
+
+static const char *imx8mq_audio_ahb_sels[] = {"osc_25m", "sys2_pll_500m", "sys1_pll_800m", "sys2_pll_1000m",
+ "sys2_pll_166m", "sys3_pll2_out", "audio_pll1_out", "video_pll1_out", };
+
+static const char *imx8mq_dsi_ahb_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
+ "sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out"};
+
+static const char *imx8mq_dram_alt_sels[] = {"osc_25m", "sys1_pll_800m", "sys1_pll_100m", "sys2_pll_500m",
+ "sys2_pll_250m", "sys1_pll_400m", "audio_pll1_out", "sys1_pll_266m", };
+
+static const char *imx8mq_dram_apb_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
+ "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
+
+static const char *imx8mq_vpu_g1_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_100m", "sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", };
+
+static const char *imx8mq_vpu_g2_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_100m", "sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", };
+
+static const char *imx8mq_disp_dtrc_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll2_out", "audio_pll2_out", };
+
+static const char *imx8mq_disp_dc8000_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll2_out", "audio_pll2_out", };
+
+static const char *imx8mq_pcie1_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m",
+ "sys1_pll_800m", "sys2_pll_500m", "sys2_pll_250m", "sys3_pll2_out", };
+
+static const char *imx8mq_pcie1_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1", "clk_ext2",
+ "clk_ext3", "clk_ext4", };
+
+static const char *imx8mq_pcie1_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_500m", "sys3_pll2_out",
+ "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", };
+
+static const char *imx8mq_dc_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll2_out", "clk_ext4", };
+
+static const char *imx8mq_lcdif_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll2_out", "clk_ext4", };
+
+static const char *imx8mq_sai1_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext1", "clk_ext2", };
+
+static const char *imx8mq_sai2_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext2", "clk_ext3", };
+
+static const char *imx8mq_sai3_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext3", "clk_ext4", };
+
+static const char *imx8mq_sai4_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext1", "clk_ext2", };
+
+static const char *imx8mq_sai5_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext2", "clk_ext3", };
+
+static const char *imx8mq_sai6_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext3", "clk_ext4", };
+
+static const char *imx8mq_spdif1_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext2", "clk_ext3", };
+
+static const char *imx8mq_spdif2_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext3", "clk_ext4", };
+
+static const char *imx8mq_enet_ref_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_500m", "sys2_pll_100m",
+ "sys1_pll_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", };
+
+static const char *imx8mq_enet_timer_sels[] = {"osc_25m", "sys2_pll_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
+ "clk_ext3", "clk_ext4", "video_pll1_out", };
+
+static const char *imx8mq_enet_phy_sels[] = {"osc_25m", "sys2_pll_50m", "sys2_pll_125m", "sys2_pll_500m",
+ "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
+
+static const char *imx8mq_nand_sels[] = {"osc_25m", "sys2_pll_500m", "audio_pll1_out", "sys1_pll_400m",
+ "audio_pll2_out", "sys3_pll2_out", "sys2_pll_250m", "video_pll1_out", };
+
+static const char *imx8mq_qspi_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m",
+ "audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", };
+
+static const char *imx8mq_usdhc1_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m",
+ "audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", };
+
+static const char *imx8mq_usdhc2_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m",
+ "audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", };
+
+static const char *imx8mq_i2c1_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out",
+ "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
+
+static const char *imx8mq_i2c2_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out",
+ "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
+
+static const char *imx8mq_i2c3_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out",
+ "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
+
+static const char *imx8mq_i2c4_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out",
+ "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
+
+static const char *imx8mq_uart1_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
+ "sys3_pll2_out", "clk_ext2", "clk_ext4", "audio_pll2_out", };
+
+static const char *imx8mq_uart2_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
+ "sys3_pll2_out", "clk_ext2", "clk_ext3", "audio_pll2_out", };
+
+static const char *imx8mq_uart3_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
+ "sys3_pll2_out", "clk_ext2", "clk_ext4", "audio_pll2_out", };
+
+static const char *imx8mq_uart4_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
+ "sys3_pll2_out", "clk_ext2", "clk_ext3", "audio_pll2_out", };
+
+static const char *imx8mq_usb_core_sels[] = {"osc_25m", "sys1_pll_100m", "sys1_pll_40m", "sys2_pll_100m",
+ "sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
+
+static const char *imx8mq_usb_phy_sels[] = {"osc_25m", "sys1_pll_100m", "sys1_pll_40m", "sys2_pll_100m",
+ "sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
+
+static const char *imx8mq_ecspi1_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
+ "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
+
+static const char *imx8mq_ecspi2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
+ "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
+
+static const char *imx8mq_pwm1_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
+ "sys3_pll2_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", };
+
+static const char *imx8mq_pwm2_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
+ "sys3_pll2_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", };
+
+static const char *imx8mq_pwm3_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
+ "sys3_pll2_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", };
+
+static const char *imx8mq_pwm4_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
+ "sys3_pll2_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", };
+
+static const char *imx8mq_gpt1_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_400m", "sys1_pll_40m",
+ "sys1_pll_80m", "audio_pll1_out", "clk_ext1", };
+
+static const char *imx8mq_wdog_sels[] = {"osc_25m", "sys1_pll_133m", "sys1_pll_160m", "vpu_pll_out",
+ "sys2_pll_125m", "sys3_pll2_out", "sys1_pll_80m", "sys2_pll_166m", };
+
+static const char *imx8mq_wrclk_sels[] = {"osc_25m", "sys1_pll_40m", "vpu_pll_out", "sys3_pll2_out", "sys2_pll_200m",
+ "sys1_pll_266m", "sys2_pll_500m", "sys1_pll_100m", };
+
+static const char *imx8mq_dsi_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
+ "sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", };
+
+static const char *imx8mq_dsi_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
+ "sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
+
+static const char *imx8mq_dsi_dbi_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_100m", "sys1_pll_800m",
+ "sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", };
+
+static const char *imx8mq_dsi_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
+ "sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out", };
+
+static const char *imx8mq_csi1_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
+ "sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", };
+
+static const char *imx8mq_csi1_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
+ "sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
+
+static const char *imx8mq_csi1_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
+ "sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out", };
+
+static const char *imx8mq_csi2_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
+ "sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", };
+
+static const char *imx8mq_csi2_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
+ "sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
+
+static const char *imx8mq_csi2_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
+ "sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out", };
+
+static const char *imx8mq_pcie2_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m",
+ "sys1_pll_800m", "sys2_pll_500m", "sys2_pll_333m", "sys3_pll2_out", };
+
+static const char *imx8mq_pcie2_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1",
+ "clk_ext2", "clk_ext3", "clk_ext4", "sys1_pll_400m", };
+
+static const char *imx8mq_pcie2_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_50m", "sys3_pll2_out",
+ "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", };
+
+static const char *imx8mq_ecspi3_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
+ "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
+static const char *imx8mq_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
+
+static const char *imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_400m", "sys2_pll_166m", "audio_pll1_out",
+ "video_pll1_out", "ckil", };
+
+static struct clk_onecell_data clk_data;
+
+static void __init imx8mq_clocks_init(struct device_node *ccm_node)
+{
+ struct device_node *np;
+ void __iomem *base;
+ int i;
+
+ clks[IMX8MQ_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
+ clks[IMX8MQ_CLK_32K] = of_clk_get_by_name(ccm_node, "ckil");
+ clks[IMX8MQ_CLK_25M] = of_clk_get_by_name(ccm_node, "osc_25m");
+ clks[IMX8MQ_CLK_27M] = of_clk_get_by_name(ccm_node, "osc_27m");
+ clks[IMX8MQ_CLK_EXT1] = of_clk_get_by_name(ccm_node, "clk_ext1");
+ clks[IMX8MQ_CLK_EXT2] = of_clk_get_by_name(ccm_node, "clk_ext2");
+ clks[IMX8MQ_CLK_EXT3] = of_clk_get_by_name(ccm_node, "clk_ext3");
+ clks[IMX8MQ_CLK_EXT4] = of_clk_get_by_name(ccm_node, "clk_ext4");
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop");
+ base = of_iomap(np, 0);
+ WARN_ON(!base);
+
+ clks[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ clks[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ clks[IMX8MQ_VPU_PLL_REF_SEL] = imx_clk_mux("vpu_pll_ref_sel", base + 0x20, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ clks[IMX8MQ_AUDIO_PLL1_REF_SEL] = imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ clks[IMX8MQ_AUDIO_PLL2_REF_SEL] = imx_clk_mux("audio_pll2_ref_sel", base + 0x8, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ clks[IMX8MQ_VIDEO_PLL1_REF_SEL] = imx_clk_mux("video_pll1_ref_sel", base + 0x10, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ clks[IMX8MQ_SYS1_PLL1_REF_SEL] = imx_clk_mux("sys1_pll1_ref_sel", base + 0x30, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ clks[IMX8MQ_SYS2_PLL1_REF_SEL] = imx_clk_mux("sys2_pll1_ref_sel", base + 0x3c, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ clks[IMX8MQ_SYS3_PLL1_REF_SEL] = imx_clk_mux("sys3_pll1_ref_sel", base + 0x48, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ clks[IMX8MQ_DRAM_PLL1_REF_SEL] = imx_clk_mux("dram_pll1_ref_sel", base + 0x60, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+
+ clks[IMX8MQ_ARM_PLL_REF_DIV] = imx_clk_divider("arm_pll_ref_div", "arm_pll_ref_sel", base + 0x28, 5, 6);
+ clks[IMX8MQ_GPU_PLL_REF_DIV] = imx_clk_divider("gpu_pll_ref_div", "gpu_pll_ref_sel", base + 0x18, 5, 6);
+ clks[IMX8MQ_VPU_PLL_REF_DIV] = imx_clk_divider("vpu_pll_ref_div", "vpu_pll_ref_sel", base + 0x20, 5, 6);
+ clks[IMX8MQ_AUDIO_PLL1_REF_DIV] = imx_clk_divider("audio_pll1_ref_div", "audio_pll1_ref_sel", base + 0x0, 5, 6);
+ clks[IMX8MQ_AUDIO_PLL2_REF_DIV] = imx_clk_divider("audio_pll2_ref_div", "audio_pll2_ref_sel", base + 0x8, 5, 6);
+ clks[IMX8MQ_VIDEO_PLL1_REF_DIV] = imx_clk_divider("video_pll1_ref_div", "video_pll1_ref_sel", base + 0x10, 5, 6);
+ clks[IMX8MQ_SYS1_PLL1_REF_DIV] = imx_clk_divider("sys1_pll1_ref_div", "sys1_pll1_ref_sel", base + 0x38, 25, 3);
+ clks[IMX8MQ_SYS2_PLL1_REF_DIV] = imx_clk_divider("sys2_pll1_ref_div", "sys2_pll1_ref_sel", base + 0x44, 25, 3);
+ clks[IMX8MQ_SYS3_PLL1_REF_DIV] = imx_clk_divider("sys3_pll1_ref_div", "sys3_pll1_ref_sel", base + 0x50, 25, 3);
+ clks[IMX8MQ_DRAM_PLL1_REF_DIV] = imx_clk_divider("dram_pll1_ref_div", "dram_pll1_ref_sel", base + 0x68, 25, 3);
+
+ clks[IMX8MQ_ARM_PLL] = imx_clk_frac_pll("arm_pll", "arm_pll_ref_div", base + 0x28);
+ clks[IMX8MQ_GPU_PLL] = imx_clk_frac_pll("gpu_pll", "gpu_pll_ref_div", base + 0x18);
+ clks[IMX8MQ_VPU_PLL] = imx_clk_frac_pll("vpu_pll", "vpu_pll_ref_div", base + 0x20);
+ clks[IMX8MQ_AUDIO_PLL1] = imx_clk_frac_pll("audio_pll1", "audio_pll1_ref_div", base + 0x0);
+ clks[IMX8MQ_AUDIO_PLL2] = imx_clk_frac_pll("audio_pll2", "audio_pll2_ref_div", base + 0x8);
+ clks[IMX8MQ_VIDEO_PLL1] = imx_clk_frac_pll("video_pll1", "video_pll1_ref_div", base + 0x10);
+ clks[IMX8MQ_SYS1_PLL1] = imx_clk_sccg_pll("sys1_pll1", "sys1_pll1_ref_div", base + 0x30, SCCG_PLL1);
+ clks[IMX8MQ_SYS2_PLL1] = imx_clk_sccg_pll("sys2_pll1", "sys2_pll1_ref_div", base + 0x3c, SCCG_PLL1);
+ clks[IMX8MQ_SYS3_PLL1] = imx_clk_sccg_pll("sys3_pll1", "sys3_pll1_ref_div", base + 0x48, SCCG_PLL1);
+ clks[IMX8MQ_DRAM_PLL1] = imx_clk_sccg_pll("dram_pll1", "dram_pll1_ref_div", base + 0x60, SCCG_PLL1);
+
+ clks[IMX8MQ_SYS1_PLL2] = imx_clk_sccg_pll("sys1_pll2", "sys1_pll1_out_div", base + 0x30, SCCG_PLL2);
+ clks[IMX8MQ_SYS2_PLL2] = imx_clk_sccg_pll("sys2_pll2", "sys2_pll1_out_div", base + 0x3c, SCCG_PLL2);
+ clks[IMX8MQ_SYS3_PLL2] = imx_clk_sccg_pll("sys3_pll2", "sys3_pll1_out_div", base + 0x48, SCCG_PLL2);
+ clks[IMX8MQ_DRAM_PLL2] = imx_clk_sccg_pll("dram_pll2", "dram_pll1_out_div", base + 0x60, SCCG_PLL2);
+
+ /* PLL divs */
+ clks[IMX8MQ_SYS1_PLL1_OUT_DIV] = imx_clk_divider("sys1_pll1_out_div", "sys1_pll1_out", base + 0x38, 19, 6);
+ clks[IMX8MQ_SYS2_PLL1_OUT_DIV] = imx_clk_divider("sys2_pll1_out_div", "sys2_pll1_out", base + 0x44, 19, 6);
+ clks[IMX8MQ_SYS3_PLL1_OUT_DIV] = imx_clk_divider("sys3_pll1_out_div", "sys3_pll1_out", base + 0x50, 19, 6);
+ clks[IMX8MQ_DRAM_PLL1_OUT_DIV] = imx_clk_divider("dram_pll1_out_div", "dram_pll1_out", base + 0x68, 19, 6);
+ clks[IMX8MQ_SYS1_PLL2_DIV] = imx_clk_divider("sys1_pll2_div", "sys1_pll2", base + 0x38, 1, 6);
+ clks[IMX8MQ_SYS2_PLL2_DIV] = imx_clk_divider("sys2_pll2_div", "sys2_pll2", base + 0x44, 1, 6);
+ clks[IMX8MQ_SYS3_PLL2_DIV] = imx_clk_divider("sys3_pll2_div", "sys3_pll2", base + 0x50, 1, 6);
+ clks[IMX8MQ_DRAM_PLL2_DIV] = imx_clk_divider("dram_pll2_div", "dram_pll2", base + 0x68, 1, 6);
+
+ /* PLL bypass out */
+ clks[IMX8MQ_ARM_PLL_BYPASS] = imx_clk_mux("arm_pll_bypass", base + 0x28, 14, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels));
+ clks[IMX8MQ_GPU_PLL_BYPASS] = imx_clk_mux("gpu_pll_bypass", base + 0x18, 14, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels));
+ clks[IMX8MQ_VPU_PLL_BYPASS] = imx_clk_mux("vpu_pll_bypass", base + 0x20, 14, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels));
+ clks[IMX8MQ_AUDIO_PLL1_BYPASS] = imx_clk_mux("audio_pll1_bypass", base + 0x0, 14, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels));
+ clks[IMX8MQ_AUDIO_PLL2_BYPASS] = imx_clk_mux("audio_pll2_bypass", base + 0x8, 14, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels));
+ clks[IMX8MQ_VIDEO_PLL1_BYPASS] = imx_clk_mux("video_pll1_bypass", base + 0x10, 14, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels));
+
+ clks[IMX8MQ_SYS1_PLL1_OUT] = imx_clk_mux("sys1_pll1_out", base + 0x30, 5, 1, sys1_pll1_out_sels, ARRAY_SIZE(sys1_pll1_out_sels));
+ clks[IMX8MQ_SYS2_PLL1_OUT] = imx_clk_mux("sys2_pll1_out", base + 0x3c, 5, 1, sys2_pll1_out_sels, ARRAY_SIZE(sys2_pll1_out_sels));
+ clks[IMX8MQ_SYS3_PLL1_OUT] = imx_clk_mux("sys3_pll1_out", base + 0x48, 5, 1, sys3_pll1_out_sels, ARRAY_SIZE(sys3_pll1_out_sels));
+ clks[IMX8MQ_DRAM_PLL1_OUT] = imx_clk_mux("dram_pll1_out", base + 0x60, 5, 1, dram_pll1_out_sels, ARRAY_SIZE(dram_pll1_out_sels));
+ clks[IMX8MQ_SYS1_PLL2_OUT] = imx_clk_mux("sys1_pll2_out", base + 0x30, 4, 1, sys1_pll2_out_sels, ARRAY_SIZE(sys1_pll2_out_sels));
+ clks[IMX8MQ_SYS2_PLL2_OUT] = imx_clk_mux("sys2_pll2_out", base + 0x3c, 4, 1, sys2_pll2_out_sels, ARRAY_SIZE(sys2_pll2_out_sels));
+ clks[IMX8MQ_SYS3_PLL2_OUT] = imx_clk_mux("sys3_pll2_out", base + 0x48, 4, 1, sys3_pll2_out_sels, ARRAY_SIZE(sys3_pll2_out_sels));
+ clks[IMX8MQ_DRAM_PLL2_OUT] = imx_clk_mux("dram_pll2_out", base + 0x60, 4, 1, dram_pll2_out_sels, ARRAY_SIZE(dram_pll2_out_sels));
+
+ /* unbypass all the plls */
+ clk_set_parent(clks[IMX8MQ_GPU_PLL_BYPASS], clks[IMX8MQ_GPU_PLL]);
+ clk_set_parent(clks[IMX8MQ_VPU_PLL_BYPASS], clks[IMX8MQ_VPU_PLL]);
+ clk_set_parent(clks[IMX8MQ_AUDIO_PLL1_BYPASS], clks[IMX8MQ_AUDIO_PLL1]);
+ clk_set_parent(clks[IMX8MQ_AUDIO_PLL2_BYPASS], clks[IMX8MQ_AUDIO_PLL2]);
+ clk_set_parent(clks[IMX8MQ_VIDEO_PLL1_BYPASS], clks[IMX8MQ_VIDEO_PLL1]);
+ clk_set_parent(clks[IMX8MQ_SYS3_PLL1_OUT], clks[IMX8MQ_SYS3_PLL1]);
+ clk_set_parent(clks[IMX8MQ_SYS3_PLL2_OUT], clks[IMX8MQ_SYS3_PLL2_DIV]);
+
+ /* PLL OUT GATE */
+ clks[IMX8MQ_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x28, 21);
+ clks[IMX8MQ_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x18, 21);
+ clks[IMX8MQ_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x20, 21);
+ clks[IMX8MQ_AUDIO_PLL1_OUT] = imx_clk_gate("audio_pll1_out", "audio_pll1_bypass", base + 0x0, 21);
+ clks[IMX8MQ_AUDIO_PLL2_OUT] = imx_clk_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x8, 21);
+ clks[IMX8MQ_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x10, 21);
+ clks[IMX8MQ_SYS1_PLL_OUT] = imx_clk_gate("sys1_pll_out", "sys1_pll2_out", base + 0x30, 9);
+ clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_gate("sys2_pll_out", "sys2_pll2_out", base + 0x3c, 9);
+ clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_gate("sys3_pll_out", "sys3_pll2_out", base + 0x48, 9);
+ clks[IMX8MQ_DRAM_PLL_OUT] = imx_clk_gate("dram_pll_out", "dram_pll2_out", base + 0x60, 9);
+
+ /* SYS PLL fixed output */
+ clks[IMX8MQ_SYS1_PLL_40M] = imx_clk_fixed_factor("sys1_pll_40m", "sys1_pll_out", 1, 20);
+ clks[IMX8MQ_SYS1_PLL_80M] = imx_clk_fixed_factor("sys1_pll_80m", "sys1_pll_out", 1, 10);
+ clks[IMX8MQ_SYS1_PLL_100M] = imx_clk_fixed_factor("sys1_pll_100m", "sys1_pll_out", 1, 8);
+ clks[IMX8MQ_SYS1_PLL_133M] = imx_clk_fixed_factor("sys1_pll_133m", "sys1_pll_out", 1, 6);
+ clks[IMX8MQ_SYS1_PLL_160M] = imx_clk_fixed_factor("sys1_pll_160m", "sys1_pll_out", 1, 5);
+ clks[IMX8MQ_SYS1_PLL_200M] = imx_clk_fixed_factor("sys1_pll_200m", "sys1_pll_out", 1, 4);
+ clks[IMX8MQ_SYS1_PLL_266M] = imx_clk_fixed_factor("sys1_pll_266m", "sys1_pll_out", 1, 3);
+ clks[IMX8MQ_SYS1_PLL_400M] = imx_clk_fixed_factor("sys1_pll_400m", "sys1_pll_out", 1, 2);
+ clks[IMX8MQ_SYS1_PLL_800M] = imx_clk_fixed_factor("sys1_pll_800m", "sys1_pll_out", 1, 1);
+
+ clks[IMX8MQ_SYS2_PLL_50M] = imx_clk_fixed_factor("sys2_pll_50m", "sys2_pll_out", 1, 20);
+ clks[IMX8MQ_SYS2_PLL_100M] = imx_clk_fixed_factor("sys2_pll_100m", "sys2_pll_out", 1, 10);
+ clks[IMX8MQ_SYS2_PLL_125M] = imx_clk_fixed_factor("sys2_pll_125m", "sys2_pll_out", 1, 8);
+ clks[IMX8MQ_SYS2_PLL_166M] = imx_clk_fixed_factor("sys2_pll_166m", "sys2_pll_out", 1, 6);
+ clks[IMX8MQ_SYS2_PLL_200M] = imx_clk_fixed_factor("sys2_pll_200m", "sys2_pll_out", 1, 5);
+ clks[IMX8MQ_SYS2_PLL_250M] = imx_clk_fixed_factor("sys2_pll_250m", "sys2_pll_out", 1, 4);
+ clks[IMX8MQ_SYS2_PLL_333M] = imx_clk_fixed_factor("sys2_pll_333m", "sys2_pll_out", 1, 3);
+ clks[IMX8MQ_SYS2_PLL_500M] = imx_clk_fixed_factor("sys2_pll_500m", "sys2_pll_out", 1, 2);
+ clks[IMX8MQ_SYS2_PLL_1000M] = imx_clk_fixed_factor("sys2_pll_1000m", "sys2_pll_out", 1, 1);
+
+ np = ccm_node;
+ base = of_iomap(np, 0);
+ WARN_ON(!base);
+ /* CORE */
+ clks[IMX8MQ_CLK_A53_SRC] = imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels));
+ clks[IMX8MQ_CLK_VPU_SRC] = imx_clk_mux2("vpu_src", base + 0x8100, 24, 3, imx8mq_vpu_sels, ARRAY_SIZE(imx8mq_vpu_sels));
+ clks[IMX8MQ_CLK_GPU_CORE_SRC] = imx_clk_mux2("gpu_core_src", base + 0x8180, 24, 3, imx8mq_gpu_core_sels, ARRAY_SIZE(imx8mq_gpu_core_sels));
+ clks[IMX8MQ_CLK_GPU_SHADER_SRC] = imx_clk_mux2("gpu_shader_src", base + 0x8200, 24, 3, imx8mq_gpu_shader_sels, ARRAY_SIZE(imx8mq_gpu_shader_sels));
+ clks[IMX8MQ_CLK_A53_CG] = imx_clk_gate3_flags("arm_a53_cg", "arm_a53_src", base + 0x8000, 28, CLK_IS_CRITICAL);
+ clks[IMX8MQ_CLK_VPU_CG] = imx_clk_gate3("vpu_cg", "vpu_src", base + 0x8100, 28);
+ clks[IMX8MQ_CLK_GPU_CORE_CG] = imx_clk_gate3("gpu_core_cg", "gpu_core_src", base + 0x8180, 28);
+ clks[IMX8MQ_CLK_GPU_SHADER_CG] = imx_clk_gate3("gpu_shader_cg", "gpu_shader_src", base + 0x8200, 28);
+
+ clks[IMX8MQ_CLK_A53_DIV] = imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
+ clks[IMX8MQ_CLK_VPU_DIV] = imx_clk_divider2("vpu_div", "vpu_cg", base + 0x8100, 0, 3);
+ clks[IMX8MQ_CLK_GPU_CORE_DIV] = imx_clk_divider2("gpu_core_div", "gpu_core_cg", base + 0x8180, 0, 3);
+ clks[IMX8MQ_CLK_GPU_SHADER_DIV] = imx_clk_divider2("gpu_shader_div", "gpu_shader_cg", base + 0x8200, 0, 3);
+
+ /* BUS */
+ clks[IMX8MQ_CLK_MAIN_AXI] = imx_clk_composite_critical("main_axi", imx8mq_main_axi_sels, base + 0x8800);
+ clks[IMX8MQ_CLK_ENET_AXI] = imx_clk_composite("enet_axi", imx8mq_enet_axi_sels, base + 0x8880);
+ clks[IMX8MQ_CLK_NAND_USDHC_BUS] = imx_clk_composite("nand_usdhc_bus", imx8mq_nand_usdhc_sels, base + 0x8900);
+ clks[IMX8MQ_CLK_VPU_BUS] = imx_clk_composite("vpu_bus", imx8mq_vpu_bus_sels, base + 0x8980);
+ clks[IMX8MQ_CLK_DISP_AXI] = imx_clk_composite("disp_axi", imx8mq_disp_axi_sels, base + 0x8a00);
+ clks[IMX8MQ_CLK_DISP_APB] = imx_clk_composite("disp_apb", imx8mq_disp_apb_sels, base + 0x8a80);
+ clks[IMX8MQ_CLK_DISP_RTRM] = imx_clk_composite("disp_rtrm", imx8mq_disp_rtrm_sels, base + 0x8b00);
+ clks[IMX8MQ_CLK_USB_BUS] = imx_clk_composite("usb_bus", imx8mq_usb_bus_sels, base + 0x8b80);
+ clks[IMX8MQ_CLK_GPU_AXI] = imx_clk_composite("gpu_axi", imx8mq_gpu_axi_sels, base + 0x8c00);
+ clks[IMX8MQ_CLK_GPU_AHB] = imx_clk_composite("gpu_ahb", imx8mq_gpu_ahb_sels, base + 0x8c80);
+ clks[IMX8MQ_CLK_NOC] = imx_clk_composite_critical("noc", imx8mq_noc_sels, base + 0x8d00);
+ clks[IMX8MQ_CLK_NOC_APB] = imx_clk_composite_critical("noc_apb", imx8mq_noc_apb_sels, base + 0x8d80);
+
+ /* AHB */
+ clks[IMX8MQ_CLK_AHB] = imx_clk_composite("ahb", imx8mq_ahb_sels, base + 0x9000);
+ clks[IMX8MQ_CLK_AUDIO_AHB] = imx_clk_composite("audio_ahb", imx8mq_audio_ahb_sels, base + 0x9100);
+
+ /* IPG */
+ clks[IMX8MQ_CLK_IPG_ROOT] = imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1);
+ clks[IMX8MQ_CLK_IPG_AUDIO_ROOT] = imx_clk_divider2("ipg_audio_root", "audio_ahb", base + 0x9180, 0, 1);
+
+ /* IP */
+ clks[IMX8MQ_CLK_DRAM_CORE] = imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mq_dram_core_sels, ARRAY_SIZE(imx8mq_dram_core_sels), CLK_IS_CRITICAL);
+
+ clks[IMX8MQ_CLK_DRAM_ALT] = imx_clk_composite("dram_alt", imx8mq_dram_alt_sels, base + 0xa000);
+ clks[IMX8MQ_CLK_DRAM_APB] = imx_clk_composite_critical("dram_apb", imx8mq_dram_apb_sels, base + 0xa080);
+ clks[IMX8MQ_CLK_VPU_G1] = imx_clk_composite("vpu_g1", imx8mq_vpu_g1_sels, base + 0xa100);
+ clks[IMX8MQ_CLK_VPU_G2] = imx_clk_composite("vpu_g2", imx8mq_vpu_g2_sels, base + 0xa180);
+ clks[IMX8MQ_CLK_DISP_DTRC] = imx_clk_composite("disp_dtrc", imx8mq_disp_dtrc_sels, base + 0xa200);
+ clks[IMX8MQ_CLK_DISP_DC8000] = imx_clk_composite("disp_dc8000", imx8mq_disp_dc8000_sels, base + 0xa280);
+ clks[IMX8MQ_CLK_PCIE1_CTRL] = imx_clk_composite("pcie1_ctrl", imx8mq_pcie1_ctrl_sels, base + 0xa300);
+ clks[IMX8MQ_CLK_PCIE1_PHY] = imx_clk_composite("pcie1_phy", imx8mq_pcie1_phy_sels, base + 0xa380);
+ clks[IMX8MQ_CLK_PCIE1_AUX] = imx_clk_composite("pcie1_aux", imx8mq_pcie1_aux_sels, base + 0xa400);
+ clks[IMX8MQ_CLK_DC_PIXEL] = imx_clk_composite("dc_pixel", imx8mq_dc_pixel_sels, base + 0xa480);
+ clks[IMX8MQ_CLK_LCDIF_PIXEL] = imx_clk_composite("lcdif_pixel", imx8mq_lcdif_pixel_sels, base + 0xa500);
+ clks[IMX8MQ_CLK_SAI1] = imx_clk_composite("sai1", imx8mq_sai1_sels, base + 0xa580);
+ clks[IMX8MQ_CLK_SAI2] = imx_clk_composite("sai2", imx8mq_sai2_sels, base + 0xa600);
+ clks[IMX8MQ_CLK_SAI3] = imx_clk_composite("sai3", imx8mq_sai3_sels, base + 0xa680);
+ clks[IMX8MQ_CLK_SAI4] = imx_clk_composite("sai4", imx8mq_sai4_sels, base + 0xa700);
+ clks[IMX8MQ_CLK_SAI5] = imx_clk_composite("sai5", imx8mq_sai5_sels, base + 0xa780);
+ clks[IMX8MQ_CLK_SAI6] = imx_clk_composite("sai6", imx8mq_sai6_sels, base + 0xa800);
+ clks[IMX8MQ_CLK_SPDIF1] = imx_clk_composite("spdif1", imx8mq_spdif1_sels, base + 0xa880);
+ clks[IMX8MQ_CLK_SPDIF2] = imx_clk_composite("spdif2", imx8mq_spdif2_sels, base + 0xa900);
+ clks[IMX8MQ_CLK_ENET_REF] = imx_clk_composite("enet_ref", imx8mq_enet_ref_sels, base + 0xa980);
+ clks[IMX8MQ_CLK_ENET_TIMER] = imx_clk_composite("enet_timer", imx8mq_enet_timer_sels, base + 0xaa00);
+ clks[IMX8MQ_CLK_ENET_PHY_REF] = imx_clk_composite("enet_phy", imx8mq_enet_phy_sels, base + 0xaa80);
+ clks[IMX8MQ_CLK_NAND] = imx_clk_composite("nand", imx8mq_nand_sels, base + 0xab00);
+ clks[IMX8MQ_CLK_QSPI] = imx_clk_composite("qspi", imx8mq_qspi_sels, base + 0xab80);
+ clks[IMX8MQ_CLK_USDHC1] = imx_clk_composite("usdhc1", imx8mq_usdhc1_sels, base + 0xac00);
+ clks[IMX8MQ_CLK_USDHC2] = imx_clk_composite("usdhc2", imx8mq_usdhc2_sels, base + 0xac80);
+ clks[IMX8MQ_CLK_I2C1] = imx_clk_composite("i2c1", imx8mq_i2c1_sels, base + 0xad00);
+ clks[IMX8MQ_CLK_I2C2] = imx_clk_composite("i2c2", imx8mq_i2c2_sels, base + 0xad80);
+ clks[IMX8MQ_CLK_I2C3] = imx_clk_composite("i2c3", imx8mq_i2c3_sels, base + 0xae00);
+ clks[IMX8MQ_CLK_I2C4] = imx_clk_composite("i2c4", imx8mq_i2c4_sels, base + 0xae80);
+ clks[IMX8MQ_CLK_UART1] = imx_clk_composite("uart1", imx8mq_uart1_sels, base + 0xaf00);
+ clks[IMX8MQ_CLK_UART2] = imx_clk_composite("uart2", imx8mq_uart2_sels, base + 0xaf80);
+ clks[IMX8MQ_CLK_UART3] = imx_clk_composite("uart3", imx8mq_uart3_sels, base + 0xb000);
+ clks[IMX8MQ_CLK_UART4] = imx_clk_composite("uart4", imx8mq_uart4_sels, base + 0xb080);
+ clks[IMX8MQ_CLK_USB_CORE_REF] = imx_clk_composite("usb_core_ref", imx8mq_usb_core_sels, base + 0xb100);
+ clks[IMX8MQ_CLK_USB_PHY_REF] = imx_clk_composite("usb_phy_ref", imx8mq_usb_phy_sels, base + 0xb180);
+ clks[IMX8MQ_CLK_ECSPI1] = imx_clk_composite("ecspi1", imx8mq_ecspi1_sels, base + 0xb280);
+ clks[IMX8MQ_CLK_ECSPI2] = imx_clk_composite("ecspi2", imx8mq_ecspi2_sels, base + 0xb300);
+ clks[IMX8MQ_CLK_PWM1] = imx_clk_composite("pwm1", imx8mq_pwm1_sels, base + 0xb380);
+ clks[IMX8MQ_CLK_PWM2] = imx_clk_composite("pwm2", imx8mq_pwm2_sels, base + 0xb400);
+ clks[IMX8MQ_CLK_PWM3] = imx_clk_composite("pwm3", imx8mq_pwm3_sels, base + 0xb480);
+ clks[IMX8MQ_CLK_PWM4] = imx_clk_composite("pwm4", imx8mq_pwm4_sels, base + 0xb500);
+ clks[IMX8MQ_CLK_GPT1] = imx_clk_composite("gpt1", imx8mq_gpt1_sels, base + 0xb580);
+ clks[IMX8MQ_CLK_WDOG] = imx_clk_composite("wdog", imx8mq_wdog_sels, base + 0xb900);
+ clks[IMX8MQ_CLK_WRCLK] = imx_clk_composite("wrclk", imx8mq_wrclk_sels, base + 0xb980);
+ clks[IMX8MQ_CLK_CLKO2] = imx_clk_composite("clko2", imx8mq_clko2_sels, base + 0xba80);
+ clks[IMX8MQ_CLK_DSI_CORE] = imx_clk_composite("dsi_core", imx8mq_dsi_core_sels, base + 0xbb00);
+ clks[IMX8MQ_CLK_DSI_PHY_REF] = imx_clk_composite("dsi_phy_ref", imx8mq_dsi_phy_sels, base + 0xbb80);
+ clks[IMX8MQ_CLK_DSI_DBI] = imx_clk_composite("dsi_dbi", imx8mq_dsi_dbi_sels, base + 0xbc00);
+ clks[IMX8MQ_CLK_DSI_ESC] = imx_clk_composite("dsi_esc", imx8mq_dsi_esc_sels, base + 0xbc80);
+ clks[IMX8MQ_CLK_DSI_AHB] = imx_clk_composite("dsi_ahb", imx8mq_dsi_ahb_sels, base + 0x9200);
+ clks[IMX8MQ_CLK_CSI1_CORE] = imx_clk_composite("csi1_core", imx8mq_csi1_core_sels, base + 0xbd00);
+ clks[IMX8MQ_CLK_CSI1_PHY_REF] = imx_clk_composite("csi1_phy_ref", imx8mq_csi1_phy_sels, base + 0xbd80);
+ clks[IMX8MQ_CLK_CSI1_ESC] = imx_clk_composite("csi1_esc", imx8mq_csi1_esc_sels, base + 0xbe00);
+ clks[IMX8MQ_CLK_CSI2_CORE] = imx_clk_composite("csi2_core", imx8mq_csi2_core_sels, base + 0xbe80);
+ clks[IMX8MQ_CLK_CSI2_PHY_REF] = imx_clk_composite("csi2_phy_ref", imx8mq_csi2_phy_sels, base + 0xbf00);
+ clks[IMX8MQ_CLK_CSI2_ESC] = imx_clk_composite("csi2_esc", imx8mq_csi2_esc_sels, base + 0xbf80);
+ clks[IMX8MQ_CLK_PCIE2_CTRL] = imx_clk_composite("pcie2_ctrl", imx8mq_pcie2_ctrl_sels, base + 0xc000);
+ clks[IMX8MQ_CLK_PCIE2_PHY] = imx_clk_composite("pcie2_phy", imx8mq_pcie2_phy_sels, base + 0xc080);
+ clks[IMX8MQ_CLK_PCIE2_AUX] = imx_clk_composite("pcie2_aux", imx8mq_pcie2_aux_sels, base + 0xc100);
+ clks[IMX8MQ_CLK_ECSPI3] = imx_clk_composite("ecspi3", imx8mq_ecspi3_sels, base + 0xc180);
+
+ /*FIXME, the doc is not ready now */
+ clks[IMX8MQ_CLK_ECSPI1_ROOT] = imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0);
+ clks[IMX8MQ_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0);
+ clks[IMX8MQ_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0);
+ clks[IMX8MQ_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0);
+ clks[IMX8MQ_CLK_GPT1_ROOT] = imx_clk_gate4("gpt1_root_clk", "gpt1", base + 0x4100, 0);
+ clks[IMX8MQ_CLK_I2C1_ROOT] = imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0);
+ clks[IMX8MQ_CLK_I2C2_ROOT] = imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0);
+ clks[IMX8MQ_CLK_I2C3_ROOT] = imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0);
+ clks[IMX8MQ_CLK_I2C4_ROOT] = imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0);
+ clks[IMX8MQ_CLK_MU_ROOT] = imx_clk_gate4("mu_root_clk", "ipg_root", base + 0x4210, 0);
+ clks[IMX8MQ_CLK_OCOTP_ROOT] = imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0);
+ clks[IMX8MQ_CLK_PCIE1_ROOT] = imx_clk_gate4("pcie1_root_clk", "pcie1_ctrl", base + 0x4250, 0);
+ clks[IMX8MQ_CLK_PCIE2_ROOT] = imx_clk_gate4("pcie2_root_clk", "pcie2_ctrl", base + 0x4640, 0);
+ clks[IMX8MQ_CLK_PWM1_ROOT] = imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0);
+ clks[IMX8MQ_CLK_PWM2_ROOT] = imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0);
+ clks[IMX8MQ_CLK_PWM3_ROOT] = imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0);
+ clks[IMX8MQ_CLK_PWM4_ROOT] = imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0);
+ clks[IMX8MQ_CLK_QSPI_ROOT] = imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0);
+ clks[IMX8MQ_CLK_RAWNAND_ROOT] = imx_clk_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand);
+ clks[IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus", base + 0x4300, 0, &share_count_nand);
+ clks[IMX8MQ_CLK_SAI1_ROOT] = imx_clk_gate2_shared2("sai1_root_clk", "sai1", base + 0x4330, 0, &share_count_sai1);
+ clks[IMX8MQ_CLK_SAI1_IPG] = imx_clk_gate2_shared2("sai1_ipg_clk", "ipg_audio_root", base + 0x4330, 0, &share_count_sai1);
+ clks[IMX8MQ_CLK_SAI2_ROOT] = imx_clk_gate2_shared2("sai2_root_clk", "sai2", base + 0x4340, 0, &share_count_sai2);
+ clks[IMX8MQ_CLK_SAI2_IPG] = imx_clk_gate2_shared2("sai2_ipg_clk", "ipg_root", base + 0x4340, 0, &share_count_sai2);
+ clks[IMX8MQ_CLK_SAI3_ROOT] = imx_clk_gate2_shared2("sai3_root_clk", "sai3", base + 0x4350, 0, &share_count_sai3);
+ clks[IMX8MQ_CLK_SAI3_IPG] = imx_clk_gate2_shared2("sai3_ipg_clk", "ipg_root", base + 0x4350, 0, &share_count_sai3);
+ clks[IMX8MQ_CLK_SAI4_ROOT] = imx_clk_gate2_shared2("sai4_root_clk", "sai4", base + 0x4360, 0, &share_count_sai4);
+ clks[IMX8MQ_CLK_SAI4_IPG] = imx_clk_gate2_shared2("sai4_ipg_clk", "ipg_audio_root", base + 0x4360, 0, &share_count_sai4);
+ clks[IMX8MQ_CLK_SAI5_ROOT] = imx_clk_gate2_shared2("sai5_root_clk", "sai5", base + 0x4370, 0, &share_count_sai5);
+ clks[IMX8MQ_CLK_SAI5_IPG] = imx_clk_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5);
+ clks[IMX8MQ_CLK_SAI6_ROOT] = imx_clk_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6);
+ clks[IMX8MQ_CLK_SAI6_IPG] = imx_clk_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6);
+ clks[IMX8MQ_CLK_UART1_ROOT] = imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0);
+ clks[IMX8MQ_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
+ clks[IMX8MQ_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
+ clks[IMX8MQ_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0);
+ clks[IMX8MQ_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_core_ref", base + 0x44d0, 0);
+ clks[IMX8MQ_CLK_USB2_CTRL_ROOT] = imx_clk_gate4("usb2_ctrl_root_clk", "usb_core_ref", base + 0x44e0, 0);
+ clks[IMX8MQ_CLK_USB1_PHY_ROOT] = imx_clk_gate4("usb1_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0);
+ clks[IMX8MQ_CLK_USB2_PHY_ROOT] = imx_clk_gate4("usb2_phy_root_clk", "usb_phy_ref", base + 0x4500, 0);
+ clks[IMX8MQ_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0);
+ clks[IMX8MQ_CLK_USDHC2_ROOT] = imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0);
+ clks[IMX8MQ_CLK_WDOG1_ROOT] = imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0);
+ clks[IMX8MQ_CLK_WDOG2_ROOT] = imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0);
+ clks[IMX8MQ_CLK_WDOG3_ROOT] = imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0);
+ clks[IMX8MQ_CLK_VPU_G1_ROOT] = imx_clk_gate2_flags("vpu_g1_root_clk", "vpu_g1", base + 0x4560, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
+ clks[IMX8MQ_CLK_GPU_ROOT] = imx_clk_gate4("gpu_root_clk", "gpu_core_div", base + 0x4570, 0);
+ clks[IMX8MQ_CLK_VPU_G2_ROOT] = imx_clk_gate2_flags("vpu_g2_root_clk", "vpu_g2", base + 0x45a0, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
+ clks[IMX8MQ_CLK_DISP_ROOT] = imx_clk_gate2_shared2("disp_root_clk", "disp_dc8000", base + 0x45d0, 0, &share_count_dcss);
+ clks[IMX8MQ_CLK_DISP_AXI_ROOT] = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_dcss);
+ clks[IMX8MQ_CLK_DISP_APB_ROOT] = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_dcss);
+ clks[IMX8MQ_CLK_DISP_RTRM_ROOT] = imx_clk_gate2_shared2("disp_rtrm_root_clk", "disp_rtrm", base + 0x45d0, 0, &share_count_dcss);
+ clks[IMX8MQ_CLK_TMU_ROOT] = imx_clk_gate4_flags("tmu_root_clk", "ipg_root", base + 0x4620, 0, CLK_IS_CRITICAL);
+ clks[IMX8MQ_CLK_VPU_DEC_ROOT] = imx_clk_gate2_flags("vpu_dec_root_clk", "vpu_bus", base + 0x4630, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
+ clks[IMX8MQ_CLK_CSI1_ROOT] = imx_clk_gate4("csi1_root_clk", "csi1_core", base + 0x4650, 0);
+ clks[IMX8MQ_CLK_CSI2_ROOT] = imx_clk_gate4("csi2_root_clk", "csi2_core", base + 0x4660, 0);
+ clks[IMX8MQ_CLK_SDMA1_ROOT] = imx_clk_gate4("sdma1_clk", "ipg_root", base + 0x43a0, 0);
+ clks[IMX8MQ_CLK_SDMA2_ROOT] = imx_clk_gate4("sdma2_clk", "ipg_audio_root", base + 0x43b0, 0);
+
+ clks[IMX8MQ_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc_25m", 1, 8);
+ clks[IMX8MQ_CLK_DRAM_ALT_ROOT] = imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4);
+
+ for (i = 0; i < IMX8MQ_CLK_END; i++)
+ if (IS_ERR(clks[i]))
+ pr_err("i.MX8mq clk %u register failed with %ld\n",
+ i, PTR_ERR(clks[i]));
+
+ clk_data.clks = clks;
+ clk_data.clk_num = ARRAY_SIZE(clks);
+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
+ clk_set_parent(clks[IMX8MQ_CLK_AHB], clks[IMX8MQ_SYS1_PLL_133M]);
+ clk_set_parent(clks[IMX8MQ_CLK_NAND_USDHC_BUS], clks[IMX8MQ_SYS1_PLL_266M]);
+ clk_set_parent(clks[IMX8MQ_CLK_AUDIO_AHB], clks[IMX8MQ_SYS2_PLL_500M]);
+
+ /* config video_pll1 clock */
+ clk_set_parent(clks[IMX8MQ_VIDEO_PLL1_REF_SEL], clks[IMX8MQ_CLK_27M]);
+ clk_set_rate(clks[IMX8MQ_VIDEO_PLL1], 593999999);
+
+ /* increase NOC clock to achieve best DDR access performance */
+ clk_set_rate(clks[IMX8MQ_CLK_NOC], clk_get_rate(clks[IMX8MQ_SYS1_PLL_800M]));
+
+ /* set pcie root's parent clk source */
+ clk_set_parent(clks[IMX8MQ_CLK_PCIE1_CTRL], clks[IMX8MQ_SYS2_PLL_250M]);
+ clk_set_parent(clks[IMX8MQ_CLK_PCIE1_PHY], clks[IMX8MQ_SYS2_PLL_100M]);
+ clk_set_parent(clks[IMX8MQ_CLK_PCIE2_CTRL], clks[IMX8MQ_SYS2_PLL_250M]);
+ clk_set_parent(clks[IMX8MQ_CLK_PCIE2_PHY], clks[IMX8MQ_SYS2_PLL_100M]);
+
+ clk_set_parent(clks[IMX8MQ_CLK_CSI1_CORE], clks[IMX8MQ_SYS1_PLL_266M]);
+ clk_set_parent(clks[IMX8MQ_CLK_CSI1_PHY_REF], clks[IMX8MQ_SYS2_PLL_1000M]);
+ clk_set_parent(clks[IMX8MQ_CLK_CSI1_ESC], clks[IMX8MQ_SYS1_PLL_800M]);
+ clk_set_parent(clks[IMX8MQ_CLK_CSI2_CORE], clks[IMX8MQ_SYS1_PLL_266M]);
+ clk_set_parent(clks[IMX8MQ_CLK_CSI2_PHY_REF], clks[IMX8MQ_SYS2_PLL_1000M]);
+ clk_set_parent(clks[IMX8MQ_CLK_CSI2_ESC], clks[IMX8MQ_SYS1_PLL_800M]);
+}
+
+CLK_OF_DECLARE(imx8mq, "fsl,imx8mq-ccm", imx8mq_clocks_init);
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 9d7c9c8..64faf27 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -128,6 +128,15 @@ static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
reg, shift, width, 0, &imx_ccm_lock);
}
+static inline struct clk *imx_clk_divider2_flags(const char *name,
+ const char *parent, void __iomem *reg, u8 shift, u8 width,
+ unsigned long flags)
+{
+ return clk_register_divider(NULL, name, parent,
+ flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
+ reg, shift, width, 0, &imx_ccm_lock);
+}
+
static inline struct clk *imx_clk_gate(const char *name, const char *parent,
void __iomem *reg, u8 shift)
{
@@ -195,6 +204,15 @@ static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
reg, shift, 0, &imx_ccm_lock);
}
+static inline struct clk *imx_clk_gate3_flags(const char *name,
+ const char *parent, void __iomem *reg, u8 shift,
+ unsigned long flags)
+{
+ return clk_register_gate(NULL, name, parent,
+ flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
+ reg, shift, 0, &imx_ccm_lock);
+}
+
static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
void __iomem *reg, u8 shift)
{
@@ -203,6 +221,15 @@ static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
reg, shift, 0x3, 0, &imx_ccm_lock, NULL);
}
+static inline struct clk *imx_clk_gate4_flags(const char *name,
+ const char *parent, void __iomem *reg, u8 shift,
+ unsigned long flags)
+{
+ return clk_register_gate2(NULL, name, parent,
+ flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
+ reg, shift, 0x3, 0, &imx_ccm_lock, NULL);
+}
+
static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
u8 shift, u8 width, const char **parents, int num_parents)
{
@@ -228,6 +255,15 @@ static inline struct clk *imx_clk_mux_flags(const char *name,
&imx_ccm_lock);
}
+static inline struct clk *imx_clk_mux2_flags(const char *name,
+ void __iomem *reg, u8 shift, u8 width, const char **parents,
+ int num_parents, unsigned long flags)
+{
+ return clk_register_mux(NULL, name, parents, num_parents,
+ flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
+ reg, shift, width, 0, &imx_ccm_lock);
+}
+
struct clk *imx_clk_cpu(const char *name, const char *parent_name,
struct clk *div, struct clk *mux, struct clk *pll,
struct clk *step);
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v9 4/5] clk: imx: add imx composite clock
2018-09-24 10:39 ` [PATCH v9 4/5] clk: imx: add imx composite clock Abel Vesa
@ 2018-09-25 16:42 ` Fabio Estevam
2018-09-26 6:47 ` Sascha Hauer
2018-10-17 19:51 ` Stephen Boyd
1 sibling, 1 reply; 23+ messages in thread
From: Fabio Estevam @ 2018-09-25 16:42 UTC (permalink / raw)
To: linux-arm-kernel
Hi Abel,
On Mon, Sep 24, 2018 at 7:39 AM, Abel Vesa <abel.vesa@nxp.com> wrote:
> +static long imx_clk_composite_divider_round_rate(struct clk_hw *hw,
> + unsigned long rate,
> + unsigned long *prate)
> +{
> + int prediv_value;
> + int div_value;
> +
> + imx_clk_composite_compute_dividers(rate, *prate,
> + &prediv_value, &div_value);
> +
> + rate = DIV_ROUND_UP_ULL((u64)*prate, prediv_value);
You assing a value to 'rate' here.
> + rate = DIV_ROUND_UP_ULL((u64)rate, div_value);
And then overwrite it immediately after.
Is this really the intended behavior?
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v9 4/5] clk: imx: add imx composite clock
2018-09-25 16:42 ` Fabio Estevam
@ 2018-09-26 6:47 ` Sascha Hauer
2018-09-26 12:02 ` Fabio Estevam
0 siblings, 1 reply; 23+ messages in thread
From: Sascha Hauer @ 2018-09-26 6:47 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Sep 25, 2018 at 01:42:12PM -0300, Fabio Estevam wrote:
> Hi Abel,
>
> On Mon, Sep 24, 2018 at 7:39 AM, Abel Vesa <abel.vesa@nxp.com> wrote:
>
> > +static long imx_clk_composite_divider_round_rate(struct clk_hw *hw,
> > + unsigned long rate,
> > + unsigned long *prate)
> > +{
> > + int prediv_value;
> > + int div_value;
> > +
> > + imx_clk_composite_compute_dividers(rate, *prate,
> > + &prediv_value, &div_value);
> > +
> > + rate = DIV_ROUND_UP_ULL((u64)*prate, prediv_value);
>
> You assing a value to 'rate' here.
>
> > + rate = DIV_ROUND_UP_ULL((u64)rate, div_value);
>
> And then overwrite it immediately after.
It's:
rate = *prate / prediv_value;
rate = rate / div_value;
To me this looks correct. However, For an unsigned long type we have
DIV_ROUND_UP() with which we do not need any casting. For 64bit code
unsigned long is 64bit anyway which makes the cast a no-op and for 32bit
code there's also no point in exanding the initial 32bit value to 64bit.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
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^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v9 4/5] clk: imx: add imx composite clock
2018-09-26 6:47 ` Sascha Hauer
@ 2018-09-26 12:02 ` Fabio Estevam
0 siblings, 0 replies; 23+ messages in thread
From: Fabio Estevam @ 2018-09-26 12:02 UTC (permalink / raw)
To: linux-arm-kernel
Hi Sascha,
On Wed, Sep 26, 2018 at 3:47 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> It's:
> rate = *prate / prediv_value;
> rate = rate / div_value;
Yes, this looks correct. Thanks for the feedback.
> To me this looks correct. However, For an unsigned long type we have
> DIV_ROUND_UP() with which we do not need any casting. For 64bit code
> unsigned long is 64bit anyway which makes the cast a no-op and for 32bit
> code there's also no point in exanding the initial 32bit value to 64bit.
That's a good point too.
Thanks
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v9 5/5] clk: imx: add clock driver for i.MX8MQ CCM
2018-09-24 10:39 ` [PATCH v9 5/5] clk: imx: add clock driver for i.MX8MQ CCM Abel Vesa
@ 2018-10-17 19:44 ` Stephen Boyd
2018-11-07 12:09 ` Abel Vesa
0 siblings, 1 reply; 23+ messages in thread
From: Stephen Boyd @ 2018-10-17 19:44 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Abel Vesa (2018-09-24 03:39:57)
> From: Lucas Stach <l.stach@pengutronix.de>
>
> Add driver for the Clock Control Module found on i.MX8MQ.
>
> This is largely based on the downstream driver from Anson Huang and
> Bai Ping at NXP, plus the imx composite clock from Abel Vesa at NXP,
> with only some small adaptions to mainline from me.
Can you point to the downstream driver so we can know what small
adaptations were made.
>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
> drivers/clk/imx/Makefile | 1 +
> drivers/clk/imx/clk-imx8mq.c | 602 +++++++++++++++++++++++++++++++++++++++++++
> drivers/clk/imx/clk.h | 36 +++
> 3 files changed, 639 insertions(+)
> create mode 100644 drivers/clk/imx/clk-imx8mq.c
>
> diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
> index 4fabb0a..64e695c 100644
> --- a/drivers/clk/imx/Makefile
> +++ b/drivers/clk/imx/Makefile
> @@ -30,3 +30,4 @@ obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o
> obj-$(CONFIG_SOC_IMX6UL) += clk-imx6ul.o
> obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o
> obj-$(CONFIG_SOC_VF610) += clk-vf610.o
> +obj-$(CONFIG_SOC_IMX8MQ) += clk-imx8mq.o
Please try to keep this alphabetical on CONFIG symbol.
> diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
> new file mode 100644
> index 0000000..aadb523
> --- /dev/null
> +++ b/drivers/clk/imx/clk-imx8mq.c
> @@ -0,0 +1,602 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright 2018 NXP.
> + * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
> + */
> +
> +#include <dt-bindings/clock/imx8mq-clock.h>
> +#include <linux/clk.h>
> +#include <linux/clkdev.h>
Are these two includes used?
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/types.h>
> +
> +#include "clk.h"
> +
> +static u32 share_count_sai1;
> +static u32 share_count_sai2;
> +static u32 share_count_sai3;
> +static u32 share_count_sai4;
> +static u32 share_count_sai5;
> +static u32 share_count_sai6;
> +static u32 share_count_dcss;
> +static u32 share_count_nand;
> +
[...]
> +
> +static const char *imx8mq_ecspi3_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
> + "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
> +static const char *imx8mq_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
> +
> +static const char *imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_400m", "sys2_pll_166m", "audio_pll1_out",
> + "video_pll1_out", "ckil", };
> +
> +static struct clk_onecell_data clk_data;
> +
> +static void __init imx8mq_clocks_init(struct device_node *ccm_node)
> +{
> + struct device_node *np;
> + void __iomem *base;
> + int i;
> +
> + clks[IMX8MQ_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
> + clks[IMX8MQ_CLK_32K] = of_clk_get_by_name(ccm_node, "ckil");
> + clks[IMX8MQ_CLK_25M] = of_clk_get_by_name(ccm_node, "osc_25m");
> + clks[IMX8MQ_CLK_27M] = of_clk_get_by_name(ccm_node, "osc_27m");
> + clks[IMX8MQ_CLK_EXT1] = of_clk_get_by_name(ccm_node, "clk_ext1");
> + clks[IMX8MQ_CLK_EXT2] = of_clk_get_by_name(ccm_node, "clk_ext2");
> + clks[IMX8MQ_CLK_EXT3] = of_clk_get_by_name(ccm_node, "clk_ext3");
> + clks[IMX8MQ_CLK_EXT4] = of_clk_get_by_name(ccm_node, "clk_ext4");
> +
> + np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop");
> + base = of_iomap(np, 0);
> + WARN_ON(!base);
And if that fails? return without continuing?
> +
> + clks[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
> + clks[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
> + clks[IMX8MQ_VPU_PLL_REF_SEL] = imx_clk_mux("vpu_pll_ref_sel", base + 0x20, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
> + clks[IMX8MQ_AUDIO_PLL1_REF_SEL] = imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
[..]
> + clks[IMX8MQ_CLK_DSI_CORE] = imx_clk_composite("dsi_core", imx8mq_dsi_core_sels, base + 0xbb00);
> + clks[IMX8MQ_CLK_DSI_PHY_REF] = imx_clk_composite("dsi_phy_ref", imx8mq_dsi_phy_sels, base + 0xbb80);
> + clks[IMX8MQ_CLK_DSI_DBI] = imx_clk_composite("dsi_dbi", imx8mq_dsi_dbi_sels, base + 0xbc00);
> + clks[IMX8MQ_CLK_DSI_ESC] = imx_clk_composite("dsi_esc", imx8mq_dsi_esc_sels, base + 0xbc80);
> + clks[IMX8MQ_CLK_DSI_AHB] = imx_clk_composite("dsi_ahb", imx8mq_dsi_ahb_sels, base + 0x9200);
> + clks[IMX8MQ_CLK_CSI1_CORE] = imx_clk_composite("csi1_core", imx8mq_csi1_core_sels, base + 0xbd00);
> + clks[IMX8MQ_CLK_CSI1_PHY_REF] = imx_clk_composite("csi1_phy_ref", imx8mq_csi1_phy_sels, base + 0xbd80);
> + clks[IMX8MQ_CLK_CSI1_ESC] = imx_clk_composite("csi1_esc", imx8mq_csi1_esc_sels, base + 0xbe00);
> + clks[IMX8MQ_CLK_CSI2_CORE] = imx_clk_composite("csi2_core", imx8mq_csi2_core_sels, base + 0xbe80);
> + clks[IMX8MQ_CLK_CSI2_PHY_REF] = imx_clk_composite("csi2_phy_ref", imx8mq_csi2_phy_sels, base + 0xbf00);
> + clks[IMX8MQ_CLK_CSI2_ESC] = imx_clk_composite("csi2_esc", imx8mq_csi2_esc_sels, base + 0xbf80);
> + clks[IMX8MQ_CLK_PCIE2_CTRL] = imx_clk_composite("pcie2_ctrl", imx8mq_pcie2_ctrl_sels, base + 0xc000);
> + clks[IMX8MQ_CLK_PCIE2_PHY] = imx_clk_composite("pcie2_phy", imx8mq_pcie2_phy_sels, base + 0xc080);
> + clks[IMX8MQ_CLK_PCIE2_AUX] = imx_clk_composite("pcie2_aux", imx8mq_pcie2_aux_sels, base + 0xc100);
> + clks[IMX8MQ_CLK_ECSPI3] = imx_clk_composite("ecspi3", imx8mq_ecspi3_sels, base + 0xc180);
> +
> + /*FIXME, the doc is not ready now */
What does this mean?
> + clks[IMX8MQ_CLK_ECSPI1_ROOT] = imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0);
> + clks[IMX8MQ_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0);
> + clks[IMX8MQ_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0);
> + clks[IMX8MQ_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0);
> + clks[IMX8MQ_CLK_GPT1_ROOT] = imx_clk_gate4("gpt1_root_clk", "gpt1", base + 0x4100, 0);
[...]
> +
> + clks[IMX8MQ_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc_25m", 1, 8);
> + clks[IMX8MQ_CLK_DRAM_ALT_ROOT] = imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4);
> +
> + for (i = 0; i < IMX8MQ_CLK_END; i++)
> + if (IS_ERR(clks[i]))
> + pr_err("i.MX8mq clk %u register failed with %ld\n",
> + i, PTR_ERR(clks[i]));
> +
> + clk_data.clks = clks;
> + clk_data.clk_num = ARRAY_SIZE(clks);
> + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
Any chance to move to using clk_hw based provider and clk registration
APIs?
> +
> + clk_set_parent(clks[IMX8MQ_CLK_AHB], clks[IMX8MQ_SYS1_PLL_133M]);
> + clk_set_parent(clks[IMX8MQ_CLK_NAND_USDHC_BUS], clks[IMX8MQ_SYS1_PLL_266M]);
> + clk_set_parent(clks[IMX8MQ_CLK_AUDIO_AHB], clks[IMX8MQ_SYS2_PLL_500M]);
> +
> + /* config video_pll1 clock */
> + clk_set_parent(clks[IMX8MQ_VIDEO_PLL1_REF_SEL], clks[IMX8MQ_CLK_27M]);
> + clk_set_rate(clks[IMX8MQ_VIDEO_PLL1], 593999999);
> +
> + /* increase NOC clock to achieve best DDR access performance */
> + clk_set_rate(clks[IMX8MQ_CLK_NOC], clk_get_rate(clks[IMX8MQ_SYS1_PLL_800M]));
> +
> + /* set pcie root's parent clk source */
> + clk_set_parent(clks[IMX8MQ_CLK_PCIE1_CTRL], clks[IMX8MQ_SYS2_PLL_250M]);
> + clk_set_parent(clks[IMX8MQ_CLK_PCIE1_PHY], clks[IMX8MQ_SYS2_PLL_100M]);
> + clk_set_parent(clks[IMX8MQ_CLK_PCIE2_CTRL], clks[IMX8MQ_SYS2_PLL_250M]);
> + clk_set_parent(clks[IMX8MQ_CLK_PCIE2_PHY], clks[IMX8MQ_SYS2_PLL_100M]);
> +
> + clk_set_parent(clks[IMX8MQ_CLK_CSI1_CORE], clks[IMX8MQ_SYS1_PLL_266M]);
> + clk_set_parent(clks[IMX8MQ_CLK_CSI1_PHY_REF], clks[IMX8MQ_SYS2_PLL_1000M]);
> + clk_set_parent(clks[IMX8MQ_CLK_CSI1_ESC], clks[IMX8MQ_SYS1_PLL_800M]);
> + clk_set_parent(clks[IMX8MQ_CLK_CSI2_CORE], clks[IMX8MQ_SYS1_PLL_266M]);
> + clk_set_parent(clks[IMX8MQ_CLK_CSI2_PHY_REF], clks[IMX8MQ_SYS2_PLL_1000M]);
> + clk_set_parent(clks[IMX8MQ_CLK_CSI2_ESC], clks[IMX8MQ_SYS1_PLL_800M]);
Can this be done with assigned clock parents and assigned clock rates?
> +}
> +
> +CLK_OF_DECLARE(imx8mq, "fsl,imx8mq-ccm", imx8mq_clocks_init);
Can you please add a comment indicating why this can't be done with a
platform driver, or convert this to be a platform driver?
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v9 4/5] clk: imx: add imx composite clock
2018-09-24 10:39 ` [PATCH v9 4/5] clk: imx: add imx composite clock Abel Vesa
2018-09-25 16:42 ` Fabio Estevam
@ 2018-10-17 19:51 ` Stephen Boyd
2018-10-18 9:57 ` Abel Vesa
1 sibling, 1 reply; 23+ messages in thread
From: Stephen Boyd @ 2018-10-17 19:51 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Abel Vesa (2018-09-24 03:39:56)
> diff --git a/drivers/clk/imx/clk-composite.c b/drivers/clk/imx/clk-composite.c
> new file mode 100644
> index 0000000..4b03107
> --- /dev/null
> +++ b/drivers/clk/imx/clk-composite.c
> @@ -0,0 +1,181 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright 2018 NXP
> + */
> +
> +#include <linux/errno.h>
> +#include <linux/slab.h>
> +#include <linux/clk-provider.h>
> +#include <linux/clk.h>
Is this include used?
> +
> +#include "clk.h"
> +
> +#define PCG_PREDIV_SHIFT 16
> +#define PCG_PREDIV_WIDTH 3
> +#define PCG_PREDIV_MAX 8
> +
> +#define PCG_DIV_SHIFT 0
> +#define PCG_DIV_WIDTH 6
> +#define PCG_DIV_MAX 64
> +
> +#define PCG_PCS_SHIFT 24
> +#define PCG_PCS_MASK 0x7
> +
> +#define PCG_CGC_SHIFT 28
> +
> +static unsigned long imx_clk_composite_divider_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct clk_divider *divider = to_clk_divider(hw);
> + unsigned long prediv_rate;
> + unsigned int prediv_value;
> + unsigned int div_value;
> +
> + prediv_value = clk_readl(divider->reg) >> divider->shift;
> + prediv_value &= clk_div_mask(divider->width);
> +
> + prediv_rate = divider_recalc_rate(hw, parent_rate, prediv_value,
> + NULL, divider->flags,
> + divider->width);
> +
> + div_value = clk_readl(divider->reg) >> PCG_DIV_SHIFT;
> + div_value &= clk_div_mask(PCG_DIV_WIDTH);
> +
> + return divider_recalc_rate(hw, prediv_rate, div_value, NULL,
> + divider->flags, PCG_DIV_WIDTH);
> +}
> +
> +static int imx_clk_composite_compute_dividers(unsigned long rate,
> + unsigned long parent_rate,
> + int *prediv, int *postdiv)
> +{
> + int div1, div2;
> + int error = INT_MAX;
> + int ret = -EINVAL;
> +
> + /* default values */
> + *prediv = 1;
> + *postdiv = 1;
> +
> + for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) {
> + for (div2 = 1; div2 <= PCG_DIV_MAX; div2++) {
> + int new_error = ((parent_rate / div1) / div2) - rate;
> +
> + if (abs(new_error) < abs(error)) {
> + *prediv = div1;
> + *postdiv = div2;
> + error = new_error;
> + ret = 0;
> + }
> + }
> + }
> + return ret;
> +}
> +
> +static long imx_clk_composite_divider_round_rate(struct clk_hw *hw,
> + unsigned long rate,
> + unsigned long *prate)
> +{
> + int prediv_value;
> + int div_value;
> +
> + imx_clk_composite_compute_dividers(rate, *prate,
> + &prediv_value, &div_value);
> +
> + rate = DIV_ROUND_UP_ULL((u64)*prate, prediv_value);
> + rate = DIV_ROUND_UP_ULL((u64)rate, div_value);
> +
> + return rate;
Looks the same as another patch, maybe it is?
Anyway, same nitpick about returning the DIV_ROUND_UP_ULL() result.
> +}
> +
> +static int imx_clk_composite_divider_set_rate(struct clk_hw *hw,
> + unsigned long rate,
> + unsigned long parent_rate)
> +{
> + struct clk_divider *divider = to_clk_divider(hw);
> + unsigned long flags = 0;
> + int prediv_value;
> + int div_value;
> + int ret = 0;
> + u32 val;
> +
> + ret = imx_clk_composite_compute_dividers(rate, parent_rate,
> + &prediv_value, &div_value);
> + if (ret)
> + return -EINVAL;
> +
> + spin_lock_irqsave(divider->lock, flags);
> +
> + val = clk_readl(divider->reg);
> + val &= ~((clk_div_mask(divider->width) << divider->shift) |
> + (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
> +
> + val |= (u32)(prediv_value - 1) << divider->shift;
> + val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;
> + clk_writel(val, divider->reg);
Please don't use clk_writel().
> +
> + spin_unlock_irqrestore(divider->lock, flags);
> +
> + return ret;
> +}
> +
> +static const struct clk_ops imx_clk_composite_divider_ops = {
> + .recalc_rate = imx_clk_composite_divider_recalc_rate,
> + .round_rate = imx_clk_composite_divider_round_rate,
> + .set_rate = imx_clk_composite_divider_set_rate,
> +};
> +
> +struct clk *imx_clk_composite_flags(const char *name,
> + const char **parent_names,
> + int num_parents, void __iomem *reg,
> + unsigned long flags)
> +{
> + struct clk_hw *mux_hw = NULL, *div_hw = NULL, *gate_hw = NULL;
> + struct clk_divider *div = NULL;
> + struct clk_gate *gate = NULL;
> + struct clk_mux *mux = NULL;
> + struct clk *clk = ERR_PTR(-ENOMEM);
> +
> + mux = kzalloc(sizeof(*mux), GFP_KERNEL);
> + if (!mux)
> + goto fail;
> +
> + mux_hw = &mux->hw;
> + mux->reg = reg;
> + mux->shift = PCG_PCS_SHIFT;
> + mux->mask = PCG_PCS_MASK;
> +
> + div = kzalloc(sizeof(*div), GFP_KERNEL);
> + if (!div)
> + goto fail;
> +
> + div_hw = &div->hw;
> + div->reg = reg;
> + div->shift = PCG_PREDIV_SHIFT;
> + div->width = PCG_PREDIV_WIDTH;
> + div->lock = &imx_ccm_lock;
> + div->flags = CLK_DIVIDER_ROUND_CLOSEST;
> +
> + gate = kzalloc(sizeof(*gate), GFP_KERNEL);
> + if (!gate)
> + goto fail;
> +
> + gate_hw = &gate->hw;
> + gate->reg = reg;
> + gate->bit_idx = PCG_CGC_SHIFT;
> +
> + clk = clk_register_composite(NULL, name, parent_names, num_parents,
> + mux_hw, &clk_mux_ops, div_hw,
> + &imx_clk_composite_divider_ops, gate_hw,
> + &clk_gate_ops, flags);
Didn't I already review this? I'd prefer we move this to using clk_hw
based APIs and then return the clk pointer if needed.
> + if (IS_ERR(clk))
> + goto fail;
> +
> + return clk;
> +
> +fail:
> + kfree(gate);
> + kfree(div);
> + kfree(mux);
> + return clk;
> +}
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v9 3/5] clk: imx: add SCCG PLL type
2018-09-24 10:39 ` [PATCH v9 3/5] clk: imx: add SCCG PLL type Abel Vesa
@ 2018-10-17 19:55 ` Stephen Boyd
2018-11-07 11:54 ` Abel Vesa
0 siblings, 1 reply; 23+ messages in thread
From: Stephen Boyd @ 2018-10-17 19:55 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Abel Vesa (2018-09-24 03:39:55)
> diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pll.c
> new file mode 100644
> index 0000000..a9837fa
> --- /dev/null
> +++ b/drivers/clk/imx/clk-sccg-pll.c
> @@ -0,0 +1,237 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright 2018 NXP.
> + */
> +
> +#include <linux/clk.h>
Is this include used? Otherwise should see clk-provider.h included here.
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/slab.h>
> +#include <linux/delay.h>
> +#include <linux/bitfield.h>
> +
> +#include "clk.h"
> +
> +/* PLL CFGs */
> +#define PLL_CFG0 0x0
> +#define PLL_CFG1 0x4
> +#define PLL_CFG2 0x8
> +
> +#define PLL_DIVF1_MASK GENMASK(18, 13)
> +#define PLL_DIVF2_MASK GENMASK(12, 7)
> +#define PLL_DIVR1_MASK GENMASK(27, 25)
> +#define PLL_DIVR2_MASK GENMASK(24, 19)
> +#define PLL_REF_MASK GENMASK(2, 0)
> +
> +#define PLL_LOCK_MASK BIT(31)
> +#define PLL_PD_MASK BIT(7)
> +
> +#define OSC_25M 25000000
> +#define OSC_27M 27000000
> +
> +#define PLL_SCCG_LOCK_TIMEOUT 70
> +
> +struct clk_sccg_pll {
> + struct clk_hw hw;
> + void __iomem *base;
> +};
> +
> +#define to_clk_sccg_pll(_hw) container_of(_hw, struct clk_sccg_pll, hw)
> +
> +static int clk_pll_wait_lock(struct clk_sccg_pll *pll)
> +{
> + u32 val;
> +
> + return readl_poll_timeout(pll->base, val, val & PLL_LOCK_MASK, 0,
> + PLL_SCCG_LOCK_TIMEOUT);
> +}
> +
> +static int clk_pll1_is_prepared(struct clk_hw *hw)
> +{
> + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
> + u32 val;
> +
> + val = readl_relaxed(pll->base + PLL_CFG0);
> + return (val & PLL_PD_MASK) ? 0 : 1;
> +}
> +
> +static unsigned long clk_pll1_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
> + u32 val, divf;
> +
> + val = readl_relaxed(pll->base + PLL_CFG2);
> + divf = FIELD_GET(PLL_DIVF1_MASK, val);
> +
> + return parent_rate * 2 * (divf + 1);
> +}
> +
> +static long clk_pll1_round_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long *prate)
> +{
> + unsigned long parent_rate = *prate;
> + u32 div;
> +
> + div = rate / (parent_rate * 2);
Can parent_rate be 0?
> +
> + return parent_rate * div * 2;
> +}
> +
> +static int clk_pll1_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
> + u32 val;
> + u32 divf;
> +
> + divf = rate / (parent_rate * 2);
Can parent_rate be 0?
> +
> + val = readl_relaxed(pll->base + PLL_CFG2);
> + val &= ~PLL_DIVF1_MASK;
> + val |= FIELD_PREP(PLL_DIVF1_MASK, divf - 1);
> + writel_relaxed(val, pll->base + PLL_CFG2);
> +
> + return clk_pll_wait_lock(pll);
> +}
> +
> +static int clk_pll1_prepare(struct clk_hw *hw)
> +{
> + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
> + u32 val;
> +
> + val = readl_relaxed(pll->base + PLL_CFG0);
> + val &= ~PLL_PD_MASK;
> + writel_relaxed(val, pll->base + PLL_CFG0);
> +
> + return clk_pll_wait_lock(pll);
> +}
> +
> +static void clk_pll1_unprepare(struct clk_hw *hw)
> +{
> + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
> + u32 val;
> +
> + val = readl_relaxed(pll->base + PLL_CFG0);
> + val |= PLL_PD_MASK;
> + writel_relaxed(val, pll->base + PLL_CFG0);
> +
> +}
> +
> +static unsigned long clk_pll2_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
> + u32 val, ref, divr1, divf1, divr2, divf2;
> + u64 temp64;
> +
> + val = readl_relaxed(pll->base + PLL_CFG0);
> + switch (FIELD_GET(PLL_REF_MASK, val)) {
> + case 0:
> + ref = OSC_25M;
> + break;
> + case 1:
> + ref = OSC_27M;
> + break;
> + default:
> + ref = OSC_25M;
Does this information not come through 'parent_rate'?
> + break;
> + }
> +
> + val = readl_relaxed(pll->base + PLL_CFG2);
> + divr1 = FIELD_GET(PLL_DIVR1_MASK, val);
> + divr2 = FIELD_GET(PLL_DIVR2_MASK, val);
> + divf1 = FIELD_GET(PLL_DIVF1_MASK, val);
> + divf2 = FIELD_GET(PLL_DIVF2_MASK, val);
> +
> + temp64 = ref * 2;
> + temp64 *= (divf1 + 1) * (divf2 + 1);
> +
> + do_div(temp64, (divr1 + 1) * (divr2 + 1));
Nitpicks: A comment with the equation may be helpful to newcomers.
> +
> + return (unsigned long)temp64;
Drop useless cast please.
> +}
> +
> +static long clk_pll2_round_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long *prate)
> +{
> + u32 div;
> + unsigned long parent_rate = *prate;
> +
> + div = rate / (parent_rate);
> +
> + return parent_rate * div;
> +}
> +
> +static int clk_pll2_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + u32 val;
> + u32 divf;
> + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
> +
> + divf = rate / (parent_rate);
Drop useless parenthesis please.
> +
> + val = readl_relaxed(pll->base + PLL_CFG2);
> + val &= ~PLL_DIVF2_MASK;
> + val |= FIELD_PREP(PLL_DIVF2_MASK, divf - 1);
> + writel_relaxed(val, pll->base + PLL_CFG2);
> +
> + return clk_pll_wait_lock(pll);
> +}
> +
> +static const struct clk_ops clk_sccg_pll1_ops = {
> + .is_prepared = clk_pll1_is_prepared,
> + .recalc_rate = clk_pll1_recalc_rate,
> + .round_rate = clk_pll1_round_rate,
> + .set_rate = clk_pll1_set_rate,
> +};
> +
> +static const struct clk_ops clk_sccg_pll2_ops = {
> + .prepare = clk_pll1_prepare,
> + .unprepare = clk_pll1_unprepare,
> + .recalc_rate = clk_pll2_recalc_rate,
> + .round_rate = clk_pll2_round_rate,
> + .set_rate = clk_pll2_set_rate,
> +};
> +
> +struct clk *imx_clk_sccg_pll(const char *name,
> + const char *parent_name,
> + void __iomem *base,
> + enum imx_sccg_pll_type pll_type)
> +{
> + struct clk_sccg_pll *pll;
> + struct clk *clk;
> + struct clk_init_data init;
> +
> + pll = kzalloc(sizeof(*pll), GFP_KERNEL);
> + if (!pll)
> + return ERR_PTR(-ENOMEM);
> +
> + pll->base = base;
> + init.name = name;
> + switch (pll_type) {
> + case SCCG_PLL1:
> + init.ops = &clk_sccg_pll1_ops;
> + break;
> + case SCCG_PLL2:
> + init.ops = &clk_sccg_pll2_ops;
> + break;
> + default:
> + kfree(pll);
> + return ERR_PTR(-EINVAL);
Do this case statement before allocating? So that kfree() isn't required
here?
> + }
> +
> + init.flags = 0;
> + init.parent_names = &parent_name;
> + init.num_parents = 1;
> +
> + pll->hw.init = &init;
> +
> + clk = clk_register(NULL, &pll->hw);
Any chance to use clk_hw based registration APIs?
> + if (IS_ERR(clk))
> + kfree(pll);
> +
> + return clk;
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v9 2/5] clk: imx: add fractional PLL output clock
2018-09-24 10:39 ` [PATCH v9 2/5] clk: imx: add fractional PLL output clock Abel Vesa
@ 2018-10-17 19:59 ` Stephen Boyd
2018-11-07 12:25 ` Abel Vesa
0 siblings, 1 reply; 23+ messages in thread
From: Stephen Boyd @ 2018-10-17 19:59 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Abel Vesa (2018-09-24 03:39:54)
> From: Lucas Stach <l.stach@pengutronix.de>
>
> This is a new clock type introduced on i.MX8.
Ok, what's the clock type? Add another sentence please.
>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
[..]
> diff --git a/drivers/clk/imx/clk-frac-pll.c b/drivers/clk/imx/clk-frac-pll.c
> new file mode 100644
> index 0000000..030df76
> --- /dev/null
> +++ b/drivers/clk/imx/clk-frac-pll.c
> @@ -0,0 +1,215 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright 2018 NXP.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/jiffies.h>
Is this used for something?
> +#include <linux/slab.h>
> +#include <linux/bitfield.h>
> +
> +#include "clk.h"
[...]
> +
> +static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct clk_frac_pll *pll = to_clk_frac_pll(hw);
> + u32 val, divff, divfi, divq;
> + u64 temp64;
> +
> + val = readl_relaxed(pll->base + PLL_CFG0);
> + divq = ((val & PLL_OUTPUT_DIV_MASK) + 1) * 2;
> + val = readl_relaxed(pll->base + PLL_CFG1);
> + divff = FIELD_GET(PLL_FRAC_DIV_MASK, val);
> + divfi = (val & PLL_INT_DIV_MASK);
Nitpick: Drop useless parenthesis please.
> +
> + temp64 = (u64)parent_rate * 8;
> + temp64 *= divff;
> + do_div(temp64, PLL_FRAC_DENOM);
> + temp64 /= divq;
> +
> + return parent_rate * 8 * (divfi + 1) / divq + (unsigned long)temp64;
> +}
> +
> +static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long *prate)
> +{
> + unsigned long parent_rate = *prate;
> + u32 divff, divfi;
> + u64 temp64;
> +
> + parent_rate *= 8;
And parent_rate can't overflow if it's a u32? Maybe it could be a u64 so
that we don't need casting later on in this function.
> + rate *= 2;
> + divfi = rate / parent_rate;
> + temp64 = (u64)(rate - divfi * parent_rate);
> + temp64 *= PLL_FRAC_DENOM;
> + do_div(temp64, parent_rate);
> + divff = temp64;
> +
> + temp64 = (u64)parent_rate;
> + temp64 *= divff;
> + do_div(temp64, PLL_FRAC_DENOM);
> +
> + return (parent_rate * divfi + (unsigned long)temp64) / 2;
> +}
> +
> +/*
> + * To simplify the clock calculation, we can keep the 'PLL_OUTPUT_VAL' at zero
> + * (means the PLL output will be divided by 2). So the PLL output can use
> + * the below formula:
> + * pllout = parent_rate * 8 / 2 * DIVF_VAL;
> + * where DIVF_VAL = 1 + DIVFI + DIVFF / 2^24.
> + */
> +static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + struct clk_frac_pll *pll = to_clk_frac_pll(hw);
> + u32 val, divfi, divff;
> + u64 temp64;
> + int ret;
> +
> + parent_rate *= 8;
> + rate *= 2;
> + divfi = rate / parent_rate;
> + temp64 = (u64) (rate - divfi * parent_rate);
> + temp64 *= PLL_FRAC_DENOM;
> + do_div(temp64, parent_rate);
> + divff = temp64;
> +
> + val = readl_relaxed(pll->base + PLL_CFG1);
> + val &= ~(PLL_FRAC_DIV_MASK | PLL_INT_DIV_MASK);
> + val |= ((divff << 7) | (divfi - 1));
Nitpick: Drop the extra parenthesis please.
> + writel_relaxed(val, pll->base + PLL_CFG1);
> +
> + val = readl_relaxed(pll->base + PLL_CFG0);
> + val &= ~0x1f;
> + writel_relaxed(val, pll->base + PLL_CFG0);
> +
> + /* Set the NEV_DIV_VAL to reload the DIVFI and DIVFF */
> + val = readl_relaxed(pll->base + PLL_CFG0);
> + val |= PLL_NEWDIV_VAL;
> + writel_relaxed(val, pll->base + PLL_CFG0);
> +
> + ret = clk_wait_ack(pll);
> +
> + /* clear the NEV_DIV_VAL */
> + val = readl_relaxed(pll->base + PLL_CFG0);
> + val &= ~PLL_NEWDIV_VAL;
> + writel_relaxed(val, pll->base + PLL_CFG0);
> +
> + return ret;
> +}
> +
> +static const struct clk_ops clk_frac_pll_ops = {
> + .prepare = clk_pll_prepare,
> + .unprepare = clk_pll_unprepare,
> + .is_prepared = clk_pll_is_prepared,
> + .recalc_rate = clk_pll_recalc_rate,
> + .round_rate = clk_pll_round_rate,
> + .set_rate = clk_pll_set_rate,
> +};
> +
> +struct clk *imx_clk_frac_pll(const char *name, const char *parent_name,
> + void __iomem *base)
> +{
> + struct clk_init_data init;
> + struct clk_frac_pll *pll;
> + struct clk *clk;
> +
> + pll = kzalloc(sizeof(*pll), GFP_KERNEL);
> + if (!pll)
> + return ERR_PTR(-ENOMEM);
> +
> + pll->base = base;
> + init.name = name;
> + init.ops = &clk_frac_pll_ops;
> + init.flags = 0;
> + init.parent_names = &parent_name;
> + init.num_parents = 1;
> +
> + pll->hw.init = &init;
> +
> + clk = clk_register(NULL, &pll->hw);
clk_hw based please.
> + if (IS_ERR(clk))
> + kfree(pll);
> +
> + return clk;
> +}
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v9 4/5] clk: imx: add imx composite clock
2018-10-17 19:51 ` Stephen Boyd
@ 2018-10-18 9:57 ` Abel Vesa
0 siblings, 0 replies; 23+ messages in thread
From: Abel Vesa @ 2018-10-18 9:57 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Oct 17, 2018 at 12:51:35PM -0700, Stephen Boyd wrote:
> Quoting Abel Vesa (2018-09-24 03:39:56)
> > + clk = clk_register_composite(NULL, name, parent_names, num_parents,
> > + mux_hw, &clk_mux_ops, div_hw,
> > + &imx_clk_composite_divider_ops, gate_hw,
> > + &clk_gate_ops, flags);
>
> Didn't I already review this? I'd prefer we move this to using clk_hw
> based APIs and then return the clk pointer if needed.
>
Yes, you reviewed the v11, so you can ignore this 9th version.
I'll implement all the comments from you in the 12th version before sending.
I'll also switch all clk based register functions call sites
to clk_hw based ones.
Thanks
> > + if (IS_ERR(clk))
> > + goto fail;
> > +
> > + return clk;
> > +
> > +fail:
> > + kfree(gate);
> > + kfree(div);
> > + kfree(mux);
> > + return clk;
> > +}
--
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v9 3/5] clk: imx: add SCCG PLL type
2018-10-17 19:55 ` Stephen Boyd
@ 2018-11-07 11:54 ` Abel Vesa
2018-11-07 19:01 ` Stephen Boyd
0 siblings, 1 reply; 23+ messages in thread
From: Abel Vesa @ 2018-11-07 11:54 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Oct 17, 2018 at 12:55:52PM -0700, Stephen Boyd wrote:
> Quoting Abel Vesa (2018-09-24 03:39:55)
> > diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pll.c
> > new file mode 100644
> > index 0000000..a9837fa
> > --- /dev/null
> > +++ b/drivers/clk/imx/clk-sccg-pll.c
> > @@ -0,0 +1,237 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright 2018 NXP.
> > + */
> > +
> > +#include <linux/clk.h>
>
> Is this include used? Otherwise should see clk-provider.h included here.
>
Fixed in the next version.
> > +#include <linux/err.h>
> > +#include <linux/io.h>
> > +#include <linux/iopoll.h>
> > +#include <linux/slab.h>
> > +#include <linux/delay.h>
> > +#include <linux/bitfield.h>
> > +
> > +#include "clk.h"
> > +
> > +/* PLL CFGs */
> > +#define PLL_CFG0 0x0
> > +#define PLL_CFG1 0x4
> > +#define PLL_CFG2 0x8
> > +
> > +#define PLL_DIVF1_MASK GENMASK(18, 13)
> > +#define PLL_DIVF2_MASK GENMASK(12, 7)
> > +#define PLL_DIVR1_MASK GENMASK(27, 25)
> > +#define PLL_DIVR2_MASK GENMASK(24, 19)
> > +#define PLL_REF_MASK GENMASK(2, 0)
> > +
> > +#define PLL_LOCK_MASK BIT(31)
> > +#define PLL_PD_MASK BIT(7)
> > +
> > +#define OSC_25M 25000000
> > +#define OSC_27M 27000000
> > +
> > +#define PLL_SCCG_LOCK_TIMEOUT 70
> > +
> > +struct clk_sccg_pll {
> > + struct clk_hw hw;
> > + void __iomem *base;
> > +};
> > +
> > +#define to_clk_sccg_pll(_hw) container_of(_hw, struct clk_sccg_pll, hw)
> > +
> > +static int clk_pll_wait_lock(struct clk_sccg_pll *pll)
> > +{
> > + u32 val;
> > +
> > + return readl_poll_timeout(pll->base, val, val & PLL_LOCK_MASK, 0,
> > + PLL_SCCG_LOCK_TIMEOUT);
> > +}
> > +
> > +static int clk_pll1_is_prepared(struct clk_hw *hw)
> > +{
> > + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
> > + u32 val;
> > +
> > + val = readl_relaxed(pll->base + PLL_CFG0);
> > + return (val & PLL_PD_MASK) ? 0 : 1;
> > +}
> > +
> > +static unsigned long clk_pll1_recalc_rate(struct clk_hw *hw,
> > + unsigned long parent_rate)
> > +{
> > + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
> > + u32 val, divf;
> > +
> > + val = readl_relaxed(pll->base + PLL_CFG2);
> > + divf = FIELD_GET(PLL_DIVF1_MASK, val);
> > +
> > + return parent_rate * 2 * (divf + 1);
> > +}
> > +
> > +static long clk_pll1_round_rate(struct clk_hw *hw, unsigned long rate,
> > + unsigned long *prate)
> > +{
> > + unsigned long parent_rate = *prate;
> > + u32 div;
> > +
> > + div = rate / (parent_rate * 2);
>
> Can parent_rate be 0?
>
Fixed in the next version.
> > +
> > + return parent_rate * div * 2;
> > +}
> > +
> > +static int clk_pll1_set_rate(struct clk_hw *hw, unsigned long rate,
> > + unsigned long parent_rate)
> > +{
> > + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
> > + u32 val;
> > + u32 divf;
> > +
> > + divf = rate / (parent_rate * 2);
>
> Can parent_rate be 0?
>
Fixed in the next version.
> > +
> > + val = readl_relaxed(pll->base + PLL_CFG2);
> > + val &= ~PLL_DIVF1_MASK;
> > + val |= FIELD_PREP(PLL_DIVF1_MASK, divf - 1);
> > + writel_relaxed(val, pll->base + PLL_CFG2);
> > +
> > + return clk_pll_wait_lock(pll);
> > +}
> > +
> > +static int clk_pll1_prepare(struct clk_hw *hw)
> > +{
> > + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
> > + u32 val;
> > +
> > + val = readl_relaxed(pll->base + PLL_CFG0);
> > + val &= ~PLL_PD_MASK;
> > + writel_relaxed(val, pll->base + PLL_CFG0);
> > +
> > + return clk_pll_wait_lock(pll);
> > +}
> > +
> > +static void clk_pll1_unprepare(struct clk_hw *hw)
> > +{
> > + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
> > + u32 val;
> > +
> > + val = readl_relaxed(pll->base + PLL_CFG0);
> > + val |= PLL_PD_MASK;
> > + writel_relaxed(val, pll->base + PLL_CFG0);
> > +
> > +}
> > +
> > +static unsigned long clk_pll2_recalc_rate(struct clk_hw *hw,
> > + unsigned long parent_rate)
> > +{
> > + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
> > + u32 val, ref, divr1, divf1, divr2, divf2;
> > + u64 temp64;
> > +
> > + val = readl_relaxed(pll->base + PLL_CFG0);
> > + switch (FIELD_GET(PLL_REF_MASK, val)) {
> > + case 0:
> > + ref = OSC_25M;
> > + break;
> > + case 1:
> > + ref = OSC_27M;
> > + break;
> > + default:
> > + ref = OSC_25M;
>
> Does this information not come through 'parent_rate'?
>
No. So basically both pll1 and pll2 and the divider after it form together this SCCG:
https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834
See: Figure 5-8. SSCG PLL Block Diagram
We're basically reading the input of the pll 1 in order to compute the output of the entire SCCG.
I know it's a mess. I'm working on cleaning it up, but for now we need this in in order to boot up.
> > + break;
> > + }
> > +
> > + val = readl_relaxed(pll->base + PLL_CFG2);
> > + divr1 = FIELD_GET(PLL_DIVR1_MASK, val);
> > + divr2 = FIELD_GET(PLL_DIVR2_MASK, val);
> > + divf1 = FIELD_GET(PLL_DIVF1_MASK, val);
> > + divf2 = FIELD_GET(PLL_DIVF2_MASK, val);
> > +
> > + temp64 = ref * 2;
> > + temp64 *= (divf1 + 1) * (divf2 + 1);
> > +
> > + do_div(temp64, (divr1 + 1) * (divr2 + 1));
>
> Nitpicks: A comment with the equation may be helpful to newcomers.
Since the SCCG is contructed by multiple different types of clocks here, the equation doesn't help
since it is spread in all constructing blocks.
>
> > +
> > + return (unsigned long)temp64;
>
> Drop useless cast please.
>
Fixed in the next version.
> > +}
> > +
> > +static long clk_pll2_round_rate(struct clk_hw *hw, unsigned long rate,
> > + unsigned long *prate)
> > +{
> > + u32 div;
> > + unsigned long parent_rate = *prate;
> > +
> > + div = rate / (parent_rate);
> > +
> > + return parent_rate * div;
> > +}
> > +
> > +static int clk_pll2_set_rate(struct clk_hw *hw, unsigned long rate,
> > + unsigned long parent_rate)
> > +{
> > + u32 val;
> > + u32 divf;
> > + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
> > +
> > + divf = rate / (parent_rate);
>
> Drop useless parenthesis please.
>
Fixed in the next version.
> > +
> > + val = readl_relaxed(pll->base + PLL_CFG2);
> > + val &= ~PLL_DIVF2_MASK;
> > + val |= FIELD_PREP(PLL_DIVF2_MASK, divf - 1);
> > + writel_relaxed(val, pll->base + PLL_CFG2);
> > +
> > + return clk_pll_wait_lock(pll);
> > +}
> > +
> > +static const struct clk_ops clk_sccg_pll1_ops = {
> > + .is_prepared = clk_pll1_is_prepared,
> > + .recalc_rate = clk_pll1_recalc_rate,
> > + .round_rate = clk_pll1_round_rate,
> > + .set_rate = clk_pll1_set_rate,
> > +};
> > +
> > +static const struct clk_ops clk_sccg_pll2_ops = {
> > + .prepare = clk_pll1_prepare,
> > + .unprepare = clk_pll1_unprepare,
> > + .recalc_rate = clk_pll2_recalc_rate,
> > + .round_rate = clk_pll2_round_rate,
> > + .set_rate = clk_pll2_set_rate,
> > +};
> > +
> > +struct clk *imx_clk_sccg_pll(const char *name,
> > + const char *parent_name,
> > + void __iomem *base,
> > + enum imx_sccg_pll_type pll_type)
> > +{
> > + struct clk_sccg_pll *pll;
> > + struct clk *clk;
> > + struct clk_init_data init;
> > +
> > + pll = kzalloc(sizeof(*pll), GFP_KERNEL);
> > + if (!pll)
> > + return ERR_PTR(-ENOMEM);
> > +
> > + pll->base = base;
> > + init.name = name;
> > + switch (pll_type) {
> > + case SCCG_PLL1:
> > + init.ops = &clk_sccg_pll1_ops;
> > + break;
> > + case SCCG_PLL2:
> > + init.ops = &clk_sccg_pll2_ops;
> > + break;
> > + default:
> > + kfree(pll);
> > + return ERR_PTR(-EINVAL);
>
> Do this case statement before allocating? So that kfree() isn't required
> here?
>
Fixed in the next version.
> > + }
> > +
> > + init.flags = 0;
> > + init.parent_names = &parent_name;
> > + init.num_parents = 1;
> > +
> > + pll->hw.init = &init;
> > +
> > + clk = clk_register(NULL, &pll->hw);
>
> Any chance to use clk_hw based registration APIs?
>
Fixed in the next version.
> > + if (IS_ERR(clk))
> > + kfree(pll);
> > +
> > + return clk;
--
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v9 5/5] clk: imx: add clock driver for i.MX8MQ CCM
2018-10-17 19:44 ` Stephen Boyd
@ 2018-11-07 12:09 ` Abel Vesa
0 siblings, 0 replies; 23+ messages in thread
From: Abel Vesa @ 2018-11-07 12:09 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Oct 17, 2018 at 12:44:52PM -0700, Stephen Boyd wrote:
> Quoting Abel Vesa (2018-09-24 03:39:57)
> > From: Lucas Stach <l.stach@pengutronix.de>
> >
> > Add driver for the Clock Control Module found on i.MX8MQ.
> >
> > This is largely based on the downstream driver from Anson Huang and
> > Bai Ping at NXP, plus the imx composite clock from Abel Vesa at NXP,
> > with only some small adaptions to mainline from me.
>
> Can you point to the downstream driver so we can know what small
> adaptations were made.
>
It's was implemented originally in NXP's internal tree. The adaptations
to the initial implementation are not that small anymore. I even changed the
authorship since it has changed quite a lot compared to the initial version.
> >
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> > ---
> > drivers/clk/imx/Makefile | 1 +
> > drivers/clk/imx/clk-imx8mq.c | 602 +++++++++++++++++++++++++++++++++++++++++++
> > drivers/clk/imx/clk.h | 36 +++
> > 3 files changed, 639 insertions(+)
> > create mode 100644 drivers/clk/imx/clk-imx8mq.c
> >
> > diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
> > index 4fabb0a..64e695c 100644
> > --- a/drivers/clk/imx/Makefile
> > +++ b/drivers/clk/imx/Makefile
> > @@ -30,3 +30,4 @@ obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o
> > obj-$(CONFIG_SOC_IMX6UL) += clk-imx6ul.o
> > obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o
> > obj-$(CONFIG_SOC_VF610) += clk-vf610.o
> > +obj-$(CONFIG_SOC_IMX8MQ) += clk-imx8mq.o
>
> Please try to keep this alphabetical on CONFIG symbol.
>
Fixed in the next version.
> > diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
> > new file mode 100644
> > index 0000000..aadb523
> > --- /dev/null
> > +++ b/drivers/clk/imx/clk-imx8mq.c
> > @@ -0,0 +1,602 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright 2018 NXP.
> > + * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
> > + */
> > +
> > +#include <dt-bindings/clock/imx8mq-clock.h>
> > +#include <linux/clk.h>
> > +#include <linux/clkdev.h>
>
> Are these two includes used?
>
clkdev.h include is removed in the next version.
clk.h is needed by of_clk_get_by_name.
> > +#include <linux/err.h>
> > +#include <linux/init.h>
> > +#include <linux/io.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/types.h>
> > +
> > +#include "clk.h"
> > +
> > +static u32 share_count_sai1;
> > +static u32 share_count_sai2;
> > +static u32 share_count_sai3;
> > +static u32 share_count_sai4;
> > +static u32 share_count_sai5;
> > +static u32 share_count_sai6;
> > +static u32 share_count_dcss;
> > +static u32 share_count_nand;
> > +
> [...]
> > +
> > +static const char *imx8mq_ecspi3_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
> > + "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
> > +static const char *imx8mq_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
> > +
> > +static const char *imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_400m", "sys2_pll_166m", "audio_pll1_out",
> > + "video_pll1_out", "ckil", };
> > +
> > +static struct clk_onecell_data clk_data;
> > +
> > +static void __init imx8mq_clocks_init(struct device_node *ccm_node)
> > +{
> > + struct device_node *np;
> > + void __iomem *base;
> > + int i;
> > +
> > + clks[IMX8MQ_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
> > + clks[IMX8MQ_CLK_32K] = of_clk_get_by_name(ccm_node, "ckil");
> > + clks[IMX8MQ_CLK_25M] = of_clk_get_by_name(ccm_node, "osc_25m");
> > + clks[IMX8MQ_CLK_27M] = of_clk_get_by_name(ccm_node, "osc_27m");
> > + clks[IMX8MQ_CLK_EXT1] = of_clk_get_by_name(ccm_node, "clk_ext1");
> > + clks[IMX8MQ_CLK_EXT2] = of_clk_get_by_name(ccm_node, "clk_ext2");
> > + clks[IMX8MQ_CLK_EXT3] = of_clk_get_by_name(ccm_node, "clk_ext3");
> > + clks[IMX8MQ_CLK_EXT4] = of_clk_get_by_name(ccm_node, "clk_ext4");
> > +
> > + np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop");
> > + base = of_iomap(np, 0);
> > + WARN_ON(!base);
>
> And if that fails? return without continuing?
>
Fixed in the next version.
> > +
> > + clks[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
> > + clks[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
> > + clks[IMX8MQ_VPU_PLL_REF_SEL] = imx_clk_mux("vpu_pll_ref_sel", base + 0x20, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
> > + clks[IMX8MQ_AUDIO_PLL1_REF_SEL] = imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
> [..]
> > + clks[IMX8MQ_CLK_DSI_CORE] = imx_clk_composite("dsi_core", imx8mq_dsi_core_sels, base + 0xbb00);
> > + clks[IMX8MQ_CLK_DSI_PHY_REF] = imx_clk_composite("dsi_phy_ref", imx8mq_dsi_phy_sels, base + 0xbb80);
> > + clks[IMX8MQ_CLK_DSI_DBI] = imx_clk_composite("dsi_dbi", imx8mq_dsi_dbi_sels, base + 0xbc00);
> > + clks[IMX8MQ_CLK_DSI_ESC] = imx_clk_composite("dsi_esc", imx8mq_dsi_esc_sels, base + 0xbc80);
> > + clks[IMX8MQ_CLK_DSI_AHB] = imx_clk_composite("dsi_ahb", imx8mq_dsi_ahb_sels, base + 0x9200);
> > + clks[IMX8MQ_CLK_CSI1_CORE] = imx_clk_composite("csi1_core", imx8mq_csi1_core_sels, base + 0xbd00);
> > + clks[IMX8MQ_CLK_CSI1_PHY_REF] = imx_clk_composite("csi1_phy_ref", imx8mq_csi1_phy_sels, base + 0xbd80);
> > + clks[IMX8MQ_CLK_CSI1_ESC] = imx_clk_composite("csi1_esc", imx8mq_csi1_esc_sels, base + 0xbe00);
> > + clks[IMX8MQ_CLK_CSI2_CORE] = imx_clk_composite("csi2_core", imx8mq_csi2_core_sels, base + 0xbe80);
> > + clks[IMX8MQ_CLK_CSI2_PHY_REF] = imx_clk_composite("csi2_phy_ref", imx8mq_csi2_phy_sels, base + 0xbf00);
> > + clks[IMX8MQ_CLK_CSI2_ESC] = imx_clk_composite("csi2_esc", imx8mq_csi2_esc_sels, base + 0xbf80);
> > + clks[IMX8MQ_CLK_PCIE2_CTRL] = imx_clk_composite("pcie2_ctrl", imx8mq_pcie2_ctrl_sels, base + 0xc000);
> > + clks[IMX8MQ_CLK_PCIE2_PHY] = imx_clk_composite("pcie2_phy", imx8mq_pcie2_phy_sels, base + 0xc080);
> > + clks[IMX8MQ_CLK_PCIE2_AUX] = imx_clk_composite("pcie2_aux", imx8mq_pcie2_aux_sels, base + 0xc100);
> > + clks[IMX8MQ_CLK_ECSPI3] = imx_clk_composite("ecspi3", imx8mq_ecspi3_sels, base + 0xc180);
> > +
> > + /*FIXME, the doc is not ready now */
>
> What does this mean?
>
The comment does not apply anymore. It is remoed in the next version.
When the driver was initially implemented, the specs doc was not ready.
> > + clks[IMX8MQ_CLK_ECSPI1_ROOT] = imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0);
> > + clks[IMX8MQ_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0);
> > + clks[IMX8MQ_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0);
> > + clks[IMX8MQ_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0);
> > + clks[IMX8MQ_CLK_GPT1_ROOT] = imx_clk_gate4("gpt1_root_clk", "gpt1", base + 0x4100, 0);
> [...]
> > +
> > + clks[IMX8MQ_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc_25m", 1, 8);
> > + clks[IMX8MQ_CLK_DRAM_ALT_ROOT] = imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4);
> > +
> > + for (i = 0; i < IMX8MQ_CLK_END; i++)
> > + if (IS_ERR(clks[i]))
> > + pr_err("i.MX8mq clk %u register failed with %ld\n",
> > + i, PTR_ERR(clks[i]));
> > +
> > + clk_data.clks = clks;
> > + clk_data.clk_num = ARRAY_SIZE(clks);
> > + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
>
> Any chance to move to using clk_hw based provider and clk registration
> APIs?
>
Since a lot of the imx clocks that are already upstream and since it's not
quite a small change, I would prefer if this would go in as is. I intend to
make the switch to clk_hw based registration later, but it will take some time
for me to get that ready and that would delay the upstream of imx8mq drivers
even more.
All the new clock types introduced now are clk_hw based.
> > +
> > + clk_set_parent(clks[IMX8MQ_CLK_AHB], clks[IMX8MQ_SYS1_PLL_133M]);
> > + clk_set_parent(clks[IMX8MQ_CLK_NAND_USDHC_BUS], clks[IMX8MQ_SYS1_PLL_266M]);
> > + clk_set_parent(clks[IMX8MQ_CLK_AUDIO_AHB], clks[IMX8MQ_SYS2_PLL_500M]);
> > +
> > + /* config video_pll1 clock */
> > + clk_set_parent(clks[IMX8MQ_VIDEO_PLL1_REF_SEL], clks[IMX8MQ_CLK_27M]);
> > + clk_set_rate(clks[IMX8MQ_VIDEO_PLL1], 593999999);
> > +
> > + /* increase NOC clock to achieve best DDR access performance */
> > + clk_set_rate(clks[IMX8MQ_CLK_NOC], clk_get_rate(clks[IMX8MQ_SYS1_PLL_800M]));
> > +
> > + /* set pcie root's parent clk source */
> > + clk_set_parent(clks[IMX8MQ_CLK_PCIE1_CTRL], clks[IMX8MQ_SYS2_PLL_250M]);
> > + clk_set_parent(clks[IMX8MQ_CLK_PCIE1_PHY], clks[IMX8MQ_SYS2_PLL_100M]);
> > + clk_set_parent(clks[IMX8MQ_CLK_PCIE2_CTRL], clks[IMX8MQ_SYS2_PLL_250M]);
> > + clk_set_parent(clks[IMX8MQ_CLK_PCIE2_PHY], clks[IMX8MQ_SYS2_PLL_100M]);
> > +
> > + clk_set_parent(clks[IMX8MQ_CLK_CSI1_CORE], clks[IMX8MQ_SYS1_PLL_266M]);
> > + clk_set_parent(clks[IMX8MQ_CLK_CSI1_PHY_REF], clks[IMX8MQ_SYS2_PLL_1000M]);
> > + clk_set_parent(clks[IMX8MQ_CLK_CSI1_ESC], clks[IMX8MQ_SYS1_PLL_800M]);
> > + clk_set_parent(clks[IMX8MQ_CLK_CSI2_CORE], clks[IMX8MQ_SYS1_PLL_266M]);
> > + clk_set_parent(clks[IMX8MQ_CLK_CSI2_PHY_REF], clks[IMX8MQ_SYS2_PLL_1000M]);
> > + clk_set_parent(clks[IMX8MQ_CLK_CSI2_ESC], clks[IMX8MQ_SYS1_PLL_800M]);
>
> Can this be done with assigned clock parents and assigned clock rates?
>
Fair enough. Removed entirely in the next version. Each driver will set its
own rate and parent in dts later on.
> > +}
> > +
> > +CLK_OF_DECLARE(imx8mq, "fsl,imx8mq-ccm", imx8mq_clocks_init);
>
> Can you please add a comment indicating why this can't be done with a
> platform driver, or convert this to be a platform driver?
>
Good point. Switched to platform driver.
Thanks
--
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v9 2/5] clk: imx: add fractional PLL output clock
2018-10-17 19:59 ` Stephen Boyd
@ 2018-11-07 12:25 ` Abel Vesa
0 siblings, 0 replies; 23+ messages in thread
From: Abel Vesa @ 2018-11-07 12:25 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Oct 17, 2018 at 12:59:44PM -0700, Stephen Boyd wrote:
> Quoting Abel Vesa (2018-09-24 03:39:54)
> > From: Lucas Stach <l.stach@pengutronix.de>
> >
> > This is a new clock type introduced on i.MX8.
>
> Ok, what's the clock type? Add another sentence please.
>
Added in the next version a link with the pdf describing the hardware
and specified in the commit message that is a fractional clock.
> >
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> [..]
> > diff --git a/drivers/clk/imx/clk-frac-pll.c b/drivers/clk/imx/clk-frac-pll.c
> > new file mode 100644
> > index 0000000..030df76
> > --- /dev/null
> > +++ b/drivers/clk/imx/clk-frac-pll.c
> > @@ -0,0 +1,215 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright 2018 NXP.
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/err.h>
> > +#include <linux/io.h>
> > +#include <linux/iopoll.h>
> > +#include <linux/jiffies.h>
>
> Is this used for something?
>
Removed in the next version.
> > +#include <linux/slab.h>
> > +#include <linux/bitfield.h>
> > +
> > +#include "clk.h"
> [...]
> > +
> > +static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
> > + unsigned long parent_rate)
> > +{
> > + struct clk_frac_pll *pll = to_clk_frac_pll(hw);
> > + u32 val, divff, divfi, divq;
> > + u64 temp64;
> > +
> > + val = readl_relaxed(pll->base + PLL_CFG0);
> > + divq = ((val & PLL_OUTPUT_DIV_MASK) + 1) * 2;
> > + val = readl_relaxed(pll->base + PLL_CFG1);
> > + divff = FIELD_GET(PLL_FRAC_DIV_MASK, val);
> > + divfi = (val & PLL_INT_DIV_MASK);
>
> Nitpick: Drop useless parenthesis please.
>
Removed in the next version.
> > +
> > + temp64 = (u64)parent_rate * 8;
> > + temp64 *= divff;
> > + do_div(temp64, PLL_FRAC_DENOM);
> > + temp64 /= divq;
> > +
> > + return parent_rate * 8 * (divfi + 1) / divq + (unsigned long)temp64;
> > +}
> > +
> > +static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> > + unsigned long *prate)
> > +{
> > + unsigned long parent_rate = *prate;
> > + u32 divff, divfi;
> > + u64 temp64;
> > +
> > + parent_rate *= 8;
>
> And parent_rate can't overflow if it's a u32? Maybe it could be a u64 so
> that we don't need casting later on in this function.
>
Fixed in the next version.
> > + rate *= 2;
> > + divfi = rate / parent_rate;
> > + temp64 = (u64)(rate - divfi * parent_rate);
> > + temp64 *= PLL_FRAC_DENOM;
> > + do_div(temp64, parent_rate);
> > + divff = temp64;
> > +
> > + temp64 = (u64)parent_rate;
> > + temp64 *= divff;
> > + do_div(temp64, PLL_FRAC_DENOM);
> > +
> > + return (parent_rate * divfi + (unsigned long)temp64) / 2;
> > +}
> > +
> > +/*
> > + * To simplify the clock calculation, we can keep the 'PLL_OUTPUT_VAL' at zero
> > + * (means the PLL output will be divided by 2). So the PLL output can use
> > + * the below formula:
> > + * pllout = parent_rate * 8 / 2 * DIVF_VAL;
> > + * where DIVF_VAL = 1 + DIVFI + DIVFF / 2^24.
> > + */
> > +static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> > + unsigned long parent_rate)
> > +{
> > + struct clk_frac_pll *pll = to_clk_frac_pll(hw);
> > + u32 val, divfi, divff;
> > + u64 temp64;
> > + int ret;
> > +
> > + parent_rate *= 8;
> > + rate *= 2;
> > + divfi = rate / parent_rate;
> > + temp64 = (u64) (rate - divfi * parent_rate);
> > + temp64 *= PLL_FRAC_DENOM;
> > + do_div(temp64, parent_rate);
> > + divff = temp64;
> > +
> > + val = readl_relaxed(pll->base + PLL_CFG1);
> > + val &= ~(PLL_FRAC_DIV_MASK | PLL_INT_DIV_MASK);
> > + val |= ((divff << 7) | (divfi - 1));
>
> Nitpick: Drop the extra parenthesis please.
>
Removed in the next version.
> > + writel_relaxed(val, pll->base + PLL_CFG1);
> > +
> > + val = readl_relaxed(pll->base + PLL_CFG0);
> > + val &= ~0x1f;
> > + writel_relaxed(val, pll->base + PLL_CFG0);
> > +
> > + /* Set the NEV_DIV_VAL to reload the DIVFI and DIVFF */
> > + val = readl_relaxed(pll->base + PLL_CFG0);
> > + val |= PLL_NEWDIV_VAL;
> > + writel_relaxed(val, pll->base + PLL_CFG0);
> > +
> > + ret = clk_wait_ack(pll);
> > +
> > + /* clear the NEV_DIV_VAL */
> > + val = readl_relaxed(pll->base + PLL_CFG0);
> > + val &= ~PLL_NEWDIV_VAL;
> > + writel_relaxed(val, pll->base + PLL_CFG0);
> > +
> > + return ret;
> > +}
> > +
> > +static const struct clk_ops clk_frac_pll_ops = {
> > + .prepare = clk_pll_prepare,
> > + .unprepare = clk_pll_unprepare,
> > + .is_prepared = clk_pll_is_prepared,
> > + .recalc_rate = clk_pll_recalc_rate,
> > + .round_rate = clk_pll_round_rate,
> > + .set_rate = clk_pll_set_rate,
> > +};
> > +
> > +struct clk *imx_clk_frac_pll(const char *name, const char *parent_name,
> > + void __iomem *base)
> > +{
> > + struct clk_init_data init;
> > + struct clk_frac_pll *pll;
> > + struct clk *clk;
> > +
> > + pll = kzalloc(sizeof(*pll), GFP_KERNEL);
> > + if (!pll)
> > + return ERR_PTR(-ENOMEM);
> > +
> > + pll->base = base;
> > + init.name = name;
> > + init.ops = &clk_frac_pll_ops;
> > + init.flags = 0;
> > + init.parent_names = &parent_name;
> > + init.num_parents = 1;
> > +
> > + pll->hw.init = &init;
> > +
> > + clk = clk_register(NULL, &pll->hw);
>
> clk_hw based please.
>
Fixed in the next version.
> > + if (IS_ERR(clk))
> > + kfree(pll);
> > +
> > + return clk;
> > +}
--
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v9 3/5] clk: imx: add SCCG PLL type
2018-11-07 11:54 ` Abel Vesa
@ 2018-11-07 19:01 ` Stephen Boyd
2018-11-07 20:26 ` Abel Vesa
0 siblings, 1 reply; 23+ messages in thread
From: Stephen Boyd @ 2018-11-07 19:01 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Abel Vesa (2018-11-07 03:54:45)
> On Wed, Oct 17, 2018 at 12:55:52PM -0700, Stephen Boyd wrote:
> > Quoting Abel Vesa (2018-09-24 03:39:55)
> > > +static unsigned long clk_pll2_recalc_rate(struct clk_hw *hw,
> > > + unsigned long parent_rate)
> > > +{
> > > + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
> > > + u32 val, ref, divr1, divf1, divr2, divf2;
> > > + u64 temp64;
> > > +
> > > + val = readl_relaxed(pll->base + PLL_CFG0);
> > > + switch (FIELD_GET(PLL_REF_MASK, val)) {
> > > + case 0:
> > > + ref = OSC_25M;
> > > + break;
> > > + case 1:
> > > + ref = OSC_27M;
> > > + break;
> > > + default:
> > > + ref = OSC_25M;
> >
> > Does this information not come through 'parent_rate'?
> >
>
> No. So basically both pll1 and pll2 and the divider after it form together this SCCG:
>
> https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834
>
> See: Figure 5-8. SSCG PLL Block Diagram
Thanks for the link!
>
> We're basically reading the input of the pll 1 in order to compute the output of the entire SCCG.
>
> I know it's a mess. I'm working on cleaning it up, but for now we need this in in order to boot up.
What's the plan to clean it up?
>
> > > + break;
> > > + }
> > > +
> > > + val = readl_relaxed(pll->base + PLL_CFG2);
> > > + divr1 = FIELD_GET(PLL_DIVR1_MASK, val);
> > > + divr2 = FIELD_GET(PLL_DIVR2_MASK, val);
> > > + divf1 = FIELD_GET(PLL_DIVF1_MASK, val);
> > > + divf2 = FIELD_GET(PLL_DIVF2_MASK, val);
> > > +
> > > + temp64 = ref * 2;
> > > + temp64 *= (divf1 + 1) * (divf2 + 1);
> > > +
> > > + do_div(temp64, (divr1 + 1) * (divr2 + 1));
> >
> > Nitpicks: A comment with the equation may be helpful to newcomers.
>
> Since the SCCG is contructed by multiple different types of clocks here, the equation doesn't help
> since it is spread in all constructing blocks.
Ok.
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v9 3/5] clk: imx: add SCCG PLL type
2018-11-07 19:01 ` Stephen Boyd
@ 2018-11-07 20:26 ` Abel Vesa
2018-11-08 0:18 ` Stephen Boyd
0 siblings, 1 reply; 23+ messages in thread
From: Abel Vesa @ 2018-11-07 20:26 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Nov 07, 2018 at 11:01:02AM -0800, Stephen Boyd wrote:
> Quoting Abel Vesa (2018-11-07 03:54:45)
> > On Wed, Oct 17, 2018 at 12:55:52PM -0700, Stephen Boyd wrote:
> > > Quoting Abel Vesa (2018-09-24 03:39:55)
> > > > +static unsigned long clk_pll2_recalc_rate(struct clk_hw *hw,
> > > > + unsigned long parent_rate)
> > > > +{
> > > > + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
> > > > + u32 val, ref, divr1, divf1, divr2, divf2;
> > > > + u64 temp64;
> > > > +
> > > > + val = readl_relaxed(pll->base + PLL_CFG0);
> > > > + switch (FIELD_GET(PLL_REF_MASK, val)) {
> > > > + case 0:
> > > > + ref = OSC_25M;
> > > > + break;
> > > > + case 1:
> > > > + ref = OSC_27M;
> > > > + break;
> > > > + default:
> > > > + ref = OSC_25M;
> > >
> > > Does this information not come through 'parent_rate'?
> > >
> >
> > No. So basically both pll1 and pll2 and the divider after it form together this SCCG:
> >
> > https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834
> >
> > See: Figure 5-8. SSCG PLL Block Diagram
>
> Thanks for the link!
>
> >
> > We're basically reading the input of the pll 1 in order to compute the output of the entire SCCG.
> >
> > I know it's a mess. I'm working on cleaning it up, but for now we need this in in order to boot up.
>
> What's the plan to clean it up?
So I'm doing this in our internal tree first to make sure I don't break the
other (newer) socs.
I already have a prototype in testing but it's a long way to upstream it.
Basically, I'm replacing all of this with a single, more like a composite,
more complex, clock type that does all the magic inside.
One of the problems is the fact that the bypasses can have the same sources
and in my case, I'm implementing that as a list of parents name, but the
parent names list doesn't work with duplicates, so I have to find some other
way to do it.
Once I have something clean and tested enough I'll send it upstream.
>
> >
> > > > + break;
> > > > + }
> > > > +
> > > > + val = readl_relaxed(pll->base + PLL_CFG2);
> > > > + divr1 = FIELD_GET(PLL_DIVR1_MASK, val);
> > > > + divr2 = FIELD_GET(PLL_DIVR2_MASK, val);
> > > > + divf1 = FIELD_GET(PLL_DIVF1_MASK, val);
> > > > + divf2 = FIELD_GET(PLL_DIVF2_MASK, val);
> > > > +
> > > > + temp64 = ref * 2;
> > > > + temp64 *= (divf1 + 1) * (divf2 + 1);
> > > > +
> > > > + do_div(temp64, (divr1 + 1) * (divr2 + 1));
> > >
> > > Nitpicks: A comment with the equation may be helpful to newcomers.
> >
> > Since the SCCG is contructed by multiple different types of clocks here, the equation doesn't help
> > since it is spread in all constructing blocks.
>
> Ok.
>
--
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v9 3/5] clk: imx: add SCCG PLL type
2018-11-07 20:26 ` Abel Vesa
@ 2018-11-08 0:18 ` Stephen Boyd
2018-11-08 12:29 ` Abel Vesa
0 siblings, 1 reply; 23+ messages in thread
From: Stephen Boyd @ 2018-11-08 0:18 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Abel Vesa (2018-11-07 12:26:25)
> On Wed, Nov 07, 2018 at 11:01:02AM -0800, Stephen Boyd wrote:
> >
> >
> > What's the plan to clean it up?
>
> So I'm doing this in our internal tree first to make sure I don't break the
> other (newer) socs.
>
> I already have a prototype in testing but it's a long way to upstream it.
>
> Basically, I'm replacing all of this with a single, more like a composite,
> more complex, clock type that does all the magic inside.
>
> One of the problems is the fact that the bypasses can have the same sources
> and in my case, I'm implementing that as a list of parents name, but the
> parent names list doesn't work with duplicates, so I have to find some other
> way to do it.
>
> Once I have something clean and tested enough I'll send it upstream.
Ok. Thanks for the info.
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v9 3/5] clk: imx: add SCCG PLL type
2018-11-08 0:18 ` Stephen Boyd
@ 2018-11-08 12:29 ` Abel Vesa
2018-11-08 18:28 ` Stephen Boyd
0 siblings, 1 reply; 23+ messages in thread
From: Abel Vesa @ 2018-11-08 12:29 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Nov 07, 2018 at 04:18:35PM -0800, Stephen Boyd wrote:
> Quoting Abel Vesa (2018-11-07 12:26:25)
> > On Wed, Nov 07, 2018 at 11:01:02AM -0800, Stephen Boyd wrote:
> > >
> > >
> > > What's the plan to clean it up?
> >
> > So I'm doing this in our internal tree first to make sure I don't break the
> > other (newer) socs.
> >
> > I already have a prototype in testing but it's a long way to upstream it.
> >
> > Basically, I'm replacing all of this with a single, more like a composite,
> > more complex, clock type that does all the magic inside.
> >
> > One of the problems is the fact that the bypasses can have the same sources
> > and in my case, I'm implementing that as a list of parents name, but the
> > parent names list doesn't work with duplicates, so I have to find some other
> > way to do it.
> >
> > Once I have something clean and tested enough I'll send it upstream.
>
> Ok. Thanks for the info.
>
Just to avoid any kind of confusion.
The whole refactoring of the SCCG clock will be done in a separate (later) change
and will not be part of this patchset.
I already sent the 12th version of this current patch series and I would really
like to get this in ASAP so that the booting up of imx8mq will not be delayed.
Thanks
Abel
--
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v9 3/5] clk: imx: add SCCG PLL type
2018-11-08 12:29 ` Abel Vesa
@ 2018-11-08 18:28 ` Stephen Boyd
2018-11-10 16:05 ` A.s. Dong
0 siblings, 1 reply; 23+ messages in thread
From: Stephen Boyd @ 2018-11-08 18:28 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Abel Vesa (2018-11-08 04:29:39)
> On Wed, Nov 07, 2018 at 04:18:35PM -0800, Stephen Boyd wrote:
> > Quoting Abel Vesa (2018-11-07 12:26:25)
> > > On Wed, Nov 07, 2018 at 11:01:02AM -0800, Stephen Boyd wrote:
> > > >
> > > >
> > > > What's the plan to clean it up?
> > >
> > > So I'm doing this in our internal tree first to make sure I don't break the
> > > other (newer) socs.
> > >
> > > I already have a prototype in testing but it's a long way to upstream it.
> > >
> > > Basically, I'm replacing all of this with a single, more like a composite,
> > > more complex, clock type that does all the magic inside.
> > >
> > > One of the problems is the fact that the bypasses can have the same sources
> > > and in my case, I'm implementing that as a list of parents name, but the
> > > parent names list doesn't work with duplicates, so I have to find some other
> > > way to do it.
> > >
> > > Once I have something clean and tested enough I'll send it upstream.
> >
> > Ok. Thanks for the info.
> >
>
> Just to avoid any kind of confusion.
>
> The whole refactoring of the SCCG clock will be done in a separate (later) change
> and will not be part of this patchset.
>
> I already sent the 12th version of this current patch series and I would really
> like to get this in ASAP so that the booting up of imx8mq will not be delayed.
>
Ok. Well we're in rc1 right now, and so we're not merging new drivers
into mainline. I can merge the clk driver into clk-next, but you'll have
to wait for the stabilization period to end (approximately 6 or 7 weeks)
before this can get into the next kernel version. It will be in
linux-next much sooner of course.
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v9 3/5] clk: imx: add SCCG PLL type
2018-11-08 18:28 ` Stephen Boyd
@ 2018-11-10 16:05 ` A.s. Dong
2018-11-13 14:25 ` Shawn Guo
0 siblings, 1 reply; 23+ messages in thread
From: A.s. Dong @ 2018-11-10 16:05 UTC (permalink / raw)
To: linux-arm-kernel
Hi Stephen,
[...]
> > I already sent the 12th version of this current patch series and I
> > would really like to get this in ASAP so that the booting up of imx8mq will
> not be delayed.
> >
>
> Ok. Well we're in rc1 right now, and so we're not merging new drivers into
> mainline. I can merge the clk driver into clk-next, but you'll have to wait for the
> stabilization period to end (approximately 6 or 7 weeks) before this can get
> into the next kernel version. It will be in linux-next much sooner of course.
That would be great if you can help that.
We're now working with SUSE to enable i.MX8 support.
Their criteria is only backporting patches which must be at least in maintainer's
next tree already. So either picked up by you or Shawn would help a lot on it.
BTW, one simple question is that because MX8MQ DTS patches depends on
this clock driver series. How would you suggest this series to go through
your tree or Shawn's tree?
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v9 3/5] clk: imx: add SCCG PLL type
2018-11-10 16:05 ` A.s. Dong
@ 2018-11-13 14:25 ` Shawn Guo
2018-11-14 23:21 ` Stephen Boyd
0 siblings, 1 reply; 23+ messages in thread
From: Shawn Guo @ 2018-11-13 14:25 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Nov 10, 2018 at 04:05:44PM +0000, A.s. Dong wrote:
> Hi Stephen,
>
> [...]
> > > I already sent the 12th version of this current patch series and I
> > > would really like to get this in ASAP so that the booting up of imx8mq will
> > not be delayed.
> > >
> >
> > Ok. Well we're in rc1 right now, and so we're not merging new drivers into
> > mainline. I can merge the clk driver into clk-next, but you'll have to wait for the
> > stabilization period to end (approximately 6 or 7 weeks) before this can get
> > into the next kernel version. It will be in linux-next much sooner of course.
>
> That would be great if you can help that.
> We're now working with SUSE to enable i.MX8 support.
> Their criteria is only backporting patches which must be at least in maintainer's
> next tree already. So either picked up by you or Shawn would help a lot on it.
>
> BTW, one simple question is that because MX8MQ DTS patches depends on
> this clock driver series. How would you suggest this series to go through
> your tree or Shawn's tree?
Once Stephen has a topic branch for the patches, I can pull it into my
tree to resolve the DT dependency.
Shawn
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v9 3/5] clk: imx: add SCCG PLL type
2018-11-13 14:25 ` Shawn Guo
@ 2018-11-14 23:21 ` Stephen Boyd
0 siblings, 0 replies; 23+ messages in thread
From: Stephen Boyd @ 2018-11-14 23:21 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Shawn Guo (2018-11-13 06:25:36)
> On Sat, Nov 10, 2018 at 04:05:44PM +0000, A.s. Dong wrote:
> > Hi Stephen,
> >
> > [...]
> > > > I already sent the 12th version of this current patch series and I
> > > > would really like to get this in ASAP so that the booting up of imx8mq will
> > > not be delayed.
> > > >
> > >
> > > Ok. Well we're in rc1 right now, and so we're not merging new drivers into
> > > mainline. I can merge the clk driver into clk-next, but you'll have to wait for the
> > > stabilization period to end (approximately 6 or 7 weeks) before this can get
> > > into the next kernel version. It will be in linux-next much sooner of course.
> >
> > That would be great if you can help that.
> > We're now working with SUSE to enable i.MX8 support.
> > Their criteria is only backporting patches which must be at least in maintainer's
> > next tree already. So either picked up by you or Shawn would help a lot on it.
> >
> > BTW, one simple question is that because MX8MQ DTS patches depends on
> > this clock driver series. How would you suggest this series to go through
> > your tree or Shawn's tree?
>
> Once Stephen has a topic branch for the patches, I can pull it into my
> tree to resolve the DT dependency.
>
Sounds like a plan. Expect something next week.
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2018-11-14 23:21 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz follow: Atom feed
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[not found] <1537785597-26499-1-git-send-email-abel.vesa@nxp.com>
2018-09-24 10:39 ` [PATCH v9 2/5] clk: imx: add fractional PLL output clock Abel Vesa
2018-10-17 19:59 ` Stephen Boyd
2018-11-07 12:25 ` Abel Vesa
2018-09-24 10:39 ` [PATCH v9 3/5] clk: imx: add SCCG PLL type Abel Vesa
2018-10-17 19:55 ` Stephen Boyd
2018-11-07 11:54 ` Abel Vesa
2018-11-07 19:01 ` Stephen Boyd
2018-11-07 20:26 ` Abel Vesa
2018-11-08 0:18 ` Stephen Boyd
2018-11-08 12:29 ` Abel Vesa
2018-11-08 18:28 ` Stephen Boyd
2018-11-10 16:05 ` A.s. Dong
2018-11-13 14:25 ` Shawn Guo
2018-11-14 23:21 ` Stephen Boyd
2018-09-24 10:39 ` [PATCH v9 4/5] clk: imx: add imx composite clock Abel Vesa
2018-09-25 16:42 ` Fabio Estevam
2018-09-26 6:47 ` Sascha Hauer
2018-09-26 12:02 ` Fabio Estevam
2018-10-17 19:51 ` Stephen Boyd
2018-10-18 9:57 ` Abel Vesa
2018-09-24 10:39 ` [PATCH v9 5/5] clk: imx: add clock driver for i.MX8MQ CCM Abel Vesa
2018-10-17 19:44 ` Stephen Boyd
2018-11-07 12:09 ` Abel Vesa
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