From: honghui.zhang@mediatek.com (honghui.zhang at mediatek.com)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 2/9] PCI: mediatek: Fixup class ID for MT7622 as PCI_CLASS_BRIDGE_PCI
Date: Fri, 28 Sep 2018 18:04:33 +0800 [thread overview]
Message-ID: <1538129080-8206-3-git-send-email-honghui.zhang@mediatek.com> (raw)
In-Reply-To: <1538129080-8206-1-git-send-email-honghui.zhang@mediatek.com>
From: Honghui Zhang <honghui.zhang@mediatek.com>
The PCIe controller of MT7622 has TYPE 1 configuration space type, but
the HW default class type values is invalid.
The commit 101c92dc80c8 ("PCI: mediatek: Set up vendor ID and class
type for MT7622") have set the class ID for MT7622 as
PCI_CLASS_BRIDGE_HOST, but it's not workable for MT7622:
In __pci_bus_assign_resources, the framework only setup bridge's
resource window only if class type is PCI_CLASS_BRIDGE_PCI. Or it
will leave the subordinary PCIe device's MMIO window un-touched.
Fixup the class type to PCI_CLASS_BRIDGE_PCI as most of the controller
driver do.
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
---
drivers/pci/controller/pcie-mediatek.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
index 264e03f..3ab80d6 100644
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -436,7 +436,7 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
val = PCI_VENDOR_ID_MEDIATEK;
writew(val, port->base + PCIE_CONF_VEND_ID);
- val = PCI_CLASS_BRIDGE_HOST;
+ val = PCI_CLASS_BRIDGE_PCI;
writew(val, port->base + PCIE_CONF_CLASS_ID);
}
--
2.6.4
next prev parent reply other threads:[~2018-09-28 10:04 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-28 10:04 [PATCH v5 0/9] PCI: mediatek: fixup find_port, enable_msi and add pm, module support honghui.zhang at mediatek.com
2018-09-28 10:04 ` [PATCH v5 1/9] PCI: mediatek: Using slot's devfn for compare to fix mtk_pcie_find_port logic honghui.zhang at mediatek.com
2018-10-01 14:36 ` Lorenzo Pieralisi
2018-10-02 10:59 ` Lorenzo Pieralisi
2018-10-08 3:02 ` Honghui Zhang
2018-09-28 10:04 ` honghui.zhang at mediatek.com [this message]
2018-09-28 10:04 ` [PATCH v5 3/9] PCI: mediatek: Remove the redundant dev->pm_domain check honghui.zhang at mediatek.com
2018-09-28 10:04 ` [PATCH v5 4/9] PCI: mediatek: Convert to use pci_host_probe() honghui.zhang at mediatek.com
2018-09-28 15:41 ` Ryder Lee
2018-09-29 0:16 ` Honghui Zhang
2018-09-29 5:55 ` Ryder Lee
2018-09-28 10:04 ` [PATCH v5 5/9] PCI: mediatek: Move the mtk_pcie_startup_port_v2 function's define after mtk_pcie_setup_irq honghui.zhang at mediatek.com
2018-09-28 10:04 ` [PATCH v5 6/9] PCI: mediatek: Enable msi after clock enabled honghui.zhang at mediatek.com
2018-10-02 11:01 ` Lorenzo Pieralisi
2018-09-28 10:04 ` [PATCH v5 7/9] PCI: mediatek: Add system pm support for MT2712 and MT7622 honghui.zhang at mediatek.com
2018-09-28 10:04 ` [PATCH v5 8/9] PCI: mediatek: Save the GIC IRQ in mtk_pcie_port honghui.zhang at mediatek.com
2018-09-28 10:04 ` [PATCH v5 9/9] PCI: mediatek: Add loadable kernel module support honghui.zhang at mediatek.com
2018-09-29 5:58 ` [PATCH v5 0/9] PCI: mediatek: fixup find_port, enable_msi and add pm, " Ryder Lee
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