From: sean.wang@mediatek.com (Sean Wang)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/2] mmc: mediatek: add bus_clk control
Date: Sat, 29 Sep 2018 01:28:56 +0800 [thread overview]
Message-ID: <1538155736.30348.85.camel@mtkswgap22> (raw)
In-Reply-To: <1538134855-11198-3-git-send-email-chaotian.jing@mediatek.com>
Hi,
On Fri, 2018-09-28 at 19:40 +0800, Chaotian Jing wrote:
> when gate MSDC0_HCLK, access register will hang, even the MSDC driver
> will never accessing register after HCLK was gated, but for safety, need
> gate the bus_clk(which used to access register) too.
>
> Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
> ---
> drivers/mmc/host/mtk-sd.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
> index 0484138..1c1c967 100644
> --- a/drivers/mmc/host/mtk-sd.c
> +++ b/drivers/mmc/host/mtk-sd.c
> @@ -387,6 +387,7 @@ struct msdc_host {
>
> struct clk *src_clk; /* msdc source clock */
> struct clk *h_clk; /* msdc h_clk */
> + struct clk *bus_clk; /* bus clock which used to access register */
> struct clk *src_clk_cg; /* msdc source clock control gate */
> u32 mclk; /* mmc subsystem clock frequency */
> u32 src_clk_freq; /* source clock frequency */
> @@ -660,12 +661,14 @@ static void msdc_gate_clock(struct msdc_host *host)
> {
> clk_disable_unprepare(host->src_clk_cg);
> clk_disable_unprepare(host->src_clk);
> + clk_disable_unprepare(host->bus_clk);
> clk_disable_unprepare(host->h_clk);
> }
>
> static void msdc_ungate_clock(struct msdc_host *host)
> {
> clk_prepare_enable(host->h_clk);
> + clk_prepare_enable(host->bus_clk);
> clk_prepare_enable(host->src_clk);
> clk_prepare_enable(host->src_clk_cg);
> while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
> @@ -1900,6 +1903,9 @@ static int msdc_drv_probe(struct platform_device *pdev)
> goto host_free;
> }
>
> + host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
> + if (IS_ERR(host->bus_clk))
> + host->bus_clk = NULL;
The implementation would cause all SoCs to treat the bus_clk as the optional.
It seems you should add a flag to see what SoC requires the bus_clk to successfully access the related registers.
> /*source clock control gate is optional clock*/
> host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg");
> if (IS_ERR(host->src_clk_cg))
next prev parent reply other threads:[~2018-09-28 17:28 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-28 11:40 mmc: mediatek: add bus_clk control Chaotian Jing
2018-09-28 11:40 ` [PATCH 1/2] mmc: dt-bindings: add "bus-clk" for MT2712 Chaotian Jing
2018-09-28 17:34 ` Sean Wang
2018-09-29 2:37 ` Chaotian Jing
2018-09-28 11:40 ` [PATCH 2/2] mmc: mediatek: add bus_clk control Chaotian Jing
2018-09-28 17:28 ` Sean Wang [this message]
2018-09-29 2:39 ` Chaotian Jing
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