Re: (EXT) [PATCH] arm64: dts: imx8mp: Add CSIS DT nodes

[Alexander Stein <alexander.stein@ew.tq-group.com>]

Hello Laurent,

thanks for ths and the other MIPI CSI-2 related patches.

Am Donnerstag, 16. Juni 2022, 18:16:43 CEST schrieb Laurent Pinchart:
> Add DT nodes for the two CSI-2 receivers of the i.MX8MP.
> 
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> This patch depends on the DT bindings submitted in [1], for which I plan
> to submit a pull request for v5.20.
> 
> [1]
> https://lore.kernel.org/linux-media/83e27382-6f97-015f-2ee1-f43820967093@li
> naro.org/T/#u ---
>  arch/arm64/boot/dts/freescale/imx8mp.dtsi | 60 +++++++++++++++++++++++
>  1 file changed, 60 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index
> d9542dfff83f..c8ed206b7f41 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -1063,6 +1063,66 @@ media_blk_ctrl: blk-ctrl@32ec0000 {
>  				#power-domain-cells = <1>;
>  			};
> 
> +			mipi_csi_0: csi@32e40000 {
> +				compatible = "fsl,imx8mp-mipi-
csi2", "fsl,imx8mm-mipi-csi2";
> +				reg = <0x32e40000 0x10000>;
> +				interrupts = <GIC_SPI 17 
IRQ_TYPE_LEVEL_HIGH>;
> +				clock-frequency = <500000000>;

According to datasheet (IMX8MPIEC Rev 1, Table 1, Subsystem "MIPI Interface") 
"MIPI CSI1" supports up to 500MHz only in single camera use and overdrive 
mode. In normal mode only 400MHz are supported. For dual camera usage only up 
to 266MHz is supported. Apparently this is when using ISP, things might be 
different when using ISI. I'm hesitating specifying the overdrive mode 
frequency here. Most users, most probably using normal mode, would have 
requiring them to adjust this.
For dual camera this is even as low as 266MHz, but IMHO this is a special 
case.

> +				clocks = <&clk 
IMX8MP_CLK_MEDIA_APB_ROOT>,
> +					 <&clk 
IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
> +					 <&clk 
IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
> +					 <&clk 
IMX8MP_CLK_MEDIA_AXI_ROOT>;
> +				clock-names = "pclk", "wrap", 
"phy", "axi";
> +				assigned-clocks = <&clk 
IMX8MP_CLK_MEDIA_CAM1_PIX>;
> +				assigned-clock-parents = <&clk 
IMX8MP_SYS_PLL2_1000M>;
> +				assigned-clock-rates = 
<500000000>;
> +				power-domains = <&media_blk_ctrl 
IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
> +				status = "disabled";
> +
> +				ports {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					port@0 {
> +						reg = <0>;
> +					};
> +
> +					port@1 {
> +						reg = <1>;
> +					};
> +				};
> +			};
> +
> +			mipi_csi_1: csi@32e50000 {
> +				compatible = "fsl,imx8mp-mipi-
csi2", "fsl,imx8mm-mipi-csi2";
> +				reg = <0x32e50000 0x10000>;
> +				interrupts = <GIC_SPI 80 
IRQ_TYPE_LEVEL_HIGH>;
> +				clock-frequency = <266000000>;

For single camera usage this can even go as high as 277MHz. 266MHz is only for 
dual camera use.

Best regards,
Alexander

> +				clocks = <&clk 
IMX8MP_CLK_MEDIA_APB_ROOT>,
> +					 <&clk 
IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
> +					 <&clk 
IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
> +					 <&clk 
IMX8MP_CLK_MEDIA_AXI_ROOT>;
> +				clock-names = "pclk", "wrap", 
"phy", "axi";
> +				assigned-clocks = <&clk 
IMX8MP_CLK_MEDIA_CAM2_PIX>;
> +				assigned-clock-parents = <&clk 
IMX8MP_SYS_PLL2_1000M>;
> +				assigned-clock-rates = 
<266000000>;
> +				power-domains = <&media_blk_ctrl 
IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
> +				status = "disabled";
> +
> +				ports {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					port@0 {
> +						reg = <0>;
> +					};
> +
> +					port@1 {
> +						reg = <1>;
> +					};
> +				};
> +			};
> +
>  			hsio_blk_ctrl: blk-ctrl@32f10000 {
>  				compatible = "fsl,imx8mp-hsio-blk-
ctrl", "syscon";
>  				reg = <0x32f10000 0x24>;
> 
> base-commit: b13baccc3850ca8b8cccbf8ed9912dbaa0fdf7f3





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