From: Fabio Estevam <festevam@gmail.com>
To: shawnguo@kernel.org
Cc: devicetree@vger.kernel.org, marc.zyngier@arm.com,
liviu.dudau@arm.com, robh+dt@kernel.org, linux-imx@nxp.com,
kernel@pengutronix.de, Fabio Estevam <festevam@gmail.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/2] ARM: dts: imx7: Correct mask for GIC PPI interrupts
Date: Mon, 3 Dec 2018 15:40:20 -0200 [thread overview]
Message-ID: <1543858820-3354-2-git-send-email-festevam@gmail.com> (raw)
In-Reply-To: <1543858820-3354-1-git-send-email-festevam@gmail.com>
The GIC_CPU_MASK_SIMPLE() macro should take as its argument the actual
number of CPU cores the interrupt controller is wired to.
i.MX7S contains a single Cortex-A7, hence the second interrupt specifier
cell for Private Peripheral Interrupts should use "GIC_CPU_MASK_SIMPLE(1)".
Likewise, i.MX7D contains two Cortex-A7 cores, so it should use
"GIC_CPU_MASK_SIMPLE(2)" instead.
Tested on a imx7s-warp.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
arch/arm/boot/dts/imx7d.dtsi | 21 +++++++++++++++++++++
arch/arm/boot/dts/imx7s.dtsi | 10 +++++-----
2 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index 826224b..6b298e3 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -24,6 +24,15 @@
};
};
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
cpu0_opp_table: opp-table {
compatible = "operating-points-v2";
opp-shared;
@@ -72,6 +81,18 @@
};
};
};
+
+ intc: interrupt-controller@31001000 {
+ compatible = "arm,cortex-a7-gic";
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupt-parent = <&intc>;
+ reg = <0x31001000 0x1000>,
+ <0x31002000 0x2000>,
+ <0x31004000 0x2000>,
+ <0x31006000 0x2000>;
+ };
};
};
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index 477901c..098d2cc 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -160,10 +160,10 @@
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <&intc>;
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
soc {
@@ -305,7 +305,7 @@
intc: interrupt-controller@31001000 {
compatible = "arm,cortex-a7-gic";
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
#interrupt-cells = <3>;
interrupt-controller;
interrupt-parent = <&intc>;
--
2.7.4
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next prev parent reply other threads:[~2018-12-03 17:41 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-03 17:40 [PATCH 1/2] ARM: dts: imx6ul: Correct mask for GIC PPI interrupts Fabio Estevam
2018-12-03 17:40 ` Fabio Estevam [this message]
2018-12-05 4:14 ` Shawn Guo
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