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Thu, 31 Jan 2019 11:22:31 +0800 Message-ID: <1548904951.19710.41.camel@mhfsdcap03> Subject: Re: [PATCH v5 14/20] iommu/mediatek: Add mmu1 support From: Yong Wu To: Evan Green Date: Thu, 31 Jan 2019 11:22:31 +0800 In-Reply-To: References: <1546314952-15990-1-git-send-email-yong.wu@mediatek.com> <1546314952-15990-15-git-send-email-yong.wu@mediatek.com> X-Mailer: Evolution 3.2.3-0ubuntu6 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190130_192312_440820_74DB821B X-CRM114-Status: GOOD ( 22.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: youlin.pei@mediatek.com, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Nicolas Boichat , Arnd Bergmann , srv_heupstream@mediatek.com, Joerg Roedel , Will Deacon , LKML , Tomasz Figa , iommu@lists.linux-foundation.org, Rob Herring , linux-mediatek@lists.infradead.org, Matthias Brugger , yingjoe.chen@mediatek.com, Robin Murphy , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 2019-01-30 at 10:55 -0800, Evan Green wrote: > On Mon, Dec 31, 2018 at 7:59 PM Yong Wu wrote: > > > > Normally the M4U HW connect EMI with smi. the diagram is like below: > > EMI > > | > > M4U > > | > > smi-common > > | > > ----------------- > > | | | | ... > > larb0 larb1 larb2 larb3 > > > > Actually there are 2 mmu cells in the M4U HW, like this diagram: > > > > EMI > > --------- > > | | > > mmu0 mmu1 <- M4U > > | | > > --------- > > | > > smi-common > > | > > ----------------- > > | | | | ... > > larb0 larb1 larb2 larb3 > > > > This patch add support for mmu1. In order to get better performance, > > we could adjust some larbs go to mmu1 while the others still go to > > mmu0. This is controlled by a SMI COMMON register SMI_BUS_SEL(0x220). > > > > mt2712, mt8173 and mt8183 M4U HW all have 2 mmu cells. the default > > value of that register is 0 which means all the larbs go to mmu0 > > defaultly. > > > > This is a preparing patch for adjusting SMI_BUS_SEL for mt8183. > > > > Signed-off-by: Yong Wu > > --- > > drivers/iommu/mtk_iommu.c | 47 +++++++++++++++++++++++++++++------------------ > > 1 file changed, 29 insertions(+), 18 deletions(-) > > > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > > index 66e3615..7fcef19 100644 > > --- a/drivers/iommu/mtk_iommu.c > > +++ b/drivers/iommu/mtk_iommu.c > > @@ -70,27 +70,32 @@ > > #define F_MISS_FIFO_ERR_INT_EN BIT(6) > > #define F_INT_CLR_BIT BIT(12) > > > > -#define REG_MMU_INT_MAIN_CONTROL 0x124 > > -#define F_INT_TRANSLATION_FAULT BIT(0) > > -#define F_INT_MAIN_MULTI_HIT_FAULT BIT(1) > > -#define F_INT_INVALID_PA_FAULT BIT(2) > > -#define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3) > > -#define F_INT_TLB_MISS_FAULT BIT(4) > > -#define F_INT_MISS_TRANSACTION_FIFO_FAULT BIT(5) > > -#define F_INT_PRETETCH_TRANSATION_FIFO_FAULT BIT(6) > > +#define REG_MMU_INT_MAIN_CONTROL 0x124 /* mmu0 | mmu1 */ > > The comment being on that line is kind of weird, since the comment > really applies to the lines below it. Maybe the comment should be on > its own line, or on the TRANSLATION_FAULT line. Sharp eye. You are right, this comment applies the lines below. But If I move it below, then the next line will be over 80 chars. How about I add a "below:" like this: > +#define REG_MMU_INT_MAIN_CONTROL 0x124 /* below: mmu0 | mmu1 */ > > Other than that, > Reviewed-by: Evan Green _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel