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Fri, 1 Feb 2019 16:22:33 +0800 Message-ID: <1549009353.22634.6.camel@mtksdaap41> Subject: Re: [PATCH v3 12/12] clk: mediatek: Allow changing PLL rate when it is off From: Weiyi Lu To: Stephen Boyd Date: Fri, 1 Feb 2019 16:22:33 +0800 In-Reply-To: <154482488309.19322.1300826887966936368@swboyd.mtv.corp.google.com> References: <20181210073240.32278-1-weiyi.lu@mediatek.com> <20181210073240.32278-14-weiyi.lu@mediatek.com> <154482488309.19322.1300826887966936368@swboyd.mtv.corp.google.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 323FA7B1E94B6F4E0691E4A862BF236DC171CD9DE8FDF8AAEDC9BCDAB7A414842000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190201_002709_714235_A7A3C644 X-CRM114-Status: GOOD ( 11.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Nicolas Boichat , srv_heupstream@mediatek.com, James Liao , Stephen Boyd , linux-kernel@vger.kernel.org, stable@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, Matthias Brugger , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 2018-12-14 at 14:01 -0800, Stephen Boyd wrote: > Quoting Weiyi Lu (2018-12-09 23:32:40) > > From: James Liao > > > > Some modules may need to change its clock rate before turn on it. > > So changing PLL's rate when it is off should be allowed. > > This patch removes PLL enabled check before set rate, so that > > PLLs can set new frequency even if they are off. > > > > On MT8173 for example, ARMPLL's enable bit can be controlled by > > other HW. That means ARMPLL may be turned on even if we (CPU / SW) > > set ARMPLL's enable bit as 0. In this case, SW may want and can > > still change ARMPLL's rate by changing its pcw and postdiv settings. > > But without this patch, new pcw setting will not be applied because > > its enable bit is 0. > > > > (am from https://patchwork.kernel.org/patch/9411983/) > > Remove this. > OK, I'll remove it. > > > > Signed-off-by: James Liao > > Acked-by: Michael Turquette > > Signed-off-by: Weiyi Lu _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel