From: Hanjun Guo <guohanjun@huawei.com>
To: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will.deacon@arm.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>,
John Garry <john.garry@huawei.com>,
linuxarm@huawei.com, Zhangshaokun <zhangshaokun@hisilicon.com>,
Hanjun Guo <hanjun.guo@linaro.org>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 0/2] Whitelist HiSilicon Taishan v110 CPUs for Meltdown
Date: Tue, 5 Mar 2019 21:40:56 +0800 [thread overview]
Message-ID: <1551793258-5095-1-git-send-email-guohanjun@huawei.com> (raw)
From: Hanjun Guo <hanjun.guo@linaro.org>
We met boot stall on D06 which was:
[ 3.832098] SMP: Total of 64 processors activated.
[ 3.836907] CPU features: detected: GIC system register CPU interface
[ 3.843383] CPU features: detected: Privileged Access Never
[ 3.848978] CPU features: detected: User Access Override
[ 3.854316] CPU features: detected: Common not Private translations
[ 3.860609] CPU features: detected: RAS Extension Support
[ 3.866027] CPU features: detected: CRC32 instructions
[ 94.446811] CPU: All CPU(s) started at EL2
[ 94.451053] alternatives: patching kernel code
[ 94.499913] devtmpfs: initialized
It turns out that it stucks with the delay at boot for !KASLR kernels,
D06 machine is based on HiSilicon Taishan v110 CPU, which is not susceptible
to Meltdown, Will suggested that we can whitelist the MIDR in kpti_safe_list[]
table [1].
[1]:
http://lists.infradead.org/pipermail/linux-arm-kernel/2019-March/636314.html
Hanjun Guo (2):
arm64: Add MIDR encoding for HiSilicon Taishan CPUs
arm64: kpti: Whitelist HiSilicon Taishan v110 CPUs
arch/arm64/include/asm/cputype.h | 4 ++++
arch/arm64/kernel/cpufeature.c | 1 +
2 files changed, 5 insertions(+)
--
1.7.12.4
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next reply other threads:[~2019-03-05 13:43 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-05 13:40 Hanjun Guo [this message]
2019-03-05 13:40 ` [PATCH 1/2] arm64: Add MIDR encoding for HiSilicon Taishan CPUs Hanjun Guo
2019-03-05 13:40 ` [PATCH 2/2] arm64: kpti: Whitelist HiSilicon Taishan v110 CPUs Hanjun Guo
2019-03-19 14:03 ` [PATCH 0/2] Whitelist HiSilicon Taishan v110 CPUs for Meltdown Catalin Marinas
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