[PATCH 0/2] Whitelist HiSilicon Taishan v110 CPUs for Meltdown

[PATCH 0/2] Whitelist HiSilicon Taishan v110 CPUs for Meltdown

[Hanjun Guo]

From: Hanjun Guo <hanjun.guo@linaro.org>

We met boot stall on D06 which was:

[    3.832098] SMP: Total of 64 processors activated.
[    3.836907] CPU features: detected: GIC system register CPU interface
[    3.843383] CPU features: detected: Privileged Access Never
[    3.848978] CPU features: detected: User Access Override
[    3.854316] CPU features: detected: Common not Private translations
[    3.860609] CPU features: detected: RAS Extension Support
[    3.866027] CPU features: detected: CRC32 instructions
[   94.446811] CPU: All CPU(s) started at EL2
[   94.451053] alternatives: patching kernel code
[   94.499913] devtmpfs: initialized

It turns out that it stucks with the delay at boot for !KASLR kernels,
D06 machine is based on HiSilicon Taishan v110 CPU, which is not susceptible
to Meltdown, Will suggested that we can whitelist the MIDR in kpti_safe_list[]
table [1].

[1]:
http://lists.infradead.org/pipermail/linux-arm-kernel/2019-March/636314.html

Hanjun Guo (2):
  arm64: Add MIDR encoding for HiSilicon Taishan CPUs
  arm64: kpti: Whitelist HiSilicon Taishan v110 CPUs

 arch/arm64/include/asm/cputype.h | 4 ++++
 arch/arm64/kernel/cpufeature.c   | 1 +
 2 files changed, 5 insertions(+)

-- 
1.7.12.4


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[PATCH 1/2] arm64: Add MIDR encoding for HiSilicon Taishan CPUs

[Hanjun Guo]

From: Hanjun Guo <hanjun.guo@linaro.org>

Adding the MIDR encodings for HiSilicon Taishan v110 CPUs,
which is used in Kunpeng ARM64 server SoCs. TSV110 is the
abbreviation of Taishan v110.

Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Reviewed-by: John Garry <john.garry@huawei.com>
Reviewed-by: Zhangshaokun <zhangshaokun@hisilicon.com>
---
 arch/arm64/include/asm/cputype.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 951ed1a..832de73 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -76,6 +76,7 @@
 #define ARM_CPU_IMP_BRCM		0x42
 #define ARM_CPU_IMP_QCOM		0x51
 #define ARM_CPU_IMP_NVIDIA		0x4E
+#define ARM_CPU_IMP_HISI		0x48
 
 #define ARM_CPU_PART_AEM_V8		0xD0F
 #define ARM_CPU_PART_FOUNDATION		0xD00
@@ -104,6 +105,8 @@
 #define NVIDIA_CPU_PART_DENVER		0x003
 #define NVIDIA_CPU_PART_CARMEL		0x004
 
+#define HISI_CPU_PART_TSV110		0xD01
+
 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
 #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
 #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
@@ -122,6 +125,7 @@
 #define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)
 #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)
 #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
+#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
 
 #ifndef __ASSEMBLY__
 
-- 
1.7.12.4


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[PATCH 2/2] arm64: kpti: Whitelist HiSilicon Taishan v110 CPUs

[Hanjun Guo]

From: Hanjun Guo <hanjun.guo@linaro.org>

HiSilicon Taishan v110 CPUs didn't implement CSV3 field of the
ID_AA64PFR0_EL1 and are not susceptible to Meltdown, so whitelist
the MIDR in kpti_safe_list[] table.

Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Reviewed-by: John Garry <john.garry@huawei.com>
Reviewed-by: Zhangshaokun <zhangshaokun@hisilicon.com>
---
 arch/arm64/kernel/cpufeature.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index f6d84e2..0180f55 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -960,6 +960,7 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
 		MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
 		MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
 		MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
+		MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
 		{ /* sentinel */ }
 	};
 	char const *str = "command line option";
-- 
1.7.12.4


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Re: [PATCH 0/2] Whitelist HiSilicon Taishan v110 CPUs for Meltdown

[Catalin Marinas]

On Tue, Mar 05, 2019 at 09:40:56PM +0800, Hanjun Guo wrote:
> Hanjun Guo (2):
>   arm64: Add MIDR encoding for HiSilicon Taishan CPUs
>   arm64: kpti: Whitelist HiSilicon Taishan v110 CPUs

Queued for 5.1-rc2. Thanks.

-- 
Catalin

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