From: Hanjun Guo <guohanjun@huawei.com>
To: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will.deacon@arm.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>,
John Garry <john.garry@huawei.com>,
linuxarm@huawei.com, Zhangshaokun <zhangshaokun@hisilicon.com>,
Hanjun Guo <hanjun.guo@linaro.org>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/2] arm64: kpti: Whitelist HiSilicon Taishan v110 CPUs
Date: Tue, 5 Mar 2019 21:40:58 +0800 [thread overview]
Message-ID: <1551793258-5095-3-git-send-email-guohanjun@huawei.com> (raw)
In-Reply-To: <1551793258-5095-1-git-send-email-guohanjun@huawei.com>
From: Hanjun Guo <hanjun.guo@linaro.org>
HiSilicon Taishan v110 CPUs didn't implement CSV3 field of the
ID_AA64PFR0_EL1 and are not susceptible to Meltdown, so whitelist
the MIDR in kpti_safe_list[] table.
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Reviewed-by: John Garry <john.garry@huawei.com>
Reviewed-by: Zhangshaokun <zhangshaokun@hisilicon.com>
---
arch/arm64/kernel/cpufeature.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index f6d84e2..0180f55 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -960,6 +960,7 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
+ MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
{ /* sentinel */ }
};
char const *str = "command line option";
--
1.7.12.4
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next prev parent reply other threads:[~2019-03-05 13:43 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-05 13:40 [PATCH 0/2] Whitelist HiSilicon Taishan v110 CPUs for Meltdown Hanjun Guo
2019-03-05 13:40 ` [PATCH 1/2] arm64: Add MIDR encoding for HiSilicon Taishan CPUs Hanjun Guo
2019-03-05 13:40 ` Hanjun Guo [this message]
2019-03-19 14:03 ` [PATCH 0/2] Whitelist HiSilicon Taishan v110 CPUs for Meltdown Catalin Marinas
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