From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.2 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,T_DKIMWL_WL_HIGH,UNPARSEABLE_RELAY, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D976C282CE for ; Tue, 4 Jun 2019 10:15:25 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 70931216F4 for ; Tue, 4 Jun 2019 10:15:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="m41XILXA" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 70931216F4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ExBLxfiCigX2sW+AGqOt57HRT4Q05uo1B7DJSd564tc=; b=m41XILXA4Dp4ab q9yMEuzMajdZx8R2KVM7SMCitlQr09S6W4QAqvL/MRdjH0M2u8Hou/xJuS2PKXoGryY/TROLSrBta l6ZOv2PtQ0L5VxHPDc+KXAbWah0JOOJAm91CPYIrY33a168kDr9H19U3dZfY4KsygjfMhtssw87b7 RLiRtbl6i9CQjPdyKkHISUtp+2mVO9hZ2MQ1ked4tGKIXwQpBuVTg7Bw3xXU2eVK2BmkOgS9kvY8n DcfZpmIMTQt0u74Ea5cXDRVvGc0C6D1Uw4XwMn39zlH6hfqA2/72+eXdF8JqXNcHPh+qH46PjnZWi SYDVb6Q3JRkzebiVrTFw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hY6TS-0003FW-2I; Tue, 04 Jun 2019 10:15:22 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hY6Sg-0000W9-7D for linux-arm-kernel@lists.infradead.org; Tue, 04 Jun 2019 10:15:10 +0000 X-UUID: 242bbf55b7b44806813dbfdefb8f6fe8-20190604 X-UUID: 242bbf55b7b44806813dbfdefb8f6fe8-20190604 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 604291619; Tue, 04 Jun 2019 02:12:05 -0800 Received: from MTKMBS01N1.mediatek.inc (172.21.101.68) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Jun 2019 03:12:04 -0700 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Jun 2019 18:12:01 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 4 Jun 2019 18:12:01 +0800 From: Stu Hsieh To: Mauro Carvalho Chehab , Rob Herring , CK Hu Subject: [PATCH v4 09/14] [media] mtk-mipicsi: add ISR for writing the data to buffer Date: Tue, 4 Jun 2019 18:11:50 +0800 Message-ID: <1559643115-15124-10-git-send-email-stu.hsieh@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1559643115-15124-1-git-send-email-stu.hsieh@mediatek.com> References: <1559643115-15124-1-git-send-email-stu.hsieh@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190604_031434_729677_334D3850 X-CRM114-Status: GOOD ( 20.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Stu Hsieh , Matthias Brugger , linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch add ISR for writing the data to buffer When mipicsi HW complete to write the data in buffer, the interrupt woulb be trigger. So, the ISR need to clear interrupt status for next interrupt. Signed-off-by: Stu Hsieh --- .../media/platform/mtk-mipicsi/mtk_mipicsi.c | 122 +++++++++++++++++- 1 file changed, 120 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c index 8bb40656bcb1..dc5c5c888914 100644 --- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c +++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include @@ -88,6 +89,8 @@ #define CAMSV_MODULE_EN 0x10 #define CAMSV_FMT_SEL 0x14 #define CAMSV_INT_EN 0x18 +#define CAMSV_INT_STATUS 0x1C +#define PASS1_DONE_STATUS 10 #define CAMSV_SW_CTL 0x20 #define CAMSV_CLK_EN 0x30 @@ -129,6 +132,8 @@ struct mtk_mipicsi_channel { void __iomem *seninf_mux; void __iomem *camsv; struct clk *clk; + unsigned int irq; + bool irq_status; }; struct mtk_mipicsi_dev { @@ -547,26 +552,31 @@ static void mtk_mipicsi_cmos_vf_enable(struct mtk_mipicsi_dev *mipicsi, unsigned int max_camsv_num, bool enable) { + struct mtk_mipicsi_channel *ch = mipicsi->channel; void __iomem *base = NULL; u32 mask = enable ? (u32)1 : ~(u32)1; int i; for (i = 0; i < max_camsv_num; i++) if (((mipicsi->link_reg_val >> i) & 0x01U) == 0x01U) { + base = ch[i].camsv; if (enable) { + enable_irq(ch[i].irq); + /*enable cmos_en and vf_en*/ - base = mipicsi->camsv[i]; writel(readl(base + CAMSV_TG_SEN_MODE) | mask, base + CAMSV_TG_SEN_MODE); writel(readl(base + CAMSV_TG_VF_CON) | mask, base + CAMSV_TG_VF_CON); } else { /*disable cmos_en and vf_en*/ - base = mipicsi->camsv[i]; writel(readl(base + CAMSV_TG_SEN_MODE) & mask, base + CAMSV_TG_SEN_MODE); writel(readl(base + CAMSV_TG_VF_CON) & mask, base + CAMSV_TG_VF_CON); + + disable_irq(ch[i].irq); + ch[i].irq_status = false; } } } @@ -820,9 +830,100 @@ static const struct v4l2_ioctl_ops mtk_mipicsi_ioctl_ops = { .vidioc_unsubscribe_event = v4l2_event_unsubscribe, }; +static int get_irq_channel(struct mtk_mipicsi_dev *mipicsi) +{ + struct mtk_mipicsi_channel *ch = mipicsi->channel; + int i; + u32 int_reg_val; + + for (i = 0; i < mipicsi->camsv_num; i++) { + int_reg_val = readl(ch[i].camsv + CAMSV_INT_STATUS); + if ((int_reg_val & (1 << PASS1_DONE_STATUS)) != 0) + return i; + } + + return -1; +} + +static void mtk_mipicsi_irq_buf_process(struct mtk_mipicsi_dev *mipicsi) +{ + struct mtk_mipicsi_channel *ch = mipicsi->channel; + unsigned int i = 0; + struct mtk_mipicsi_buf *new_cam_buf = NULL; + struct mtk_mipicsi_buf *tmp = NULL; + unsigned int index = 0; + unsigned int next = 0; + + for (i = 0; i < mipicsi->camsv_num; ++i) + ch[i].irq_status = false; + + i = 0; + + /* only one buffer left */ + if ((&(mipicsi->fb_list))->next->next == &(mipicsi->fb_list)) + return; + + /*for each fb_lst 2 times to get the top 2 buffer.*/ + list_for_each_entry_safe(new_cam_buf, tmp, + &(mipicsi->fb_list), queue) { + if (i == 0) { + index = new_cam_buf->vb->index; + } else { + next = new_cam_buf->vb->index; + break; + } + ++i; + } + + /* + * fb_list has one more buffer. Free the first buffer to user + * and fill the second buffer to HW. + */ + vb2_buffer_done(mipicsi->cam_buf[index].vb, + VB2_BUF_STATE_DONE); + + list_del_init(&(mipicsi->cam_buf[index].queue)); +} + +static irqreturn_t mtk_mipicsi_isr(int irq, void *data) +{ + struct mtk_mipicsi_dev *mipicsi = data; + struct device *dev = &mipicsi->pdev->dev; + struct mtk_mipicsi_channel *ch = mipicsi->channel; + unsigned long flags = 0; + int isr_ch; + u8 irq_cnt = 0, i = 0; + + spin_lock_irqsave(&mipicsi->irqlock, flags); + + isr_ch = get_irq_channel(mipicsi); + if (isr_ch < 0) { + dev_info(dev, "no interrupt occur"); + spin_unlock_irqrestore(&mipicsi->irqlock, flags); + return IRQ_HANDLED; + } + + /* clear interrupt */ + writel(1UL << PASS1_DONE_STATUS, + ch[isr_ch].camsv + CAMSV_INT_STATUS); + ch[isr_ch].irq_status = true; + for (i = 0U; i < mipicsi->camsv_num; ++i) { + if (ch[i].irq_status) + ++irq_cnt; + } + + if (irq_cnt == mipicsi->link) + mtk_mipicsi_irq_buf_process(mipicsi); + spin_unlock_irqrestore(&mipicsi->irqlock, flags); + + return IRQ_HANDLED; +} + static int seninf_mux_camsv_node_parse(struct mtk_mipicsi_dev *mipicsi, int index) { + int ret; + int irq; struct clk *clk = NULL; struct device *dev = NULL; struct resource *res = NULL; @@ -854,6 +955,23 @@ static int seninf_mux_camsv_node_parse(struct mtk_mipicsi_dev *mipicsi, } ch[index].clk = clk; + irq = of_irq_get(np, 0); + if (irq <= 0) { + dev_err(dev, "get irq fail in %s node\n", np->full_name); + return -ENODEV; + } + ch[index].irq = irq; + + ret = devm_request_irq(dev, irq, + mtk_mipicsi_isr, 0, + mipicsi->drv_name, mipicsi); + if (ret != 0) { + dev_err(dev, "%s irq register failed\n", np->full_name); + return -ENODEV; + } + disable_irq(ch[index].irq); + ch[index].irq_status = false; + res = platform_get_resource(camdma_pdev, IORESOURCE_MEM, 0); if (res == NULL) { dev_err(dev, "get seninf_mux memory failed in %s node\n", -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel