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From: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
To: wg@grandegger.com, mkl@pengutronix.de, davem@davemloft.net,
	michal.simek@xilinx.com
Cc: netdev@vger.kernel.org,
	Srinivas Neeli <srinivas.neeli@xilinx.com>,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, linux-can@vger.kernel.org
Subject: [PATCH 5/5] can: xilinx_can: Fix the data phase btr1 calculation
Date: Mon, 12 Aug 2019 12:58:34 +0530	[thread overview]
Message-ID: <1565594914-18999-6-git-send-email-appana.durga.rao@xilinx.com> (raw)
In-Reply-To: <1565594914-18999-1-git-send-email-appana.durga.rao@xilinx.com>

From: Srinivas Neeli <srinivas.neeli@xilinx.com>

While calculating bitrate for the data phase, the driver is using phase
segment 1 of the arbitration phase instead of the data phase.

Signed-off-by: Srinivas Neeli <srinivas.neeli@xilinx.com>
Acked-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
 drivers/net/can/xilinx_can.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c
index 4cb8c1c9..ab26691 100644
--- a/drivers/net/can/xilinx_can.c
+++ b/drivers/net/can/xilinx_can.c
@@ -425,7 +425,7 @@ static int xcan_set_bittiming(struct net_device *ndev)
 		btr0 = dbt->brp - 1;
 
 		/* Setting Time Segment 1 in BTR Register */
-		btr1 = dbt->prop_seg + bt->phase_seg1 - 1;
+		btr1 = dbt->prop_seg + dbt->phase_seg1 - 1;
 
 		/* Setting Time Segment 2 in BTR Register */
 		btr1 |= (dbt->phase_seg2 - 1) << priv->devtype.btr_ts2_shift;
-- 
2.7.4


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  parent reply	other threads:[~2019-08-12  7:30 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-12  7:28 [PATCH 0/5] can: xilinx_can: Bug fixes Appana Durga Kedareswara rao
2019-08-12  7:28 ` [PATCH 1/5] can: xilinx_can: defer the probe if clock is not found Appana Durga Kedareswara rao
2019-08-12  9:03   ` Marc Kleine-Budde
2019-08-12  9:07     ` Appana Durga Kedareswara Rao
2019-08-12  7:28 ` [PATCH 2/5] can: xilinx_can: Fix FSR register handling in the rx path Appana Durga Kedareswara rao
2019-08-12  7:28 ` [PATCH 3/5] can: xilinx_can: Fix the data updation logic for CANFD FD frames Appana Durga Kedareswara rao
2019-08-12  7:28 ` [PATCH 4/5] can: xilinx_can: Fix FSR register FL and RI mask values for canfd 2.0 Appana Durga Kedareswara rao
2019-08-12  7:28 ` Appana Durga Kedareswara rao [this message]
2019-08-12  9:05 ` [PATCH 0/5] can: xilinx_can: Bug fixes Marc Kleine-Budde
2019-08-12  9:09   ` Appana Durga Kedareswara Rao
2019-08-12  9:10   ` Marc Kleine-Budde
2019-08-12 10:18     ` Michal Simek
2019-08-12 10:47       ` Marc Kleine-Budde
2019-08-12 10:57         ` Michal Simek
2019-08-12 10:59           ` Marc Kleine-Budde
2019-08-12 11:05             ` Michal Simek

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