From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Nicolas Boichat <drinkcat@chromium.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Rob Herring <robh@kernel.org>
Cc: James Liao <jamesjj.liao@mediatek.com>,
Weiyi Lu <weiyi.lu@mediatek.com>,
srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org,
Fan Chen <fan.chen@mediatek.com>,
linux-mediatek@lists.infradead.org, CK Hu <ck.hu@mediatek.com>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v1 3/3] arm64: dts: Add power-domains properity to mfgcfg
Date: Mon, 2 Sep 2019 16:35:10 +0800 [thread overview]
Message-ID: <1567413310-2589-4-git-send-email-weiyi.lu@mediatek.com> (raw)
In-Reply-To: <1567413310-2589-1-git-send-email-weiyi.lu@mediatek.com>
mfgcfg clock is under MFG_ASYNC power domain
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index c2749c4..3f948e9 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -388,6 +388,7 @@
compatible = "mediatek,mt8183-mfgcfg", "syscon";
reg = <0 0x13000000 0 0x1000>;
#clock-cells = <1>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_MFG_ASYNC>;
};
mmsys: syscon@14000000 {
--
1.8.1.1.dirty
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next prev parent reply other threads:[~2019-09-02 8:35 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-02 8:35 [PATCH v1 0/3] Runtime PM support for MT8183 mcucfg clock provider Weiyi Lu
2019-09-02 8:35 ` [PATCH v1 1/3] clk: mediatek: Register clock gate with device Weiyi Lu
2019-09-02 8:35 ` [PATCH v1 2/3] clk: mediatek: Runtime PM support for MT8183 mcucfg clock provider Weiyi Lu
2019-09-02 8:35 ` Weiyi Lu [this message]
2019-09-02 15:55 ` [PATCH v1 3/3] arm64: dts: Add power-domains properity to mfgcfg kbuild test robot
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