From: Rajan Vaja <rajan.vaja@xilinx.com>
To: mturquette@baylibre.com, sboyd@kernel.org,
michal.simek@xilinx.com, m.tretter@pengutronix.de,
jollys@xilinx.com
Cc: Jolly Shah <jolly.shah@xilinx.com>,
Rajan Vaja <rajan.vaja@xilinx.com>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH] clk: zynqmp: Correct bit index for divider flag
Date: Thu, 7 Nov 2019 01:01:30 -0800 [thread overview]
Message-ID: <1573117290-7990-1-git-send-email-rajan.vaja@xilinx.com> (raw)
Update divider flag bit index to match with firmware.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
drivers/clk/zynqmp/divider.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
index d8f5b70d..9e60834 100644
--- a/drivers/clk/zynqmp/divider.c
+++ b/drivers/clk/zynqmp/divider.c
@@ -2,7 +2,7 @@
/*
* Zynq UltraScale+ MPSoC Divider support
*
- * Copyright (C) 2016-2018 Xilinx
+ * Copyright (C) 2016-2019 Xilinx
*
* Adjustable divider clock implementation
*/
@@ -25,7 +25,7 @@
#define to_zynqmp_clk_divider(_hw) \
container_of(_hw, struct zynqmp_clk_divider, hw)
-#define CLK_FRAC BIT(13) /* has a fractional parent */
+#define CLK_FRAC BIT(8) /* has a fractional parent */
/**
* struct zynqmp_clk_divider - adjustable divider clock
--
2.7.4
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next reply other threads:[~2019-11-07 9:02 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-07 9:01 Rajan Vaja [this message]
2019-11-07 17:01 ` [PATCH] clk: zynqmp: Correct bit index for divider flag Michael Tretter
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