* [PATCH v4 0/2] ASoC: mt8183: fix audio playback slowly after playback @ 2019-10-16 5:59 Jiaxin Yu 2019-10-16 5:59 ` [PATCH v4 1/2] dt-bindings: mediatek: mt8183: Add #reset-cells Jiaxin Yu 2019-10-16 5:59 ` [PATCH v4 2/2] watchdog: mtk_wdt: mt8183: Add reset controller Jiaxin Yu 0 siblings, 2 replies; 6+ messages in thread From: Jiaxin Yu @ 2019-10-16 5:59 UTC (permalink / raw) To: broonie, mark.rutland, robh+dt, linux, wim Cc: alsa-devel, yong.liang, lgirdwood, jiaxin.yu, perex, tzungbi, linux-mediatek, eason.yen, linux-arm-kernel This series patches add reset controller for MT8183, and audio will use it in machine driver during bootup, they depend on the for-next. v4 changes: 1. Fixed wrong signed-off as correct mail suffix. 2. Fixed patch subject that add patch version. v3 changes: 1. https://patchwork.kernel.org/patch/11164283/ and https://patchwork.kernel.org/patch/11164305/ has been merged. 2. Change the name of mtk_wdt_compatible to mtk_wdt_data. 3. Remove toprgu_reset struct and use mtk_wdt_dev instead. 4. Get the value of sw_rst_num from .h file. 5. Adddd mt2712-resets.h for mt2712. 6. Improve commit message. v2 changes: 1. remove "WIP" that in the title of patches 2. add hyper link for the patch that depends on 3. patchwork list: https://patchwork.kernel.org/cover/11164285/ https://patchwork.kernel.org/patch/11164295/ https://patchwork.kernel.org/patch/11164299/ https://patchwork.kernel.org/patch/11164283/ https://patchwork.kernel.org/patch/11164305/ v1 changes: 1. patchwork list: https://patchwork.kernel.org/cover/11164173/ https://patchwork.kernel.org/patch/11164181/ https://patchwork.kernel.org/patch/11164185/ https://patchwork.kernel.org/patch/11164187/ https://patchwork.kernel.org/patch/11164175/ yong.liang (2): dt-bindings: mediatek: mt8183: Add #reset-cells watchdog: mtk_wdt: mt8183: Add reset controller .../devicetree/bindings/watchdog/mtk-wdt.txt | 10 +- drivers/watchdog/Kconfig | 1 + drivers/watchdog/mtk_wdt.c | 111 +++++++++++++++++- .../reset-controller/mt2712-resets.h | 22 ++++ .../reset-controller/mt8183-resets.h | 15 +++ 5 files changed, 155 insertions(+), 4 deletions(-) create mode 100644 include/dt-bindings/reset-controller/mt2712-resets.h -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v4 1/2] dt-bindings: mediatek: mt8183: Add #reset-cells 2019-10-16 5:59 [PATCH v4 0/2] ASoC: mt8183: fix audio playback slowly after playback Jiaxin Yu @ 2019-10-16 5:59 ` Jiaxin Yu 2019-11-13 9:46 ` Jiaxin Yu 2019-10-16 5:59 ` [PATCH v4 2/2] watchdog: mtk_wdt: mt8183: Add reset controller Jiaxin Yu 1 sibling, 1 reply; 6+ messages in thread From: Jiaxin Yu @ 2019-10-16 5:59 UTC (permalink / raw) To: broonie, mark.rutland, robh+dt, linux, wim Cc: alsa-devel, yong.liang, lgirdwood, jiaxin.yu, perex, tzungbi, linux-mediatek, eason.yen, linux-arm-kernel From: "yong.liang" <yong.liang@mediatek.com> Add #reset-cells property and update example Signed-off-by: yong.liang <yong.liang@mediatek.com> --- .../devicetree/bindings/watchdog/mtk-wdt.txt | 10 ++++++--- .../reset-controller/mt2712-resets.h | 22 +++++++++++++++++++ .../reset-controller/mt8183-resets.h | 15 +++++++++++++ 3 files changed, 44 insertions(+), 3 deletions(-) create mode 100644 include/dt-bindings/reset-controller/mt2712-resets.h diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt index 3ee625d0812f..4dd36bd3f1ad 100644 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt @@ -4,6 +4,7 @@ Required properties: - compatible should contain: "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701 + "mediatek,mt2712-wdt", "mediatek,mt6589-wdt": for MT2712 "mediatek,mt6589-wdt": for MT6589 "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797 "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622 @@ -16,11 +17,14 @@ Required properties: Optional properties: - timeout-sec: contains the watchdog timeout in seconds. +- #reset-cells: Should be 1. Example: -wdt: watchdog@10000000 { - compatible = "mediatek,mt6589-wdt"; - reg = <0x10000000 0x18>; +watchdog: watchdog@10007000 { + compatible = "mediatek,mt8183-wdt", + "mediatek,mt6589-wdt"; + reg = <0 0x10007000 0 0x100>; timeout-sec = <10>; + #reset-cells = <1>; }; diff --git a/include/dt-bindings/reset-controller/mt2712-resets.h b/include/dt-bindings/reset-controller/mt2712-resets.h new file mode 100644 index 000000000000..e81c8bb311b7 --- /dev/null +++ b/include/dt-bindings/reset-controller/mt2712-resets.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Yong Liang <yong.liang@mediatek.com> + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2712 +#define _DT_BINDINGS_RESET_CONTROLLER_MT2712 + +#define MT2712_TOPRGU_INFRA_SW_RST 0 +#define MT2712_TOPRGU_MM_SW_RST 1 +#define MT2712_TOPRGU_MFG_SW_RST 2 +#define MT2712_TOPRGU_VENC_SW_RST 3 +#define MT2712_TOPRGU_VDEC_SW_RST 4 +#define MT2712_TOPRGU_IMG_SW_RST 5 +#define MT2712_TOPRGU_INFRA_AO_SW_RST 8 +#define MT2712_TOPRGU_USB_SW_RST 9 +#define MT2712_TOPRGU_APMIXED_SW_RST 10 + +#define MT2712_TOPRGU_SW_RST_NUM 10 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2712 */ diff --git a/include/dt-bindings/reset-controller/mt8183-resets.h b/include/dt-bindings/reset-controller/mt8183-resets.h index 8804e34ebdd4..d582da6bedae 100644 --- a/include/dt-bindings/reset-controller/mt8183-resets.h +++ b/include/dt-bindings/reset-controller/mt8183-resets.h @@ -78,4 +78,19 @@ #define MT8183_INFRACFG_AO_I2C7_SW_RST 126 #define MT8183_INFRACFG_AO_I2C8_SW_RST 127 +#define MT8183_TOPRGU_MM_SW_RST 1 +#define MT8183_TOPRGU_MFG_SW_RST 2 +#define MT8183_TOPRGU_VENC_SW_RST 3 +#define MT8183_TOPRGU_VDEC_SW_RST 4 +#define MT8183_TOPRGU_IMG_SW_RST 5 +#define MT8183_TOPRGU_MD_SW_RST 7 +#define MT8183_TOPRGU_CONN_SW_RST 9 +#define MT8183_TOPRGU_CONN_MCU_SW_RST 12 +#define MT8183_TOPRGU_IPU0_SW_RST 14 +#define MT8183_TOPRGU_IPU1_SW_RST 15 +#define MT8183_TOPRGU_AUDIO_SW_RST 17 +#define MT8183_TOPRGU_CAMSYS_SW_RST 18 + +#define MT8183_TOPRGU_SW_RST_NUM 18 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8183 */ -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v4 1/2] dt-bindings: mediatek: mt8183: Add #reset-cells 2019-10-16 5:59 ` [PATCH v4 1/2] dt-bindings: mediatek: mt8183: Add #reset-cells Jiaxin Yu @ 2019-11-13 9:46 ` Jiaxin Yu 0 siblings, 0 replies; 6+ messages in thread From: Jiaxin Yu @ 2019-11-13 9:46 UTC (permalink / raw) To: broonie, yingjoe.chen, linux, p.zabel Cc: mark.rutland, alsa-devel, yong.liang, lgirdwood, perex, tzungbi, robh+dt, linux-mediatek, eason.yen, wim, linux-arm-kernel On Wed, 2019-10-16 at 13:59 +0800, Jiaxin Yu wrote: > From: "yong.liang" <yong.liang@mediatek.com> > > Add #reset-cells property and update example > > Signed-off-by: yong.liang <yong.liang@mediatek.com> > --- > .../devicetree/bindings/watchdog/mtk-wdt.txt | 10 ++++++--- > .../reset-controller/mt2712-resets.h | 22 +++++++++++++++++++ > .../reset-controller/mt8183-resets.h | 15 +++++++++++++ > 3 files changed, 44 insertions(+), 3 deletions(-) > create mode 100644 include/dt-bindings/reset-controller/mt2712-resets.h > > diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt > index 3ee625d0812f..4dd36bd3f1ad 100644 > --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt > +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt > @@ -4,6 +4,7 @@ Required properties: > > - compatible should contain: > "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701 > + "mediatek,mt2712-wdt", "mediatek,mt6589-wdt": for MT2712 > "mediatek,mt6589-wdt": for MT6589 > "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797 > "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622 > @@ -16,11 +17,14 @@ Required properties: > > Optional properties: > - timeout-sec: contains the watchdog timeout in seconds. > +- #reset-cells: Should be 1. > > Example: > > -wdt: watchdog@10000000 { > - compatible = "mediatek,mt6589-wdt"; > - reg = <0x10000000 0x18>; > +watchdog: watchdog@10007000 { > + compatible = "mediatek,mt8183-wdt", > + "mediatek,mt6589-wdt"; > + reg = <0 0x10007000 0 0x100>; > timeout-sec = <10>; > + #reset-cells = <1>; > }; > diff --git a/include/dt-bindings/reset-controller/mt2712-resets.h b/include/dt-bindings/reset-controller/mt2712-resets.h > new file mode 100644 > index 000000000000..e81c8bb311b7 > --- /dev/null > +++ b/include/dt-bindings/reset-controller/mt2712-resets.h > @@ -0,0 +1,22 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2019 MediaTek Inc. > + * Author: Yong Liang <yong.liang@mediatek.com> > + */ > + > +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2712 > +#define _DT_BINDINGS_RESET_CONTROLLER_MT2712 > + > +#define MT2712_TOPRGU_INFRA_SW_RST 0 > +#define MT2712_TOPRGU_MM_SW_RST 1 > +#define MT2712_TOPRGU_MFG_SW_RST 2 > +#define MT2712_TOPRGU_VENC_SW_RST 3 > +#define MT2712_TOPRGU_VDEC_SW_RST 4 > +#define MT2712_TOPRGU_IMG_SW_RST 5 > +#define MT2712_TOPRGU_INFRA_AO_SW_RST 8 > +#define MT2712_TOPRGU_USB_SW_RST 9 > +#define MT2712_TOPRGU_APMIXED_SW_RST 10 > + > +#define MT2712_TOPRGU_SW_RST_NUM 10 > + > +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2712 */ > diff --git a/include/dt-bindings/reset-controller/mt8183-resets.h b/include/dt-bindings/reset-controller/mt8183-resets.h > index 8804e34ebdd4..d582da6bedae 100644 > --- a/include/dt-bindings/reset-controller/mt8183-resets.h > +++ b/include/dt-bindings/reset-controller/mt8183-resets.h > @@ -78,4 +78,19 @@ > #define MT8183_INFRACFG_AO_I2C7_SW_RST 126 > #define MT8183_INFRACFG_AO_I2C8_SW_RST 127 > > +#define MT8183_TOPRGU_MM_SW_RST 1 > +#define MT8183_TOPRGU_MFG_SW_RST 2 > +#define MT8183_TOPRGU_VENC_SW_RST 3 > +#define MT8183_TOPRGU_VDEC_SW_RST 4 > +#define MT8183_TOPRGU_IMG_SW_RST 5 > +#define MT8183_TOPRGU_MD_SW_RST 7 > +#define MT8183_TOPRGU_CONN_SW_RST 9 > +#define MT8183_TOPRGU_CONN_MCU_SW_RST 12 > +#define MT8183_TOPRGU_IPU0_SW_RST 14 > +#define MT8183_TOPRGU_IPU1_SW_RST 15 > +#define MT8183_TOPRGU_AUDIO_SW_RST 17 > +#define MT8183_TOPRGU_CAMSYS_SW_RST 18 > + > +#define MT8183_TOPRGU_SW_RST_NUM 18 > + > #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8183 */ Hi, Philipp && Guenter, Could you help to review these two patches about mediatek reset controller? If this has any questions, please let me know, thanks a lot. Jiaxin.Yu _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v4 2/2] watchdog: mtk_wdt: mt8183: Add reset controller 2019-10-16 5:59 [PATCH v4 0/2] ASoC: mt8183: fix audio playback slowly after playback Jiaxin Yu 2019-10-16 5:59 ` [PATCH v4 1/2] dt-bindings: mediatek: mt8183: Add #reset-cells Jiaxin Yu @ 2019-10-16 5:59 ` Jiaxin Yu 2019-11-14 7:34 ` Yingjoe Chen 2019-11-14 7:41 ` Yingjoe Chen 1 sibling, 2 replies; 6+ messages in thread From: Jiaxin Yu @ 2019-10-16 5:59 UTC (permalink / raw) To: broonie, mark.rutland, robh+dt, linux, wim Cc: alsa-devel, yong.liang, lgirdwood, jiaxin.yu, perex, tzungbi, linux-mediatek, eason.yen, linux-arm-kernel From: "yong.liang" <yong.liang@mediatek.com> Add reset controller API in watchdog driver. Besides watchdog, MTK toprgu module also provide sub-system (eg, audio, camera, codec and connectivity) software reset functionality. Signed-off-by: yong.liang <yong.liang@mediatek.com> --- drivers/watchdog/Kconfig | 1 + drivers/watchdog/mtk_wdt.c | 111 ++++++++++++++++++++++++++++++++++++- 2 files changed, 111 insertions(+), 1 deletion(-) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 2e07caab9db2..629249fe5305 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -717,6 +717,7 @@ config MEDIATEK_WATCHDOG tristate "Mediatek SoCs watchdog support" depends on ARCH_MEDIATEK || COMPILE_TEST select WATCHDOG_CORE + select RESET_CONTROLLER help Say Y here to include support for the watchdog timer in Mediatek SoCs. diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index 9c3d0033260d..d29484c7940a 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -9,6 +9,9 @@ * Based on sunxi_wdt.c */ +#include <dt-bindings/reset-controller/mt2712-resets.h> +#include <dt-bindings/reset-controller/mt8183-resets.h> +#include <linux/delay.h> #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> @@ -16,10 +19,12 @@ #include <linux/module.h> #include <linux/moduleparam.h> #include <linux/of.h> +#include <linux/of_device.h> #include <linux/platform_device.h> +#include <linux/reset-controller.h> +#include <linux/slab.h> #include <linux/types.h> #include <linux/watchdog.h> -#include <linux/delay.h> #define WDT_MAX_TIMEOUT 31 #define WDT_MIN_TIMEOUT 1 @@ -44,6 +49,9 @@ #define WDT_SWRST 0x14 #define WDT_SWRST_KEY 0x1209 +#define WDT_SWSYSRST 0x18U +#define WDT_SWSYS_RST_KEY 0x88000000 + #define DRV_NAME "mtk-wdt" #define DRV_VERSION "1.0" @@ -53,8 +61,99 @@ static unsigned int timeout; struct mtk_wdt_dev { struct watchdog_device wdt_dev; void __iomem *wdt_base; + spinlock_t lock; /* protects WDT_SWSYSRST reg */ + struct reset_controller_dev rcdev; +}; + +struct mtk_wdt_data { + int sw_rst_num; }; +static const struct mtk_wdt_data mt2712_data = { + .sw_rst_num = MT2712_TOPRGU_SW_RST_NUM, +}; + +static const struct mtk_wdt_data mt8183_data = { + .sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, +}; + +static int toprgu_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + unsigned int tmp; + unsigned long flags; + struct mtk_wdt_dev *data = + container_of(rcdev, struct mtk_wdt_dev, rcdev); + + spin_lock_irqsave(&data->lock, flags); + + tmp = __raw_readl(data->wdt_base + WDT_SWSYSRST); + tmp |= BIT(id); + tmp |= WDT_SWSYS_RST_KEY; + writel(tmp, data->wdt_base + WDT_SWSYSRST); + + spin_unlock_irqrestore(&data->lock, flags); + + return 0; +} + +static int toprgu_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + unsigned int tmp; + unsigned long flags; + struct mtk_wdt_dev *data = + container_of(rcdev, struct mtk_wdt_dev, rcdev); + + spin_lock_irqsave(&data->lock, flags); + + tmp = __raw_readl(data->wdt_base + WDT_SWSYSRST); + tmp &= ~BIT(id); + tmp |= WDT_SWSYS_RST_KEY; + writel(tmp, data->wdt_base + WDT_SWSYSRST); + + spin_unlock_irqrestore(&data->lock, flags); + + return 0; +} + +static int toprgu_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int ret; + + ret = toprgu_reset_assert(rcdev, id); + if (ret) + return ret; + + return toprgu_reset_deassert(rcdev, id); +} + +static const struct reset_control_ops toprgu_reset_ops = { + .assert = toprgu_reset_assert, + .deassert = toprgu_reset_deassert, + .reset = toprgu_reset, +}; + +static int toprgu_register_reset_controller(struct platform_device *pdev, + int rst_num) +{ + int ret; + struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev); + + spin_lock_init(&mtk_wdt->lock); + + mtk_wdt->rcdev.owner = THIS_MODULE; + mtk_wdt->rcdev.nr_resets = rst_num; + mtk_wdt->rcdev.ops = &toprgu_reset_ops; + mtk_wdt->rcdev.of_node = pdev->dev.of_node; + ret = reset_controller_register(&mtk_wdt->rcdev); + if (ret != 0) + dev_err(&pdev->dev, + "couldn't register wdt reset controller: %d\n", ret); + return ret; +} + static int mtk_wdt_restart(struct watchdog_device *wdt_dev, unsigned long action, void *data) { @@ -155,6 +254,7 @@ static int mtk_wdt_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct mtk_wdt_dev *mtk_wdt; + struct mtk_wdt_data *wdt_data; int err; mtk_wdt = devm_kzalloc(dev, sizeof(*mtk_wdt), GFP_KERNEL); @@ -190,6 +290,13 @@ static int mtk_wdt_probe(struct platform_device *pdev) dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n", mtk_wdt->wdt_dev.timeout, nowayout); + wdt_data = (struct mtk_wdt_data *)of_device_get_match_data(dev); + if (wdt_data) { + err = toprgu_register_reset_controller(pdev, + wdt_data->sw_rst_num); + if (err) + return err; + } return 0; } @@ -218,7 +325,9 @@ static int mtk_wdt_resume(struct device *dev) #endif static const struct of_device_id mtk_wdt_dt_ids[] = { + { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, { .compatible = "mediatek,mt6589-wdt" }, + { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids); -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v4 2/2] watchdog: mtk_wdt: mt8183: Add reset controller 2019-10-16 5:59 ` [PATCH v4 2/2] watchdog: mtk_wdt: mt8183: Add reset controller Jiaxin Yu @ 2019-11-14 7:34 ` Yingjoe Chen 2019-11-14 7:41 ` Yingjoe Chen 1 sibling, 0 replies; 6+ messages in thread From: Yingjoe Chen @ 2019-11-14 7:34 UTC (permalink / raw) To: Jiaxin Yu Cc: mark.rutland, alsa-devel, yong.liang, robh+dt, lgirdwood, tzungbi, broonie, linux-mediatek, linux-arm-kernel, eason.yen, perex, wim, linux On Wed, 2019-10-16 at 13:59 +0800, Jiaxin Yu wrote: > From: "yong.liang" <yong.liang@mediatek.com> > > Add reset controller API in watchdog driver. > Besides watchdog, MTK toprgu module also provide sub-system (eg, audio, > camera, codec and connectivity) software reset functionality. > > Signed-off-by: yong.liang <yong.liang@mediatek.com> Jiaxin, Since you send this patch, you should add your signed-off-by tag here as well. This looks good to me otherwise. Feel free to add my reviewed by if you want: Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Joe.C > --- > drivers/watchdog/Kconfig | 1 + > drivers/watchdog/mtk_wdt.c | 111 ++++++++++++++++++++++++++++++++++++- > 2 files changed, 111 insertions(+), 1 deletion(-) > > diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig > index 2e07caab9db2..629249fe5305 100644 > --- a/drivers/watchdog/Kconfig > +++ b/drivers/watchdog/Kconfig > @@ -717,6 +717,7 @@ config MEDIATEK_WATCHDOG > tristate "Mediatek SoCs watchdog support" > depends on ARCH_MEDIATEK || COMPILE_TEST > select WATCHDOG_CORE > + select RESET_CONTROLLER > help > Say Y here to include support for the watchdog timer > in Mediatek SoCs. > diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c > index 9c3d0033260d..d29484c7940a 100644 > --- a/drivers/watchdog/mtk_wdt.c > +++ b/drivers/watchdog/mtk_wdt.c > @@ -9,6 +9,9 @@ > * Based on sunxi_wdt.c > */ > > +#include <dt-bindings/reset-controller/mt2712-resets.h> > +#include <dt-bindings/reset-controller/mt8183-resets.h> > +#include <linux/delay.h> > #include <linux/err.h> > #include <linux/init.h> > #include <linux/io.h> > @@ -16,10 +19,12 @@ > #include <linux/module.h> > #include <linux/moduleparam.h> > #include <linux/of.h> > +#include <linux/of_device.h> > #include <linux/platform_device.h> > +#include <linux/reset-controller.h> > +#include <linux/slab.h> > #include <linux/types.h> > #include <linux/watchdog.h> > -#include <linux/delay.h> > > #define WDT_MAX_TIMEOUT 31 > #define WDT_MIN_TIMEOUT 1 > @@ -44,6 +49,9 @@ > #define WDT_SWRST 0x14 > #define WDT_SWRST_KEY 0x1209 > > +#define WDT_SWSYSRST 0x18U > +#define WDT_SWSYS_RST_KEY 0x88000000 > + > #define DRV_NAME "mtk-wdt" > #define DRV_VERSION "1.0" > > @@ -53,8 +61,99 @@ static unsigned int timeout; > struct mtk_wdt_dev { > struct watchdog_device wdt_dev; > void __iomem *wdt_base; > + spinlock_t lock; /* protects WDT_SWSYSRST reg */ > + struct reset_controller_dev rcdev; > +}; > + > +struct mtk_wdt_data { > + int sw_rst_num; > }; > > +static const struct mtk_wdt_data mt2712_data = { > + .sw_rst_num = MT2712_TOPRGU_SW_RST_NUM, > +}; > + > +static const struct mtk_wdt_data mt8183_data = { > + .sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, > +}; > + > +static int toprgu_reset_assert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + unsigned int tmp; > + unsigned long flags; > + struct mtk_wdt_dev *data = > + container_of(rcdev, struct mtk_wdt_dev, rcdev); > + > + spin_lock_irqsave(&data->lock, flags); > + > + tmp = __raw_readl(data->wdt_base + WDT_SWSYSRST); > + tmp |= BIT(id); > + tmp |= WDT_SWSYS_RST_KEY; > + writel(tmp, data->wdt_base + WDT_SWSYSRST); > + > + spin_unlock_irqrestore(&data->lock, flags); > + > + return 0; > +} > + > +static int toprgu_reset_deassert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + unsigned int tmp; > + unsigned long flags; > + struct mtk_wdt_dev *data = > + container_of(rcdev, struct mtk_wdt_dev, rcdev); > + > + spin_lock_irqsave(&data->lock, flags); > + > + tmp = __raw_readl(data->wdt_base + WDT_SWSYSRST); > + tmp &= ~BIT(id); > + tmp |= WDT_SWSYS_RST_KEY; > + writel(tmp, data->wdt_base + WDT_SWSYSRST); > + > + spin_unlock_irqrestore(&data->lock, flags); > + > + return 0; > +} > + > +static int toprgu_reset(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + int ret; > + > + ret = toprgu_reset_assert(rcdev, id); > + if (ret) > + return ret; > + > + return toprgu_reset_deassert(rcdev, id); > +} > + > +static const struct reset_control_ops toprgu_reset_ops = { > + .assert = toprgu_reset_assert, > + .deassert = toprgu_reset_deassert, > + .reset = toprgu_reset, > +}; > + > +static int toprgu_register_reset_controller(struct platform_device *pdev, > + int rst_num) > +{ > + int ret; > + struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev); > + > + spin_lock_init(&mtk_wdt->lock); > + > + mtk_wdt->rcdev.owner = THIS_MODULE; > + mtk_wdt->rcdev.nr_resets = rst_num; > + mtk_wdt->rcdev.ops = &toprgu_reset_ops; > + mtk_wdt->rcdev.of_node = pdev->dev.of_node; > + ret = reset_controller_register(&mtk_wdt->rcdev); > + if (ret != 0) > + dev_err(&pdev->dev, > + "couldn't register wdt reset controller: %d\n", ret); > + return ret; > +} > + > static int mtk_wdt_restart(struct watchdog_device *wdt_dev, > unsigned long action, void *data) > { > @@ -155,6 +254,7 @@ static int mtk_wdt_probe(struct platform_device *pdev) > { > struct device *dev = &pdev->dev; > struct mtk_wdt_dev *mtk_wdt; > + struct mtk_wdt_data *wdt_data; > int err; > > mtk_wdt = devm_kzalloc(dev, sizeof(*mtk_wdt), GFP_KERNEL); > @@ -190,6 +290,13 @@ static int mtk_wdt_probe(struct platform_device *pdev) > dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n", > mtk_wdt->wdt_dev.timeout, nowayout); > > + wdt_data = (struct mtk_wdt_data *)of_device_get_match_data(dev); > + if (wdt_data) { > + err = toprgu_register_reset_controller(pdev, > + wdt_data->sw_rst_num); > + if (err) > + return err; > + } > return 0; > } > > @@ -218,7 +325,9 @@ static int mtk_wdt_resume(struct device *dev) > #endif > > static const struct of_device_id mtk_wdt_dt_ids[] = { > + { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, > { .compatible = "mediatek,mt6589-wdt" }, > + { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, > { /* sentinel */ } > }; > MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids); _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v4 2/2] watchdog: mtk_wdt: mt8183: Add reset controller 2019-10-16 5:59 ` [PATCH v4 2/2] watchdog: mtk_wdt: mt8183: Add reset controller Jiaxin Yu 2019-11-14 7:34 ` Yingjoe Chen @ 2019-11-14 7:41 ` Yingjoe Chen 1 sibling, 0 replies; 6+ messages in thread From: Yingjoe Chen @ 2019-11-14 7:41 UTC (permalink / raw) To: Jiaxin Yu Cc: mark.rutland, alsa-devel, yong.liang, robh+dt, lgirdwood, tzungbi, broonie, linux-mediatek, linux-arm-kernel, eason.yen, perex, wim, linux On Wed, 2019-10-16 at 13:59 +0800, Jiaxin Yu wrote: > From: "yong.liang" <yong.liang@mediatek.com> > > Add reset controller API in watchdog driver. > Besides watchdog, MTK toprgu module also provide sub-system (eg, audio, > camera, codec and connectivity) software reset functionality. > > Signed-off-by: yong.liang <yong.liang@mediatek.com> Jiaxin, Since you send this patch, you should add your signed-off-by tag here as well. This looks good to me otherwise. Feel free to add my reviewed by if you want: Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Joe.C > --- > drivers/watchdog/Kconfig | 1 + > drivers/watchdog/mtk_wdt.c | 111 ++++++++++++++++++++++++++++++++++++- > 2 files changed, 111 insertions(+), 1 deletion(-) > > diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig > index 2e07caab9db2..629249fe5305 100644 > --- a/drivers/watchdog/Kconfig > +++ b/drivers/watchdog/Kconfig > @@ -717,6 +717,7 @@ config MEDIATEK_WATCHDOG > tristate "Mediatek SoCs watchdog support" > depends on ARCH_MEDIATEK || COMPILE_TEST > select WATCHDOG_CORE > + select RESET_CONTROLLER > help > Say Y here to include support for the watchdog timer > in Mediatek SoCs. > diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c > index 9c3d0033260d..d29484c7940a 100644 > --- a/drivers/watchdog/mtk_wdt.c > +++ b/drivers/watchdog/mtk_wdt.c > @@ -9,6 +9,9 @@ > * Based on sunxi_wdt.c > */ > > +#include <dt-bindings/reset-controller/mt2712-resets.h> > +#include <dt-bindings/reset-controller/mt8183-resets.h> > +#include <linux/delay.h> > #include <linux/err.h> > #include <linux/init.h> > #include <linux/io.h> > @@ -16,10 +19,12 @@ > #include <linux/module.h> > #include <linux/moduleparam.h> > #include <linux/of.h> > +#include <linux/of_device.h> > #include <linux/platform_device.h> > +#include <linux/reset-controller.h> > +#include <linux/slab.h> > #include <linux/types.h> > #include <linux/watchdog.h> > -#include <linux/delay.h> > > #define WDT_MAX_TIMEOUT 31 > #define WDT_MIN_TIMEOUT 1 > @@ -44,6 +49,9 @@ > #define WDT_SWRST 0x14 > #define WDT_SWRST_KEY 0x1209 > > +#define WDT_SWSYSRST 0x18U > +#define WDT_SWSYS_RST_KEY 0x88000000 > + > #define DRV_NAME "mtk-wdt" > #define DRV_VERSION "1.0" > > @@ -53,8 +61,99 @@ static unsigned int timeout; > struct mtk_wdt_dev { > struct watchdog_device wdt_dev; > void __iomem *wdt_base; > + spinlock_t lock; /* protects WDT_SWSYSRST reg */ > + struct reset_controller_dev rcdev; > +}; > + > +struct mtk_wdt_data { > + int sw_rst_num; > }; > > +static const struct mtk_wdt_data mt2712_data = { > + .sw_rst_num = MT2712_TOPRGU_SW_RST_NUM, > +}; > + > +static const struct mtk_wdt_data mt8183_data = { > + .sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, > +}; > + > +static int toprgu_reset_assert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + unsigned int tmp; > + unsigned long flags; > + struct mtk_wdt_dev *data = > + container_of(rcdev, struct mtk_wdt_dev, rcdev); > + > + spin_lock_irqsave(&data->lock, flags); > + > + tmp = __raw_readl(data->wdt_base + WDT_SWSYSRST); > + tmp |= BIT(id); > + tmp |= WDT_SWSYS_RST_KEY; > + writel(tmp, data->wdt_base + WDT_SWSYSRST); > + > + spin_unlock_irqrestore(&data->lock, flags); > + > + return 0; > +} > + > +static int toprgu_reset_deassert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + unsigned int tmp; > + unsigned long flags; > + struct mtk_wdt_dev *data = > + container_of(rcdev, struct mtk_wdt_dev, rcdev); > + > + spin_lock_irqsave(&data->lock, flags); > + > + tmp = __raw_readl(data->wdt_base + WDT_SWSYSRST); > + tmp &= ~BIT(id); > + tmp |= WDT_SWSYS_RST_KEY; > + writel(tmp, data->wdt_base + WDT_SWSYSRST); > + > + spin_unlock_irqrestore(&data->lock, flags); > + > + return 0; > +} > + > +static int toprgu_reset(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + int ret; > + > + ret = toprgu_reset_assert(rcdev, id); > + if (ret) > + return ret; > + > + return toprgu_reset_deassert(rcdev, id); > +} > + > +static const struct reset_control_ops toprgu_reset_ops = { > + .assert = toprgu_reset_assert, > + .deassert = toprgu_reset_deassert, > + .reset = toprgu_reset, > +}; > + > +static int toprgu_register_reset_controller(struct platform_device *pdev, > + int rst_num) > +{ > + int ret; > + struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev); > + > + spin_lock_init(&mtk_wdt->lock); > + > + mtk_wdt->rcdev.owner = THIS_MODULE; > + mtk_wdt->rcdev.nr_resets = rst_num; > + mtk_wdt->rcdev.ops = &toprgu_reset_ops; > + mtk_wdt->rcdev.of_node = pdev->dev.of_node; > + ret = reset_controller_register(&mtk_wdt->rcdev); > + if (ret != 0) > + dev_err(&pdev->dev, > + "couldn't register wdt reset controller: %d\n", ret); > + return ret; > +} > + > static int mtk_wdt_restart(struct watchdog_device *wdt_dev, > unsigned long action, void *data) > { > @@ -155,6 +254,7 @@ static int mtk_wdt_probe(struct platform_device *pdev) > { > struct device *dev = &pdev->dev; > struct mtk_wdt_dev *mtk_wdt; > + struct mtk_wdt_data *wdt_data; > int err; > > mtk_wdt = devm_kzalloc(dev, sizeof(*mtk_wdt), GFP_KERNEL); > @@ -190,6 +290,13 @@ static int mtk_wdt_probe(struct platform_device *pdev) > dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n", > mtk_wdt->wdt_dev.timeout, nowayout); > > + wdt_data = (struct mtk_wdt_data *)of_device_get_match_data(dev); > + if (wdt_data) { > + err = toprgu_register_reset_controller(pdev, > + wdt_data->sw_rst_num); > + if (err) > + return err; > + } > return 0; > } > > @@ -218,7 +325,9 @@ static int mtk_wdt_resume(struct device *dev) > #endif > > static const struct of_device_id mtk_wdt_dt_ids[] = { > + { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, > { .compatible = "mediatek,mt6589-wdt" }, > + { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, > { /* sentinel */ } > }; > MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids); _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-01-02 9:06 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2019-10-16 5:59 [PATCH v4 0/2] ASoC: mt8183: fix audio playback slowly after playback Jiaxin Yu 2019-10-16 5:59 ` [PATCH v4 1/2] dt-bindings: mediatek: mt8183: Add #reset-cells Jiaxin Yu 2019-11-13 9:46 ` Jiaxin Yu 2019-10-16 5:59 ` [PATCH v4 2/2] watchdog: mtk_wdt: mt8183: Add reset controller Jiaxin Yu 2019-11-14 7:34 ` Yingjoe Chen 2019-11-14 7:41 ` Yingjoe Chen
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