From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Nicolas Boichat <drinkcat@chromium.org>
Cc: Rob Herring <robh@kernel.org>,
srv_heupstream <srv_heupstream@mediatek.com>,
James Liao <jamesjj.liao@mediatek.com>,
lkml <linux-kernel@vger.kernel.org>,
Fan Chen <fan.chen@mediatek.com>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@lists.infradead.org>,
Sascha Hauer <kernel@pengutronix.de>,
Matthias Brugger <matthias.bgg@gmail.com>,
linux-arm Mailing List <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v10 07/12] soc: mediatek: Remove infracfg misc driver support
Date: Fri, 20 Dec 2019 11:31:13 +0800 [thread overview]
Message-ID: <1576812673.8410.10.camel@mtksdaap41> (raw)
In-Reply-To: <CANMq1KDSVH0kb0YVf5iiVTs=Bpc742gJWjqk3t0KU5LMzVNJSg@mail.gmail.com>
On Thu, 2019-12-19 at 11:56 +0800, Nicolas Boichat wrote:
> On Wed, Dec 18, 2019 at 4:31 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
> >
> > In previous patches, we introduce scpsys-ext driver that covers
> > the functions which infracfg misc driver provided.
> > And then replace bus_prot_mask with bp_table of all compatibles.
> > Now, we're going to remove infracfg misc drvier which is no longer
> > being used.
> >
> > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> > ---
> > drivers/soc/mediatek/Kconfig | 10 -----
> > drivers/soc/mediatek/Makefile | 3 +-
> > drivers/soc/mediatek/mtk-infracfg.c | 79 -----------------------------------
> > include/linux/soc/mediatek/infracfg.h | 39 -----------------
> > 4 files changed, 1 insertion(+), 130 deletions(-)
> > delete mode 100644 drivers/soc/mediatek/mtk-infracfg.c
> > delete mode 100644 include/linux/soc/mediatek/infracfg.h
> >
> > diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
> > index 2114b56..f837b3c 100644
> > --- a/drivers/soc/mediatek/Kconfig
> > +++ b/drivers/soc/mediatek/Kconfig
> > @@ -10,21 +10,12 @@ config MTK_CMDQ
> > depends on ARCH_MEDIATEK || COMPILE_TEST
> > select MAILBOX
> > select MTK_CMDQ_MBOX
> > - select MTK_INFRACFG
> > help
> > Say yes here to add support for the MediaTek Command Queue (CMDQ)
> > driver. The CMDQ is used to help read/write registers with critical
> > time limitation, such as updating display configuration during the
> > vblank.
> >
> > -config MTK_INFRACFG
> > - bool "MediaTek INFRACFG Support"
> > - select REGMAP
> > - help
> > - Say yes here to add support for the MediaTek INFRACFG controller. The
> > - INFRACFG controller contains various infrastructure registers not
> > - directly associated to any device.
> > -
> > config MTK_PMIC_WRAP
> > tristate "MediaTek PMIC Wrapper Support"
> > depends on RESET_CONTROLLER
> > @@ -38,7 +29,6 @@ config MTK_SCPSYS
> > bool "MediaTek SCPSYS Support"
> > default ARCH_MEDIATEK
> > select REGMAP
> > - select MTK_INFRACFG
> > select PM_GENERIC_DOMAINS if PM
> > help
> > Say yes here to add support for the MediaTek SCPSYS power domain
> > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> > index b442be9..7bf7e88 100644
> > --- a/drivers/soc/mediatek/Makefile
> > +++ b/drivers/soc/mediatek/Makefile
> > @@ -1,5 +1,4 @@
> > # SPDX-License-Identifier: GPL-2.0-only
> > obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
> > -obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o mtk-scpsys-ext.o
> > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
> > -obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> > +obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o mtk-scpsys-ext.o
> > diff --git a/drivers/soc/mediatek/mtk-infracfg.c b/drivers/soc/mediatek/mtk-infracfg.c
> > deleted file mode 100644
> > index 341c7ac..0000000
> > --- a/drivers/soc/mediatek/mtk-infracfg.c
> > +++ /dev/null
> > @@ -1,79 +0,0 @@
> > -// SPDX-License-Identifier: GPL-2.0-only
> > -/*
> > - * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
> > - */
> > -
> > -#include <linux/export.h>
> > -#include <linux/jiffies.h>
> > -#include <linux/regmap.h>
> > -#include <linux/soc/mediatek/infracfg.h>
> > -#include <asm/processor.h>
> > -
> > -#define MTK_POLL_DELAY_US 10
> > -#define MTK_POLL_TIMEOUT (jiffies_to_usecs(HZ))
> > -
> > -#define INFRA_TOPAXI_PROTECTEN 0x0220
> > -#define INFRA_TOPAXI_PROTECTSTA1 0x0228
> > -#define INFRA_TOPAXI_PROTECTEN_SET 0x0260
> > -#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264
> > -
> > -/**
> > - * mtk_infracfg_set_bus_protection - enable bus protection
> > - * @regmap: The infracfg regmap
> > - * @mask: The mask containing the protection bits to be enabled.
> > - * @reg_update: The boolean flag determines to set the protection bits
> > - * by regmap_update_bits with enable register(PROTECTEN) or
> > - * by regmap_write with set register(PROTECTEN_SET).
> > - *
> > - * This function enables the bus protection bits for disabled power
> > - * domains so that the system does not hang when some unit accesses the
> > - * bus while in power down.
> > - */
> > -int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
> > - bool reg_update)
> > -{
> > - u32 val;
> > - int ret;
> > -
> > - if (reg_update)
> > - regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask,
> > - mask);
> > - else
> > - regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask);
> > -
> > - ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1,
> > - val, (val & mask) == mask,
> > - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
> > -
> > - return ret;
> > -}
> > -
> > -/**
> > - * mtk_infracfg_clear_bus_protection - disable bus protection
> > - * @regmap: The infracfg regmap
> > - * @mask: The mask containing the protection bits to be disabled.
> > - * @reg_update: The boolean flag determines to clear the protection bits
> > - * by regmap_update_bits with enable register(PROTECTEN) or
> > - * by regmap_write with clear register(PROTECTEN_CLR).
> > - *
> > - * This function disables the bus protection bits previously enabled with
> > - * mtk_infracfg_set_bus_protection.
> > - */
> > -
> > -int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
> > - bool reg_update)
> > -{
> > - int ret;
> > - u32 val;
> > -
> > - if (reg_update)
> > - regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0);
> > - else
> > - regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask);
> > -
> > - ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1,
> > - val, !(val & mask),
> > - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
> > -
> > - return ret;
> > -}
> > diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h
> > deleted file mode 100644
> > index fd25f01..0000000
> > --- a/include/linux/soc/mediatek/infracfg.h
> > +++ /dev/null
> > @@ -1,39 +0,0 @@
> > -/* SPDX-License-Identifier: GPL-2.0 */
> > -#ifndef __SOC_MEDIATEK_INFRACFG_H
> > -#define __SOC_MEDIATEK_INFRACFG_H
> > -
> > -#define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0)
> > -#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1)
> > -#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2)
> > -#define MT8173_TOP_AXI_PROT_EN_MMAPB_S BIT(6)
> > -#define MT8173_TOP_AXI_PROT_EN_L2C_M2 BIT(9)
> > -#define MT8173_TOP_AXI_PROT_EN_L2SS_SMI BIT(11)
> > -#define MT8173_TOP_AXI_PROT_EN_L2SS_ADD BIT(12)
> > -#define MT8173_TOP_AXI_PROT_EN_CCI_M2 BIT(13)
> > -#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14)
> > -#define MT8173_TOP_AXI_PROT_EN_PERI_M0 BIT(15)
> > -#define MT8173_TOP_AXI_PROT_EN_PERI_M1 BIT(16)
> > -#define MT8173_TOP_AXI_PROT_EN_DEBUGSYS BIT(17)
> > -#define MT8173_TOP_AXI_PROT_EN_CQ_DMA BIT(18)
> > -#define MT8173_TOP_AXI_PROT_EN_GCPU BIT(19)
> > -#define MT8173_TOP_AXI_PROT_EN_IOMMU BIT(20)
> > -#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21)
> > -#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22)
> > -#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23)
> > -
> > -#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1)
> > -#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2)
> > -#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8)
> > -
> > -#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17))
> > -#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25))
> > -#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \
> > - BIT(28))
> > -#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \
> > - BIT(7) | BIT(8))
>
> It was really nice to have these all defined, can we move those to
> scpsys-ext.h? (and do the same for MT8183?)
>
Sure. And I'll do the same for MT8183 in next version.
> > -int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
> > - bool reg_update);
> > -int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
> > - bool reg_update);
> > -#endif /* __SOC_MEDIATEK_INFRACFG_H */
> > --
> > 1.8.1.1.dirty
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-12-20 3:36 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-18 8:30 [PATCH v10 00/12] Mediatek MT8183 scpsys support Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 01/12] dt-bindings: mediatek: Add property to mt8183 smi-common Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 02/12] dt-bindings: soc: Add MT8183 power dt-bindings Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 03/12] soc: mediatek: Add basic_clk_name to scp_power_data Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 04/12] soc: mediatek: Use basic_clk_name for all compatibles Weiyi Lu
2019-12-19 3:48 ` Nicolas Boichat
2019-12-20 3:29 ` Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 05/12] soc: mediatek: Add multiple step bus protection control Weiyi Lu
2019-12-19 3:51 ` Nicolas Boichat
2019-12-20 3:30 ` Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 06/12] soc: mediatek: Use bp_table for all compatibles Weiyi Lu
2019-12-19 3:54 ` Nicolas Boichat
2019-12-20 3:30 ` Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 07/12] soc: mediatek: Remove infracfg misc driver support Weiyi Lu
2019-12-19 3:56 ` Nicolas Boichat
2019-12-20 3:31 ` Weiyi Lu [this message]
2019-12-18 8:30 ` [PATCH v10 08/12] soc: mediatek: Add subsys clock control for bus protection Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 09/12] soc: mediatek: Add extra sram control Weiyi Lu
2019-12-19 3:57 ` Nicolas Boichat
2019-12-18 8:30 ` [PATCH v10 10/12] soc: mediatek: Add MT8183 scpsys support Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 11/12] arm64: dts: Add power controller device node of MT8183 Weiyi Lu
2019-12-18 8:30 ` [PATCH v10 12/12] arm64: dts: Add power-domains properity to mfgcfg Weiyi Lu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1576812673.8410.10.camel@mtksdaap41 \
--to=weiyi.lu@mediatek.com \
--cc=drinkcat@chromium.org \
--cc=fan.chen@mediatek.com \
--cc=jamesjj.liao@mediatek.com \
--cc=kernel@pengutronix.de \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=matthias.bgg@gmail.com \
--cc=robh@kernel.org \
--cc=srv_heupstream@mediatek.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).