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Mon, 23 Dec 2019 13:02:40 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 6CE98C44BE6; Mon, 23 Dec 2019 13:02:40 +0000 (UTC) Received: from sramana-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sramana) by smtp.codeaurora.org (Postfix) with ESMTPSA id 548BDC3D68C; Mon, 23 Dec 2019 13:02:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 548BDC3D68C Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=sramana@codeaurora.org From: Srinivas Ramana To: will@kernel.org, catalin.marinas@arm.com, maz@kernel.org, will.deacon@arm.com Subject: [PATCH] arm64: Set SSBS for user threads while creation Date: Mon, 23 Dec 2019 18:32:26 +0530 Message-Id: <1577106146-8999-1-git-send-email-sramana@codeaurora.org> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191223_050246_433887_25DB698D X-CRM114-Status: GOOD ( 12.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-msm@vger.kernel.org, Srinivas Ramana , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Current SSBS implementation takes care of setting the SSBS bit in start_thread() for user threads. While this works for tasks launched with fork/clone followed by execve, for cases where userspace would just call fork (eg, Java applications) this leaves the SSBS bit unset. This results in performance regression for such tasks. It is understood that commit cbdf8a189a66 ("arm64: Force SSBS on context switch") masks this issue, but that was done for a different reason where heterogeneous CPUs(both SSBS supported and unsupported) are present. It is appropriate to take care of the SSBS bit for all threads while creation itself. Fixes: 8f04e8e6e29c ("arm64: ssbd: Add support for PSTATE.SSBS rather than trapping to EL3") Signed-off-by: Srinivas Ramana --- arch/arm64/kernel/process.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 71f788cd2b18..a8f05cc39261 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -399,6 +399,13 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start, */ if (clone_flags & CLONE_SETTLS) p->thread.uw.tp_value = childregs->regs[3]; + + if (arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE) { + if (is_compat_thread(task_thread_info(p))) + set_compat_ssbs_bit(childregs); + else + set_ssbs_bit(childregs); + } } else { memset(childregs, 0, sizeof(struct pt_regs)); childregs->pstate = PSR_MODE_EL1h; -- Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel