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Wed, 26 Feb 2020 23:47:41 -0800 Received: from mtkmbs05n2.mediatek.inc (172.21.101.140) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 26 Feb 2020 23:48:20 -0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 27 Feb 2020 15:46:40 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 27 Feb 2020 15:47:42 +0800 From: Sam Shih To: Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Matthias Brugger Subject: [PATCH 1/1] pwm: mediatek: add longer period support Date: Thu, 27 Feb 2020 15:46:50 +0800 Message-ID: <1582789610-23133-2-git-send-email-sam.shih@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1582789610-23133-1-git-send-email-sam.shih@mediatek.com> References: <1582789610-23133-1-git-send-email-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200226_234749_588042_E70A6F6E X-CRM114-Status: GOOD ( 11.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-pwm@vger.kernel.org, Sam Shih , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, John Crispin , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org The pwm clock source could be divided by 1625 with PWM_CON BIT(3) setting in mediatek hardware. This patch add support for longer pwm period configuration, which allowing blinking LEDs via pwm interface. Signed-off-by: Sam Shih --- drivers/pwm/pwm-mediatek.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index b94e0d09c300..9af309bea01a 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c @@ -121,8 +121,8 @@ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, int duty_ns, int period_ns) { struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); - u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH, - reg_thres = PWMTHRES; + u32 clkdiv = 0, clksel = 0, cnt_period, cnt_duty, + reg_width = PWMDWIDTH, reg_thres = PWMTHRES; u64 resolution; int ret; @@ -141,9 +141,18 @@ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, clkdiv++; cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution); + if (clkdiv > PWM_CLK_DIV_MAX && !clksel) { + clksel = 1; + clkdiv = 0; + resolution = (u64)NSEC_PER_SEC * 1000 * 1625; + do_div(resolution, + clk_get_rate(pc->clk_pwms[pwm->hwpwm])); + cnt_period = DIV_ROUND_CLOSEST_ULL( + (u64)period_ns * 1000, resolution); + } } - if (clkdiv > PWM_CLK_DIV_MAX) { + if (clkdiv > PWM_CLK_DIV_MAX && clksel) { pwm_mediatek_clk_disable(chip, pwm); dev_err(chip->dev, "period %d not supported\n", period_ns); return -EINVAL; @@ -159,7 +168,11 @@ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, } cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution); - pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); + if (clksel) + pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | + clkdiv); + else + pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period); pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty); -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel