From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 230C3C2BBC7 for ; Tue, 14 Apr 2020 09:48:55 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E75E62064A for ; Tue, 14 Apr 2020 09:48:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="AzXEix6s" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E75E62064A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=5V9QyYP5UDdEHE5PF4Bj0+6f6zCLO2AnfGlIRYERkSM=; b=AzX Eix6snRoavoy992aZ3S2uVU7MRq1vmqp5R+k69Mr/BsBvY7fJLzaNPLg9QoFKT3x58Zfpkc86k18A 1Xrde6Wjhd7Cl3VL/LV1bUQE0gX/KKp+aOxRHSNBrhS0XrqJfuy6Dz36iNSHdkWXq2ce1W9iFH07V 3bZV1lcdbSzzGXW5RAlqgj0rnBJhH/+/DLKnYR1t0ZGg2dm0x2rkJTfTs/zCPclD72UGW/n6xgSwM XWwwENxLNk/1Jn2u+Bl1pCK3OccNW+g1mN8NO4WdO3YoyaOzzr09OO9Jsuj8JnaeUMLjXeoY1Llh8 V0c9aW3OLOqB4yaTdLxLdM9yCfjBAfA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jOIBa-0000cW-Eu; Tue, 14 Apr 2020 09:48:54 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jOIBW-0000bo-Hr for linux-arm-kernel@lists.infradead.org; Tue, 14 Apr 2020 09:48:52 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D8A331FB; Tue, 14 Apr 2020 02:48:47 -0700 (PDT) Received: from p8cg001049571a15.arm.com (unknown [10.163.1.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 26F5A3F6C4; Tue, 14 Apr 2020 02:48:43 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Subject: [PATCH V2 00/16] arm64/cpufeature: Introduce ID_PFR2, ID_DFR1, ID_MMFR5 and other changes Date: Tue, 14 Apr 2020 15:18:14 +0530 Message-Id: <1586857710-17154-1-git-send-email-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.7.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200414_024850_676466_9F297D96 X-CRM114-Status: GOOD ( 10.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, suzuki.poulose@arm.com, catalin.marinas@arm.com, Anshuman Khandual , linux-kernel@vger.kernel.org, James Morse , maz@kernel.org, will@kernel.org, kvmarm@lists.cs.columbia.edu MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series is primarily motivated from an adhoc list from Mark Rutland during our previous ID_ISAR6 discussion [1]. The current proposal also accommodates some more suggestions from Will and Suzuki. This series adds missing 32 bit system registers (ID_PFR2, ID_DFR1 and ID_MMFR5), adds missing features bits on all existing system registers (32 and 64 bit) and some other miscellaneous changes. While here it also includes a patch which does macro replacement for various open bits shift encodings for various CPU ID registers. There is a slight re-order of the patches here as compared to the previous version (V1). This series is based on v5.7-rc1. All feature bits enabled here can be referred in ARM DDI 0487F.a specification. Though I have tried to select appropriate values for each new feature being added here, there might be some inconsistencies (or mistakes). In which case, please do let me know if anything needs to change. Thank you. [1] https://patchwork.kernel.org/patch/11287805/ Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Rutland Cc: Marc Zyngier Cc: James Morse Cc: Suzuki K Poulose Cc: kvmarm@lists.cs.columbia.edu Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Changes in V2: - Added Suggested-by tag from Mark Rutland for all changes he had proposed - Added comment for SpecSEI feature on why it is HIGHER_SAFE per Suzuki - Added a patch which makes ID_AA64DFR0_DOUBLELOCK a signed feature per Suzuki - Added ID_DFR1 and ID_MMFR5 system register definitions per Will - Added remaining features bits for relevant 64 bit system registers per Will - Changed commit message on [PATCH 5/7] regarding TraceFilt feature per Suzuki - Changed ID_PFR2.CSV3 (FTR_STRICT -> FTR_NONSTRICT) as 64 bit registers per Will - Changed ID_PFR0.CSV2 (FTR_STRICT -> FTR_NONSTRICT) as 64 bit registers per Will - Changed some commit messages Changes in V1: (https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=234093) Anshuman Khandual (16): arm64/cpufeature: Add explicit ftr_id_isar0[] for ID_ISAR0 register arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register arm64/cpufeature: Make doublelock a signed feature in ID_AA64DFR0 arm64/cpufeature: Introduce ID_PFR2 CPU register arm64/cpufeature: Introduce ID_DFR1 CPU register arm64/cpufeature: Introduce ID_MMFR5 CPU register arm64/cpufeature: Add remaining feature bits in ID_PFR0 register arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register arm64/cpufeature: Add remaining feature bits in ID_AA64ISAR0 register arm64/cpufeature: Add remaining feature bits in ID_AA64PFR0 register arm64/cpufeature: Add remaining feature bits in ID_AA64PFR1 register arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR0 register arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR1 register arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR2 register arm64/cpufeature: Add remaining feature bits in ID_AA64DFR0 register arm64/cpufeature: Replace all open bits shift encodings with macros arch/arm64/include/asm/cpu.h | 3 + arch/arm64/include/asm/sysreg.h | 90 ++++++++++++++++++++ arch/arm64/kernel/cpufeature.c | 141 +++++++++++++++++++++++++------- arch/arm64/kernel/cpuinfo.c | 3 + arch/arm64/kvm/sys_regs.c | 6 +- 5 files changed, 211 insertions(+), 32 deletions(-) -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel