* [PATCH] arm64: perf: Expose some new events via sysfs
@ 2020-04-21 6:31 Shaokun Zhang
2020-05-01 17:12 ` Will Deacon
0 siblings, 1 reply; 6+ messages in thread
From: Shaokun Zhang @ 2020-04-21 6:31 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Shaokun Zhang, Mark Rutland, Will Deacon
Some new PMU events can been detected by PMCEID1_EL0, but it can't
be listed, Let's expose these through sysfs.
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
---
arch/arm64/include/asm/perf_event.h | 19 +++++++++++++++++++
arch/arm64/kernel/perf_event.c | 19 +++++++++++++++++++
2 files changed, 38 insertions(+)
diff --git a/arch/arm64/include/asm/perf_event.h b/arch/arm64/include/asm/perf_event.h
index e7765b62c712..f1b93d7c4260 100644
--- a/arch/arm64/include/asm/perf_event.h
+++ b/arch/arm64/include/asm/perf_event.h
@@ -72,12 +72,31 @@
#define ARMV8_PMUV3_PERFCTR_LL_CACHE_RD 0x36
#define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD 0x37
#define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD 0x38
+#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD 0x39
+#define ARMV8_PMUV3_PERFCTR_OP_RETIRED 0x3A
+#define ARMV8_PMUV3_PERFCTR_OP_SPEC 0x3B
+#define ARMV8_PMUV3_PERFCTR_STALL 0x3C
+#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND 0x3D
+#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND 0x3E
+#define ARMV8_PMUV3_PERFCTR_STALL_SLOT 0x3F
/* Statistical profiling extension microarchitectural events */
#define ARMV8_SPE_PERFCTR_SAMPLE_POP 0x4000
#define ARMV8_SPE_PERFCTR_SAMPLE_FEED 0x4001
#define ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE 0x4002
#define ARMV8_SPE_PERFCTR_SAMPLE_COLLISION 0x4003
+#define ARMV8_SPE_PERFCTR_CNT_CYCLES 0x4004
+#define ARMV8_SPE_PERFCTR_STALL_BACKEND_MEM 0x4005
+#define ARMV8_SPE_PERFCTR_L1I_CACHE_LMISS 0x4006
+#define ARMV8_SPE_PERFCTR_L2D_CACHE_LMISS_RD 0x4009
+#define ARMV8_SPE_PERFCTR_L2I_CACHE_LMISS 0x400A
+#define ARMV8_SPE_PERFCTR_L3D_CACHE_LMISS_RD 0x400B
+#define ARMV8_SPE_PERFCTR_LDST_ALIGN_LAT 0x4020
+#define ARMV8_SPE_PERFCTR_LD_ALIGN_LAT 0x4021
+#define ARMV8_SPE_PERFCTR_ST_ALIGN_LAT 0x4022
+#define ARMV8_SPE_PERFCTR_MEM_ACCESS_CHECKED 0x4024
+#define ARMV8_SPE_PERFCTR_MEM_ACCESS_CHECKED_RD 0x4025
+#define ARMV8_SPE_PERFCTR_MEM_ACCESS_CHECKED_WR 0x4026
/* ARMv8 recommended implementation defined event types */
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD 0x40
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 4d7879484cec..24f854cf4919 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -222,10 +222,29 @@ static struct attribute *armv8_pmuv3_event_attrs[] = {
ARMV8_EVENT_ATTR(ll_cache_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_RD),
ARMV8_EVENT_ATTR(ll_cache_miss_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD),
ARMV8_EVENT_ATTR(remote_access_rd, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD),
+ ARMV8_EVENT_ATTR(l1d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD),
+ ARMV8_EVENT_ATTR(op_retired, ARMV8_PMUV3_PERFCTR_OP_RETIRED),
+ ARMV8_EVENT_ATTR(op_SPEC, ARMV8_PMUV3_PERFCTR_OP_SPEC),
+ ARMV8_EVENT_ATTR(stall, ARMV8_PMUV3_PERFCTR_STALL),
+ ARMV8_EVENT_ATTR(stall_slot_backend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND),
+ ARMV8_EVENT_ATTR(stall_slot_frontend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND),
+ ARMV8_EVENT_ATTR(stall_slot, ARMV8_PMUV3_PERFCTR_STALL_SLOT),
ARMV8_EVENT_ATTR(sample_pop, ARMV8_SPE_PERFCTR_SAMPLE_POP),
ARMV8_EVENT_ATTR(sample_feed, ARMV8_SPE_PERFCTR_SAMPLE_FEED),
ARMV8_EVENT_ATTR(sample_filtrate, ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE),
ARMV8_EVENT_ATTR(sample_collision, ARMV8_SPE_PERFCTR_SAMPLE_COLLISION),
+ ARMV8_EVENT_ATTR(cnt_cycles, ARMV8_SPE_PERFCTR_CNT_CYCLES),
+ ARMV8_EVENT_ATTR(stall_backend_mem, ARMV8_SPE_PERFCTR_STALL_BACKEND_MEM),
+ ARMV8_EVENT_ATTR(l1i_cache_lmiss, ARMV8_SPE_PERFCTR_L1I_CACHE_LMISS),
+ ARMV8_EVENT_ATTR(l2d_cache_lmiss_rd, ARMV8_SPE_PERFCTR_L2D_CACHE_LMISS_RD),
+ ARMV8_EVENT_ATTR(l2i_cache_lmiss, ARMV8_SPE_PERFCTR_L2I_CACHE_LMISS),
+ ARMV8_EVENT_ATTR(l3d_cache_lmiss_rd, ARMV8_SPE_PERFCTR_L3D_CACHE_LMISS_RD),
+ ARMV8_EVENT_ATTR(ldst_align_lat, ARMV8_SPE_PERFCTR_LDST_ALIGN_LAT),
+ ARMV8_EVENT_ATTR(ld_align_lat, ARMV8_SPE_PERFCTR_LD_ALIGN_LAT),
+ ARMV8_EVENT_ATTR(st_align_lat, ARMV8_SPE_PERFCTR_ST_ALIGN_LAT),
+ ARMV8_EVENT_ATTR(mem_access_checked, ARMV8_SPE_PERFCTR_MEM_ACCESS_CHECKED),
+ ARMV8_EVENT_ATTR(mem_access_checked_rd, ARMV8_SPE_PERFCTR_MEM_ACCESS_CHECKED_RD),
+ ARMV8_EVENT_ATTR(mem_access_checked_wr, ARMV8_SPE_PERFCTR_MEM_ACCESS_CHECKED_WR),
NULL,
};
--
2.7.4
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^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH] arm64: perf: Expose some new events via sysfs
2020-04-21 6:31 [PATCH] arm64: perf: Expose some new events via sysfs Shaokun Zhang
@ 2020-05-01 17:12 ` Will Deacon
2020-05-04 1:31 ` Shaokun Zhang
2020-05-04 3:46 ` Shaokun Zhang
0 siblings, 2 replies; 6+ messages in thread
From: Will Deacon @ 2020-05-01 17:12 UTC (permalink / raw)
To: Shaokun Zhang; +Cc: Mark Rutland, linux-arm-kernel
On Tue, Apr 21, 2020 at 02:31:53PM +0800, Shaokun Zhang wrote:
> Some new PMU events can been detected by PMCEID1_EL0, but it can't
> be listed, Let's expose these through sysfs.
>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
> ---
> arch/arm64/include/asm/perf_event.h | 19 +++++++++++++++++++
> arch/arm64/kernel/perf_event.c | 19 +++++++++++++++++++
> 2 files changed, 38 insertions(+)
>
> diff --git a/arch/arm64/include/asm/perf_event.h b/arch/arm64/include/asm/perf_event.h
> index e7765b62c712..f1b93d7c4260 100644
> --- a/arch/arm64/include/asm/perf_event.h
> +++ b/arch/arm64/include/asm/perf_event.h
> @@ -72,12 +72,31 @@
> #define ARMV8_PMUV3_PERFCTR_LL_CACHE_RD 0x36
> #define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD 0x37
> #define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD 0x38
> +#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD 0x39
> +#define ARMV8_PMUV3_PERFCTR_OP_RETIRED 0x3A
> +#define ARMV8_PMUV3_PERFCTR_OP_SPEC 0x3B
> +#define ARMV8_PMUV3_PERFCTR_STALL 0x3C
> +#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND 0x3D
> +#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND 0x3E
> +#define ARMV8_PMUV3_PERFCTR_STALL_SLOT 0x3F
Hmm, looks like the presence of this event implies the presence of the
PMMIR_EL1 register. Should we be exposing the "SLOTS" field from that in
sysfs? (obviously as a separate patch)
>
> /* Statistical profiling extension microarchitectural events */
> #define ARMV8_SPE_PERFCTR_SAMPLE_POP 0x4000
> #define ARMV8_SPE_PERFCTR_SAMPLE_FEED 0x4001
> #define ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE 0x4002
> #define ARMV8_SPE_PERFCTR_SAMPLE_COLLISION 0x4003
> +#define ARMV8_SPE_PERFCTR_CNT_CYCLES 0x4004
> +#define ARMV8_SPE_PERFCTR_STALL_BACKEND_MEM 0x4005
> +#define ARMV8_SPE_PERFCTR_L1I_CACHE_LMISS 0x4006
> +#define ARMV8_SPE_PERFCTR_L2D_CACHE_LMISS_RD 0x4009
> +#define ARMV8_SPE_PERFCTR_L2I_CACHE_LMISS 0x400A
> +#define ARMV8_SPE_PERFCTR_L3D_CACHE_LMISS_RD 0x400B
> +#define ARMV8_SPE_PERFCTR_LDST_ALIGN_LAT 0x4020
> +#define ARMV8_SPE_PERFCTR_LD_ALIGN_LAT 0x4021
> +#define ARMV8_SPE_PERFCTR_ST_ALIGN_LAT 0x4022
> +#define ARMV8_SPE_PERFCTR_MEM_ACCESS_CHECKED 0x4024
> +#define ARMV8_SPE_PERFCTR_MEM_ACCESS_CHECKED_RD 0x4025
> +#define ARMV8_SPE_PERFCTR_MEM_ACCESS_CHECKED_WR 0x4026
I think the naming is off here, as these don't seem to have anything to do
with SPE afaict.
Will
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] arm64: perf: Expose some new events via sysfs
2020-05-01 17:12 ` Will Deacon
@ 2020-05-04 1:31 ` Shaokun Zhang
2020-05-04 3:46 ` Shaokun Zhang
1 sibling, 0 replies; 6+ messages in thread
From: Shaokun Zhang @ 2020-05-04 1:31 UTC (permalink / raw)
To: Will Deacon; +Cc: Mark Rutland, linux-arm-kernel
Hi Will,
On 2020/5/2 1:12, Will Deacon wrote:
> On Tue, Apr 21, 2020 at 02:31:53PM +0800, Shaokun Zhang wrote:
>> Some new PMU events can been detected by PMCEID1_EL0, but it can't
>> be listed, Let's expose these through sysfs.
>>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
>> ---
>> arch/arm64/include/asm/perf_event.h | 19 +++++++++++++++++++
>> arch/arm64/kernel/perf_event.c | 19 +++++++++++++++++++
>> 2 files changed, 38 insertions(+)
>>
>> diff --git a/arch/arm64/include/asm/perf_event.h b/arch/arm64/include/asm/perf_event.h
>> index e7765b62c712..f1b93d7c4260 100644
>> --- a/arch/arm64/include/asm/perf_event.h
>> +++ b/arch/arm64/include/asm/perf_event.h
>> @@ -72,12 +72,31 @@
>> #define ARMV8_PMUV3_PERFCTR_LL_CACHE_RD 0x36
>> #define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD 0x37
>> #define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD 0x38
>> +#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD 0x39
>> +#define ARMV8_PMUV3_PERFCTR_OP_RETIRED 0x3A
>> +#define ARMV8_PMUV3_PERFCTR_OP_SPEC 0x3B
>> +#define ARMV8_PMUV3_PERFCTR_STALL 0x3C
>> +#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND 0x3D
>> +#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND 0x3E
>> +#define ARMV8_PMUV3_PERFCTR_STALL_SLOT 0x3F
>
> Hmm, looks like the presence of this event implies the presence of the
> PMMIR_EL1 register. Should we be exposing the "SLOTS" field from that in
> sysfs? (obviously as a separate patch)
>
Yes, Before doing this patch, I have considered the PMMIR_EL1 register, but
not sure what to do about it :-) . I will expose it in next version.
>>
>> /* Statistical profiling extension microarchitectural events */
>> #define ARMV8_SPE_PERFCTR_SAMPLE_POP 0x4000
>> #define ARMV8_SPE_PERFCTR_SAMPLE_FEED 0x4001
>> #define ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE 0x4002
>> #define ARMV8_SPE_PERFCTR_SAMPLE_COLLISION 0x4003
>> +#define ARMV8_SPE_PERFCTR_CNT_CYCLES 0x4004
>> +#define ARMV8_SPE_PERFCTR_STALL_BACKEND_MEM 0x4005
>> +#define ARMV8_SPE_PERFCTR_L1I_CACHE_LMISS 0x4006
>> +#define ARMV8_SPE_PERFCTR_L2D_CACHE_LMISS_RD 0x4009
>> +#define ARMV8_SPE_PERFCTR_L2I_CACHE_LMISS 0x400A
>> +#define ARMV8_SPE_PERFCTR_L3D_CACHE_LMISS_RD 0x400B
>> +#define ARMV8_SPE_PERFCTR_LDST_ALIGN_LAT 0x4020
>> +#define ARMV8_SPE_PERFCTR_LD_ALIGN_LAT 0x4021
>> +#define ARMV8_SPE_PERFCTR_ST_ALIGN_LAT 0x4022
>> +#define ARMV8_SPE_PERFCTR_MEM_ACCESS_CHECKED 0x4024
>> +#define ARMV8_SPE_PERFCTR_MEM_ACCESS_CHECKED_RD 0x4025
>> +#define ARMV8_SPE_PERFCTR_MEM_ACCESS_CHECKED_WR 0x4026
>
> I think the naming is off here, as these don't seem to have anything to do
> with SPE afaict.
>
Right, some are about AMUv1 events and Memory Tagging Extensions, I will comment
them correspondingly in v2.
Thanks,
Shaokun
> Will
>
> .
>
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] arm64: perf: Expose some new events via sysfs
2020-05-01 17:12 ` Will Deacon
2020-05-04 1:31 ` Shaokun Zhang
@ 2020-05-04 3:46 ` Shaokun Zhang
2020-05-04 7:06 ` Will Deacon
1 sibling, 1 reply; 6+ messages in thread
From: Shaokun Zhang @ 2020-05-04 3:46 UTC (permalink / raw)
To: Will Deacon; +Cc: Mark Rutland, linux-arm-kernel
Hi Will,
One more question;-)
On 2020/5/2 1:12, Will Deacon wrote:
> On Tue, Apr 21, 2020 at 02:31:53PM +0800, Shaokun Zhang wrote:
>> Some new PMU events can been detected by PMCEID1_EL0, but it can't
>> be listed, Let's expose these through sysfs.
>>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
>> ---
>> arch/arm64/include/asm/perf_event.h | 19 +++++++++++++++++++
>> arch/arm64/kernel/perf_event.c | 19 +++++++++++++++++++
>> 2 files changed, 38 insertions(+)
>>
>> diff --git a/arch/arm64/include/asm/perf_event.h b/arch/arm64/include/asm/perf_event.h
>> index e7765b62c712..f1b93d7c4260 100644
>> --- a/arch/arm64/include/asm/perf_event.h
>> +++ b/arch/arm64/include/asm/perf_event.h
>> @@ -72,12 +72,31 @@
>> #define ARMV8_PMUV3_PERFCTR_LL_CACHE_RD 0x36
>> #define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD 0x37
>> #define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD 0x38
>> +#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD 0x39
>> +#define ARMV8_PMUV3_PERFCTR_OP_RETIRED 0x3A
>> +#define ARMV8_PMUV3_PERFCTR_OP_SPEC 0x3B
>> +#define ARMV8_PMUV3_PERFCTR_STALL 0x3C
>> +#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND 0x3D
>> +#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND 0x3E
>> +#define ARMV8_PMUV3_PERFCTR_STALL_SLOT 0x3F
>
> Hmm, looks like the presence of this event implies the presence of the
> PMMIR_EL1 register. Should we be exposing the "SLOTS" field from that in
> sysfs? (obviously as a separate patch)
>
Shall I expose it in /sys/devices/system/cpu/cpuX/regs/, right?
Thanks,
Shaokun
>>
>> /* Statistical profiling extension microarchitectural events */
>> #define ARMV8_SPE_PERFCTR_SAMPLE_POP 0x4000
>> #define ARMV8_SPE_PERFCTR_SAMPLE_FEED 0x4001
>> #define ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE 0x4002
>> #define ARMV8_SPE_PERFCTR_SAMPLE_COLLISION 0x4003
>> +#define ARMV8_SPE_PERFCTR_CNT_CYCLES 0x4004
>> +#define ARMV8_SPE_PERFCTR_STALL_BACKEND_MEM 0x4005
>> +#define ARMV8_SPE_PERFCTR_L1I_CACHE_LMISS 0x4006
>> +#define ARMV8_SPE_PERFCTR_L2D_CACHE_LMISS_RD 0x4009
>> +#define ARMV8_SPE_PERFCTR_L2I_CACHE_LMISS 0x400A
>> +#define ARMV8_SPE_PERFCTR_L3D_CACHE_LMISS_RD 0x400B
>> +#define ARMV8_SPE_PERFCTR_LDST_ALIGN_LAT 0x4020
>> +#define ARMV8_SPE_PERFCTR_LD_ALIGN_LAT 0x4021
>> +#define ARMV8_SPE_PERFCTR_ST_ALIGN_LAT 0x4022
>> +#define ARMV8_SPE_PERFCTR_MEM_ACCESS_CHECKED 0x4024
>> +#define ARMV8_SPE_PERFCTR_MEM_ACCESS_CHECKED_RD 0x4025
>> +#define ARMV8_SPE_PERFCTR_MEM_ACCESS_CHECKED_WR 0x4026
>
> I think the naming is off here, as these don't seem to have anything to do
> with SPE afaict.
>
> Will
>
> .
>
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] arm64: perf: Expose some new events via sysfs
2020-05-04 3:46 ` Shaokun Zhang
@ 2020-05-04 7:06 ` Will Deacon
2020-05-05 2:21 ` Shaokun Zhang
0 siblings, 1 reply; 6+ messages in thread
From: Will Deacon @ 2020-05-04 7:06 UTC (permalink / raw)
To: Shaokun Zhang; +Cc: Mark Rutland, linux-arm-kernel
On Mon, May 04, 2020 at 11:46:14AM +0800, Shaokun Zhang wrote:
> Hi Will,
>
> One more question;-)
>
> On 2020/5/2 1:12, Will Deacon wrote:
> > On Tue, Apr 21, 2020 at 02:31:53PM +0800, Shaokun Zhang wrote:
> >> Some new PMU events can been detected by PMCEID1_EL0, but it can't
> >> be listed, Let's expose these through sysfs.
> >>
> >> Cc: Will Deacon <will@kernel.org>
> >> Cc: Mark Rutland <mark.rutland@arm.com>
> >> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
> >> ---
> >> arch/arm64/include/asm/perf_event.h | 19 +++++++++++++++++++
> >> arch/arm64/kernel/perf_event.c | 19 +++++++++++++++++++
> >> 2 files changed, 38 insertions(+)
> >>
> >> diff --git a/arch/arm64/include/asm/perf_event.h b/arch/arm64/include/asm/perf_event.h
> >> index e7765b62c712..f1b93d7c4260 100644
> >> --- a/arch/arm64/include/asm/perf_event.h
> >> +++ b/arch/arm64/include/asm/perf_event.h
> >> @@ -72,12 +72,31 @@
> >> #define ARMV8_PMUV3_PERFCTR_LL_CACHE_RD 0x36
> >> #define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD 0x37
> >> #define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD 0x38
> >> +#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD 0x39
> >> +#define ARMV8_PMUV3_PERFCTR_OP_RETIRED 0x3A
> >> +#define ARMV8_PMUV3_PERFCTR_OP_SPEC 0x3B
> >> +#define ARMV8_PMUV3_PERFCTR_STALL 0x3C
> >> +#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND 0x3D
> >> +#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND 0x3E
> >> +#define ARMV8_PMUV3_PERFCTR_STALL_SLOT 0x3F
> >
> > Hmm, looks like the presence of this event implies the presence of the
> > PMMIR_EL1 register. Should we be exposing the "SLOTS" field from that in
> > sysfs? (obviously as a separate patch)
> >
>
> Shall I expose it in /sys/devices/system/cpu/cpuX/regs/, right?
No; if we need to expose it (do we?) then it should be alongside the other
PMU files. e.g. /sys/bus/event_source/$pmu_name/caps/slots
Will
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] arm64: perf: Expose some new events via sysfs
2020-05-04 7:06 ` Will Deacon
@ 2020-05-05 2:21 ` Shaokun Zhang
0 siblings, 0 replies; 6+ messages in thread
From: Shaokun Zhang @ 2020-05-05 2:21 UTC (permalink / raw)
To: Will Deacon; +Cc: Mark Rutland, linux-arm-kernel
Hi Will,
On 2020/5/4 15:06, Will Deacon wrote:
> On Mon, May 04, 2020 at 11:46:14AM +0800, Shaokun Zhang wrote:
>> Hi Will,
>>
>> One more question;-)
>>
>> On 2020/5/2 1:12, Will Deacon wrote:
>>> On Tue, Apr 21, 2020 at 02:31:53PM +0800, Shaokun Zhang wrote:
>>>> Some new PMU events can been detected by PMCEID1_EL0, but it can't
>>>> be listed, Let's expose these through sysfs.
>>>>
>>>> Cc: Will Deacon <will@kernel.org>
>>>> Cc: Mark Rutland <mark.rutland@arm.com>
>>>> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
>>>> ---
>>>> arch/arm64/include/asm/perf_event.h | 19 +++++++++++++++++++
>>>> arch/arm64/kernel/perf_event.c | 19 +++++++++++++++++++
>>>> 2 files changed, 38 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/include/asm/perf_event.h b/arch/arm64/include/asm/perf_event.h
>>>> index e7765b62c712..f1b93d7c4260 100644
>>>> --- a/arch/arm64/include/asm/perf_event.h
>>>> +++ b/arch/arm64/include/asm/perf_event.h
>>>> @@ -72,12 +72,31 @@
>>>> #define ARMV8_PMUV3_PERFCTR_LL_CACHE_RD 0x36
>>>> #define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD 0x37
>>>> #define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD 0x38
>>>> +#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD 0x39
>>>> +#define ARMV8_PMUV3_PERFCTR_OP_RETIRED 0x3A
>>>> +#define ARMV8_PMUV3_PERFCTR_OP_SPEC 0x3B
>>>> +#define ARMV8_PMUV3_PERFCTR_STALL 0x3C
>>>> +#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND 0x3D
>>>> +#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND 0x3E
>>>> +#define ARMV8_PMUV3_PERFCTR_STALL_SLOT 0x3F
>>>
>>> Hmm, looks like the presence of this event implies the presence of the
>>> PMMIR_EL1 register. Should we be exposing the "SLOTS" field from that in
>>> sysfs? (obviously as a separate patch)
>>>
>>
>> Shall I expose it in /sys/devices/system/cpu/cpuX/regs/, right?
>
> No; if we need to expose it (do we?) then it should be alongside the other
It seems that we need it if the PMU version is equal or greater than ARMv8.4-PMU.
> PMU files. e.g. /sys/bus/event_source/$pmu_name/caps/slots
>
Got it, I did it as /sys/bus/event_source/devices/armv8_pmuv3_0/caps/slots or
/sys/devices/armv8_pmuv3_0/caps/slots.
Thanks,
Shaokun
> Will
>
> .
>
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end of thread, other threads:[~2020-05-05 2:22 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-04-21 6:31 [PATCH] arm64: perf: Expose some new events via sysfs Shaokun Zhang
2020-05-01 17:12 ` Will Deacon
2020-05-04 1:31 ` Shaokun Zhang
2020-05-04 3:46 ` Shaokun Zhang
2020-05-04 7:06 ` Will Deacon
2020-05-05 2:21 ` Shaokun Zhang
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