From: Zhou Wang <wangzhou1@hisilicon.com>
To: <xuwei5@huawei.com>, Catalin Marinas <catalin.marinas@arm.com>,
"Will Deacon" <will@kernel.org>
Cc: Zhou Wang <wangzhou1@hisilicon.com>,
linuxarm@huawei.com, linux-arm-kernel@lists.infradead.org
Subject: [PATCH] arm64: defconfig: Enable UACCE/PCI PASID/SEC2/HPRE configs
Date: Sat, 9 May 2020 10:05:18 +0800 [thread overview]
Message-ID: <1588989918-53184-1-git-send-email-wangzhou1@hisilicon.com> (raw)
Enable configs for UACCE, PCI PASID, HiSilicon SEC2 and HPRE drivers.
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
---
arch/arm64/configs/defconfig | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 24e534d..b6edf59 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -188,6 +188,7 @@ CONFIG_NET_9P_VIRTIO=y
CONFIG_PCI=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCI_IOV=y
+CONFIG_PCI_PASID=y
CONFIG_HOTPLUG_PCI=y
CONFIG_HOTPLUG_PCI_ACPI=y
CONFIG_PCI_AARDVARK=y
@@ -241,6 +242,7 @@ CONFIG_BLK_DEV_NVME=m
CONFIG_SRAM=y
CONFIG_EEPROM_AT24=m
CONFIG_EEPROM_AT25=m
+CONFIG_UACCE=m
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_SAS_ATA=y
@@ -968,6 +970,8 @@ CONFIG_CRYPTO_DEV_FSL_CAAM=m
CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=m
CONFIG_CRYPTO_DEV_QCOM_RNG=m
CONFIG_CRYPTO_DEV_CCREE=m
+CONFIG_CRYPTO_DEV_HISI_SEC2=m
+CONFIG_CRYPTO_DEV_HISI_HPRE=m
CONFIG_CRYPTO_DEV_HISI_ZIP=m
CONFIG_CMA_SIZE_MBYTES=32
CONFIG_PRINTK_TIME=y
--
2.8.1
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next reply other threads:[~2020-05-09 2:09 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-09 2:05 Zhou Wang [this message]
2020-05-15 7:13 ` [PATCH] arm64: defconfig: Enable UACCE/PCI PASID/SEC2/HPRE configs Wei Xu
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