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Wed, 27 May 2020 19:36:40 -0800 Received: from MTKMBS31DR.mediatek.inc (172.27.6.102) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 27 May 2020 20:36:38 -0700 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS31DR.mediatek.inc (172.27.6.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 May 2020 11:36:30 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 May 2020 11:36:29 +0800 Message-ID: <1590636882.8804.474.camel@mhfsdcap03> Subject: Re: [V9, 1/2] media: dt-bindings: media: i2c: Document OV02A10 bindings From: Dongchun Zhu To: Sakari Ailus Date: Thu, 28 May 2020 11:34:42 +0800 In-Reply-To: <20200527211628.GT7618@paasikivi.fi.intel.com> References: <20200523084103.31276-1-dongchun.zhu@mediatek.com> <20200523084103.31276-2-dongchun.zhu@mediatek.com> <20200526182847.GA92449@bogus> <1590569355.8804.448.camel@mhfsdcap03> <20200527211628.GT7618@paasikivi.fi.intel.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 0450CC54ABF4AD762CD5AF3FD76B1C4256091870E9459F877A5F0726FFA223302000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200527_203642_287889_CB0606C5 X-CRM114-Status: GOOD ( 15.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Rob Herring , Andy Shevchenko , srv_heupstream , devicetree@vger.kernel.org, Linus Walleij , Shengnan Wang =?UTF-8?Q?=28=E7=8E=8B=E5=9C=A3=E7=94=B7=29?= , Tomasz Figa , Bartosz Golaszewski , Sj Huang , Nicolas Boichat , "moderated list:ARM/Mediatek SoC support" , dongchun.zhu@mediatek.com, Louis Kuo , Matthias Brugger , Cao Bing Bu , Mauro Carvalho Chehab , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , Linux Media Mailing List Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Sakari, Rob, On Thu, 2020-05-28 at 00:16 +0300, Sakari Ailus wrote: > Hi Rob, Dongchun, > > On Wed, May 27, 2020 at 09:27:22AM -0600, Rob Herring wrote: > > > > > + properties: > > > > > + endpoint: > > > > > + type: object > > > > > + additionalProperties: false > > > > > + > > > > > + properties: > > > > > > Actually I wonder whether we need to declare 'clock-lanes' here? > > > > Yes, if you are using it. > > Dongchun, can you confirm the chip has a single data and a single clock > lane and that it does not support lane reordering? > >From the datasheet, 'MIPI inside the OV02A10 provides one single uni-directional clock lane and one bi-directional data lane solution for communication links between components inside a mobile device. The data lane has full support for HS(uni-directional) and LP(bi-directional) data transfer mode.' The sensor doesn't support lane reordering, so 'clock-lanes' property would not be added in next release. > So if there's nothing to convey to the driver, also the data-lanes should > be removed IMO. > However, 'data-lanes' property may still be required. It is known that either data-lanes or clock-lanes is an array of physical data lane indexes. Position of an entry determines the logical lane number, while the value of an entry indicates physical lane, e.g., for 1-lane MIPI CSI-2 bus we could have "data-lanes = <1>;", assuming the clock lane is on hardware lane 0. As mentioned earlier, the OV02A10 sensor supports only 1C1D and does not support lane reordering, so here we shall use 'data-lanes = <1>' as there is only a clock lane for OV02A10. Reminder: If 'data-lanes' property is not present, the driver would assume four-lane operation. This means for one-lane or two-lane operation, this property must be present and set to the right physical lane indexes. If the hardware does not support lane reordering, monotonically incremented values shall be used from 0 or 1 onwards, depending on whether or not there is also a clock lane. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel