From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6985CC433E0 for ; Fri, 24 Jul 2020 09:51:01 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3126520674 for ; Fri, 24 Jul 2020 09:51:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Z6ArFgdQ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3126520674 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=hisilicon.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=nD6tQ0Q9iHBN0gqpG3TwtqhhhIBfne8Ws9wJh/1uwzg=; b=Z6ArFgdQvNFFojzlNLb2HPusrj HEZnFu5R3l6bxe8jIidSUSDUck1zvHIFRXG0Ol3KeoKZIOxfyWO6kzvkQrQHKlr+Gs0eZ4JxNKOlq nNArc6tRzQwIKl9/4nxnVOBcz92i3wDxXyrWcIyrCtkABjGAlOYTOZ14EZjbDoRdvyvRVNRykn1xu DxmgE8x1HIdrK9OMB+sOQ4FNJZyygOlqe72tGJRyepWaQIzTPUkcgAUlRjI+0aY7bwV2NXToYlSUZ EAhX0l77OMsMLqDUJuI/MuLvvDNKQd/fl5L+oe9reaS4lNv2NnAkHapX8nQSZUr0dLlO1Hr1VL2vK 68FWxwdA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jyuKX-0003nR-4c; Fri, 24 Jul 2020 09:49:29 +0000 Received: from szxga07-in.huawei.com ([45.249.212.35] helo=huawei.com) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jyuKU-0003mX-CY for linux-arm-kernel@lists.infradead.org; Fri, 24 Jul 2020 09:49:27 +0000 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 66DB0291D677EBAADDC6; Fri, 24 Jul 2020 17:49:23 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.487.0; Fri, 24 Jul 2020 17:49:13 +0800 From: Shaokun Zhang To: Subject: [PATCH] arm64: arch_timer: Ensure timer is enabled before using istatus Date: Fri, 24 Jul 2020 17:47:17 +0800 Message-ID: <1595584037-6877-1-git-send-email-zhangshaokun@hisilicon.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200724_054926_699337_DA69B541 X-CRM114-Status: UNSURE ( 8.43 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Marc Zyngier , Daniel Lezcano , Shaokun Zhang , Nianyao Tang Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Nianyao Tang In Arm ARM spec, there is a description for timer control register, when the value of the ENABLE bit is 0, the ISTATUS field is UNKNOWN. We shall only read and use ISTATUS when ENABLE is 1, otherwise ISTATUS may be invalid. Cc: Mark Rutland Cc: Marc Zyngier Cc: Daniel Lezcano Signed-off-by: Nianyao Tang Signed-off-by: Shaokun Zhang --- drivers/clocksource/arm_arch_timer.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 6c3e84180146..0bbc2715de79 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -641,7 +641,8 @@ static __always_inline irqreturn_t timer_handler(const int access, unsigned long ctrl; ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt); - if (ctrl & ARCH_TIMER_CTRL_IT_STAT) { + if ((ctrl & ARCH_TIMER_CTRL_ENABLE) && + (ctrl & ARCH_TIMER_CTRL_IT_STAT)) { ctrl |= ARCH_TIMER_CTRL_IT_MASK; arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt); evt->event_handler(evt); -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel