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Wed, 29 Jul 2020 00:22:02 -0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 29 Jul 2020 01:19:11 -0700 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 29 Jul 2020 16:19:08 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 29 Jul 2020 16:19:07 +0800 Message-ID: <1596010724.11360.6.camel@mhfsdcap03> Subject: Re: [PATCH 2/2] arm64: dts: mt8192: add infracfg_rst node From: Crystal Guo To: Matthias Brugger Date: Wed, 29 Jul 2020 16:18:44 +0800 In-Reply-To: References: <1596008357-11213-1-git-send-email-crystal.guo@mediatek.com> <1596008357-11213-3-git-send-email-crystal.guo@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200729_042156_210439_AEF144C0 X-CRM114-Status: GOOD ( 17.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "devicetree@vger.kernel.org" , srv_heupstream , Seiya Wang =?UTF-8?Q?=28=E7=8E=8B=E8=BF=BA=E5=90=9B=29?= , "linux-kernel@vger.kernel.org" , "robh+dt@kernel.org" , "linux-mediatek@lists.infradead.org" , "p.zabel@pengutronix.de" , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 2020-07-29 at 15:45 +0800, Matthias Brugger wrote: > > On 29/07/2020 09:39, Crystal Guo wrote: > > add infracfg_rst node which is for MT8192 platform > > > > Signed-off-by: Crystal Guo > > --- > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 +++++++++- > > 1 file changed, 9 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > index b16dbbd..adc6239 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > > @@ -217,9 +217,17 @@ > > }; > > > > infracfg: infracfg@10001000 { > > - compatible = "mediatek,mt8192-infracfg", "syscon"; > > + compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd"; > > reg = <0 0x10001000 0 0x1000>; > > #clock-cells = <1>; > > + > > + infracfg_rst: reset-controller { > > + compatible = "ti,syscon-reset"; > > + #reset-cells = <1>; > > + ti,reset-bits = < > > + 0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: pcie */ > > You have Texas Instruments hardware inside infracfg? Are you sure? > TI reset-controller driver is a common driver, MTK SOC has the similar control flow, thus can reuse it. > > + >; > > + }; > > }; > > > > pericfg: pericfg@10003000 { > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel