* [PATCH v3 1/4] i2c: mediatek: Add apdma sync in i2c driver
2020-08-05 10:52 [PATCH v3 0/4] add i2c support for mt8192 Qii Wang
@ 2020-08-05 10:52 ` Qii Wang
2020-08-05 10:52 ` [PATCH v3 2/4] i2c: mediatek: Add access to more than 8GB dram " Qii Wang
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Qii Wang @ 2020-08-05 10:52 UTC (permalink / raw)
To: wsa
Cc: devicetree, qii.wang, srv_heupstream, linux-kernel, robh+dt,
linux-mediatek, linux-i2c, linux-arm-kernel
With the apdma remove hand-shake signal, it need to keep i2c and
apdma in sync manually.
Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
---
drivers/i2c/busses/i2c-mt65xx.c | 23 ++++++++++++++++++++---
1 file changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index deef69e..e6b984a 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -48,6 +48,9 @@
#define I2C_DMA_CON_TX 0x0000
#define I2C_DMA_CON_RX 0x0001
+#define I2C_DMA_ASYNC_MODE 0x0004
+#define I2C_DMA_SKIP_CONFIG 0x0010
+#define I2C_DMA_DIR_CHANGE 0x0200
#define I2C_DMA_START_EN 0x0001
#define I2C_DMA_INT_FLAG_NONE 0x0000
#define I2C_DMA_CLR_FLAG 0x0000
@@ -205,6 +208,7 @@ struct mtk_i2c_compatible {
unsigned char timing_adjust: 1;
unsigned char dma_sync: 1;
unsigned char ltiming_adjust: 1;
+ unsigned char apdma_sync: 1;
};
struct mtk_i2c_ac_timing {
@@ -311,6 +315,7 @@ struct i2c_spec_values {
.timing_adjust = 1,
.dma_sync = 0,
.ltiming_adjust = 0,
+ .apdma_sync = 0,
};
static const struct mtk_i2c_compatible mt6577_compat = {
@@ -324,6 +329,7 @@ struct i2c_spec_values {
.timing_adjust = 0,
.dma_sync = 0,
.ltiming_adjust = 0,
+ .apdma_sync = 0,
};
static const struct mtk_i2c_compatible mt6589_compat = {
@@ -337,6 +343,7 @@ struct i2c_spec_values {
.timing_adjust = 0,
.dma_sync = 0,
.ltiming_adjust = 0,
+ .apdma_sync = 0,
};
static const struct mtk_i2c_compatible mt7622_compat = {
@@ -350,6 +357,7 @@ struct i2c_spec_values {
.timing_adjust = 0,
.dma_sync = 0,
.ltiming_adjust = 0,
+ .apdma_sync = 0,
};
static const struct mtk_i2c_compatible mt8173_compat = {
@@ -362,6 +370,7 @@ struct i2c_spec_values {
.timing_adjust = 0,
.dma_sync = 0,
.ltiming_adjust = 0,
+ .apdma_sync = 0,
};
static const struct mtk_i2c_compatible mt8183_compat = {
@@ -375,6 +384,7 @@ struct i2c_spec_values {
.timing_adjust = 1,
.dma_sync = 1,
.ltiming_adjust = 1,
+ .apdma_sync = 0,
};
static const struct of_device_id mtk_i2c_of_match[] = {
@@ -798,6 +808,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
u16 start_reg;
u16 control_reg;
u16 restart_flag = 0;
+ u16 dma_sync = 0;
u32 reg_4g_mode;
u8 *dma_rd_buf = NULL;
u8 *dma_wr_buf = NULL;
@@ -851,10 +862,16 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN);
}
+ if (i2c->dev_comp->apdma_sync) {
+ dma_sync = I2C_DMA_SKIP_CONFIG | I2C_DMA_ASYNC_MODE;
+ if (i2c->op == I2C_MASTER_WRRD)
+ dma_sync |= I2C_DMA_DIR_CHANGE;
+ }
+
/* Prepare buffer data to start transfer */
if (i2c->op == I2C_MASTER_RD) {
writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
- writel(I2C_DMA_CON_RX, i2c->pdmabase + OFFSET_CON);
+ writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON);
dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
if (!dma_rd_buf)
@@ -877,7 +894,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
} else if (i2c->op == I2C_MASTER_WR) {
writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
- writel(I2C_DMA_CON_TX, i2c->pdmabase + OFFSET_CON);
+ writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON);
dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
if (!dma_wr_buf)
@@ -900,7 +917,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
} else {
writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
- writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_CON);
+ writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON);
dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
if (!dma_wr_buf)
--
1.9.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v3 2/4] i2c: mediatek: Add access to more than 8GB dram in i2c driver
2020-08-05 10:52 [PATCH v3 0/4] add i2c support for mt8192 Qii Wang
2020-08-05 10:52 ` [PATCH v3 1/4] i2c: mediatek: Add apdma sync in i2c driver Qii Wang
@ 2020-08-05 10:52 ` Qii Wang
2020-08-05 10:52 ` [PATCH v3 3/4] dt-bindings: i2c: update bindings for MT8192 SoC Qii Wang
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Qii Wang @ 2020-08-05 10:52 UTC (permalink / raw)
To: wsa
Cc: devicetree, qii.wang, srv_heupstream, linux-kernel, robh+dt,
linux-mediatek, linux-i2c, linux-arm-kernel
Newer MTK chip support more than 8GB of dram. Replace support_33bits
with more general dma_max_support and remove mtk_i2c_set_4g_mode.
Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
---
drivers/i2c/busses/i2c-mt65xx.c | 39 +++++++++++++++++----------------------
1 file changed, 17 insertions(+), 22 deletions(-)
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index e6b984a..463860e 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -55,7 +55,6 @@
#define I2C_DMA_INT_FLAG_NONE 0x0000
#define I2C_DMA_CLR_FLAG 0x0000
#define I2C_DMA_HARD_RST 0x0002
-#define I2C_DMA_4G_MODE 0x0001
#define MAX_SAMPLE_CNT_DIV 8
#define MAX_STEP_CNT_DIV 64
@@ -204,11 +203,11 @@ struct mtk_i2c_compatible {
unsigned char dcm: 1;
unsigned char auto_restart: 1;
unsigned char aux_len_reg: 1;
- unsigned char support_33bits: 1;
unsigned char timing_adjust: 1;
unsigned char dma_sync: 1;
unsigned char ltiming_adjust: 1;
unsigned char apdma_sync: 1;
+ unsigned char max_dma_support;
};
struct mtk_i2c_ac_timing {
@@ -311,11 +310,11 @@ struct i2c_spec_values {
.dcm = 1,
.auto_restart = 1,
.aux_len_reg = 1,
- .support_33bits = 1,
.timing_adjust = 1,
.dma_sync = 0,
.ltiming_adjust = 0,
.apdma_sync = 0,
+ .max_dma_support = 33,
};
static const struct mtk_i2c_compatible mt6577_compat = {
@@ -325,11 +324,11 @@ struct i2c_spec_values {
.dcm = 1,
.auto_restart = 0,
.aux_len_reg = 0,
- .support_33bits = 0,
.timing_adjust = 0,
.dma_sync = 0,
.ltiming_adjust = 0,
.apdma_sync = 0,
+ .max_dma_support = 32,
};
static const struct mtk_i2c_compatible mt6589_compat = {
@@ -339,11 +338,11 @@ struct i2c_spec_values {
.dcm = 0,
.auto_restart = 0,
.aux_len_reg = 0,
- .support_33bits = 0,
.timing_adjust = 0,
.dma_sync = 0,
.ltiming_adjust = 0,
.apdma_sync = 0,
+ .max_dma_support = 32,
};
static const struct mtk_i2c_compatible mt7622_compat = {
@@ -353,11 +352,11 @@ struct i2c_spec_values {
.dcm = 1,
.auto_restart = 1,
.aux_len_reg = 1,
- .support_33bits = 0,
.timing_adjust = 0,
.dma_sync = 0,
.ltiming_adjust = 0,
.apdma_sync = 0,
+ .max_dma_support = 32,
};
static const struct mtk_i2c_compatible mt8173_compat = {
@@ -366,11 +365,11 @@ struct i2c_spec_values {
.dcm = 1,
.auto_restart = 1,
.aux_len_reg = 1,
- .support_33bits = 1,
.timing_adjust = 0,
.dma_sync = 0,
.ltiming_adjust = 0,
.apdma_sync = 0,
+ .max_dma_support = 33,
};
static const struct mtk_i2c_compatible mt8183_compat = {
@@ -380,11 +379,11 @@ struct i2c_spec_values {
.dcm = 0,
.auto_restart = 1,
.aux_len_reg = 1,
- .support_33bits = 1,
.timing_adjust = 1,
.dma_sync = 1,
.ltiming_adjust = 1,
.apdma_sync = 0,
+ .max_dma_support = 33,
};
static const struct of_device_id mtk_i2c_of_match[] = {
@@ -796,11 +795,6 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
return 0;
}
-static inline u32 mtk_i2c_set_4g_mode(dma_addr_t addr)
-{
- return (addr & BIT_ULL(32)) ? I2C_DMA_4G_MODE : I2C_DMA_CLR_FLAG;
-}
-
static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
int num, int left_num)
{
@@ -885,8 +879,8 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
return -ENOMEM;
}
- if (i2c->dev_comp->support_33bits) {
- reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
+ if (i2c->dev_comp->max_dma_support > 32) {
+ reg_4g_mode = upper_32_bits(rpaddr);
writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
}
@@ -908,8 +902,8 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
return -ENOMEM;
}
- if (i2c->dev_comp->support_33bits) {
- reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
+ if (i2c->dev_comp->max_dma_support > 32) {
+ reg_4g_mode = upper_32_bits(wpaddr);
writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
}
@@ -954,11 +948,11 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
return -ENOMEM;
}
- if (i2c->dev_comp->support_33bits) {
- reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
+ if (i2c->dev_comp->max_dma_support > 32) {
+ reg_4g_mode = upper_32_bits(wpaddr);
writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
- reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
+ reg_4g_mode = upper_32_bits(rpaddr);
writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
}
@@ -1232,8 +1226,9 @@ static int mtk_i2c_probe(struct platform_device *pdev)
return -EINVAL;
}
- if (i2c->dev_comp->support_33bits) {
- ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(33));
+ if (i2c->dev_comp->max_dma_support > 32) {
+ ret = dma_set_mask(&pdev->dev,
+ DMA_BIT_MASK(i2c->dev_comp->max_dma_support));
if (ret) {
dev_err(&pdev->dev, "dma_set_mask return error.\n");
return ret;
--
1.9.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v3 3/4] dt-bindings: i2c: update bindings for MT8192 SoC
2020-08-05 10:52 [PATCH v3 0/4] add i2c support for mt8192 Qii Wang
2020-08-05 10:52 ` [PATCH v3 1/4] i2c: mediatek: Add apdma sync in i2c driver Qii Wang
2020-08-05 10:52 ` [PATCH v3 2/4] i2c: mediatek: Add access to more than 8GB dram " Qii Wang
@ 2020-08-05 10:52 ` Qii Wang
2020-08-05 10:52 ` [PATCH v3 4/4] i2c: mediatek: Add i2c compatible for MediaTek MT8192 Qii Wang
2020-08-05 21:42 ` [PATCH v3 0/4] add i2c support for mt8192 wsa
4 siblings, 0 replies; 7+ messages in thread
From: Qii Wang @ 2020-08-05 10:52 UTC (permalink / raw)
To: wsa
Cc: devicetree, qii.wang, srv_heupstream, linux-kernel, robh+dt,
linux-mediatek, linux-i2c, linux-arm-kernel
Add a DT binding documentation for the MT8192 soc.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
---
Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt
index 88b71c1..7f0194f 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt
@@ -14,6 +14,7 @@ Required properties:
"mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek MT7629
"mediatek,mt8173-i2c": for MediaTek MT8173
"mediatek,mt8183-i2c": for MediaTek MT8183
+ "mediatek,mt8192-i2c": for MediaTek MT8192
"mediatek,mt8516-i2c", "mediatek,mt2712-i2c": for MediaTek MT8516
- reg: physical base address of the controller and dma base, length of memory
mapped region.
--
1.9.1
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v3 4/4] i2c: mediatek: Add i2c compatible for MediaTek MT8192
2020-08-05 10:52 [PATCH v3 0/4] add i2c support for mt8192 Qii Wang
` (2 preceding siblings ...)
2020-08-05 10:52 ` [PATCH v3 3/4] dt-bindings: i2c: update bindings for MT8192 SoC Qii Wang
@ 2020-08-05 10:52 ` Qii Wang
2020-08-05 21:42 ` [PATCH v3 0/4] add i2c support for mt8192 wsa
4 siblings, 0 replies; 7+ messages in thread
From: Qii Wang @ 2020-08-05 10:52 UTC (permalink / raw)
To: wsa
Cc: devicetree, qii.wang, srv_heupstream, linux-kernel, robh+dt,
linux-mediatek, linux-i2c, linux-arm-kernel
Add i2c compatible for MT8192. Compare to MT8183 i2c controller,
MT8192 support more then 8GB DMA mode.
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
---
drivers/i2c/busses/i2c-mt65xx.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index 463860e..e889f74 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -386,6 +386,20 @@ struct i2c_spec_values {
.max_dma_support = 33,
};
+static const struct mtk_i2c_compatible mt8192_compat = {
+ .quirks = &mt8183_i2c_quirks,
+ .regs = mt_i2c_regs_v2,
+ .pmic_i2c = 0,
+ .dcm = 0,
+ .auto_restart = 1,
+ .aux_len_reg = 1,
+ .timing_adjust = 1,
+ .dma_sync = 1,
+ .ltiming_adjust = 1,
+ .apdma_sync = 1,
+ .max_dma_support = 36,
+};
+
static const struct of_device_id mtk_i2c_of_match[] = {
{ .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat },
{ .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
@@ -393,6 +407,7 @@ struct i2c_spec_values {
{ .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
{ .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
{ .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
+ { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat },
{}
};
MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
--
1.9.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v3 0/4] add i2c support for mt8192
2020-08-05 10:52 [PATCH v3 0/4] add i2c support for mt8192 Qii Wang
` (3 preceding siblings ...)
2020-08-05 10:52 ` [PATCH v3 4/4] i2c: mediatek: Add i2c compatible for MediaTek MT8192 Qii Wang
@ 2020-08-05 21:42 ` wsa
2020-08-06 6:30 ` Matthias Brugger
4 siblings, 1 reply; 7+ messages in thread
From: wsa @ 2020-08-05 21:42 UTC (permalink / raw)
To: Qii Wang
Cc: devicetree, srv_heupstream, linux-kernel, robh+dt, linux-mediatek,
linux-i2c, linux-arm-kernel
[-- Attachment #1.1: Type: text/plain, Size: 1461 bytes --]
On Wed, Aug 05, 2020 at 06:52:18PM +0800, Qii Wang wrote:
> This series are based on 5.8-rc1 and we provide four i2c patches
> to support mt8192 SoC.
>
> Main changes compared to v2:
> --delete unused I2C_DMA_4G_MODE
>
> Main changes compared to v1:
> --modify the commit with access more than 8GB dram
> --add Reviewed-by and Acked-by from Yingjoe, Matthias and Rob
>
> Qii Wang (4):
> i2c: mediatek: Add apdma sync in i2c driver
> i2c: mediatek: Add access to more than 8GB dram in i2c driver
> dt-bindings: i2c: update bindings for MT8192 SoC
> i2c: mediatek: Add i2c compatible for MediaTek MT8192
>
> .../devicetree/bindings/i2c/i2c-mt65xx.txt | 1 +
Applied to for-next, thanks!
Sidenote: I get these warnings when compiling the driver:
drivers/i2c/busses/i2c-mt65xx.c:267: warning: Function parameter or member 'min_low_ns' not described in 'i2c_spec_values'
drivers/i2c/busses/i2c-mt65xx.c:267: warning: Function parameter or member 'min_high_ns' not described in 'i2c_spec_values'
drivers/i2c/busses/i2c-mt65xx.c:267: warning: Function parameter or member 'min_su_sta_ns' not described in 'i2c_spec_values'
drivers/i2c/busses/i2c-mt65xx.c:267: warning: Function parameter or member 'max_hd_dat_ns' not described in 'i2c_spec_values'
drivers/i2c/busses/i2c-mt65xx.c:267: warning: Function parameter or member 'min_su_dat_ns' not described in 'i2c_spec_values'
Is someone interested to fix these?
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
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^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v3 0/4] add i2c support for mt8192
2020-08-05 21:42 ` [PATCH v3 0/4] add i2c support for mt8192 wsa
@ 2020-08-06 6:30 ` Matthias Brugger
0 siblings, 0 replies; 7+ messages in thread
From: Matthias Brugger @ 2020-08-06 6:30 UTC (permalink / raw)
To: wsa, Qii Wang, robh+dt, linux-i2c, devicetree, linux-arm-kernel,
linux-kernel, linux-mediatek, srv_heupstream
On 05/08/2020 23:42, wsa@the-dreams.de wrote:
> On Wed, Aug 05, 2020 at 06:52:18PM +0800, Qii Wang wrote:
>> This series are based on 5.8-rc1 and we provide four i2c patches
>> to support mt8192 SoC.
>>
>> Main changes compared to v2:
>> --delete unused I2C_DMA_4G_MODE
>>
>> Main changes compared to v1:
>> --modify the commit with access more than 8GB dram
>> --add Reviewed-by and Acked-by from Yingjoe, Matthias and Rob
>>
>> Qii Wang (4):
>> i2c: mediatek: Add apdma sync in i2c driver
>> i2c: mediatek: Add access to more than 8GB dram in i2c driver
>> dt-bindings: i2c: update bindings for MT8192 SoC
>> i2c: mediatek: Add i2c compatible for MediaTek MT8192
>>
>> .../devicetree/bindings/i2c/i2c-mt65xx.txt | 1 +
>
> Applied to for-next, thanks!
>
> Sidenote: I get these warnings when compiling the driver:
>
> drivers/i2c/busses/i2c-mt65xx.c:267: warning: Function parameter or member 'min_low_ns' not described in 'i2c_spec_values'
> drivers/i2c/busses/i2c-mt65xx.c:267: warning: Function parameter or member 'min_high_ns' not described in 'i2c_spec_values'
> drivers/i2c/busses/i2c-mt65xx.c:267: warning: Function parameter or member 'min_su_sta_ns' not described in 'i2c_spec_values'
> drivers/i2c/busses/i2c-mt65xx.c:267: warning: Function parameter or member 'max_hd_dat_ns' not described in 'i2c_spec_values'
> drivers/i2c/busses/i2c-mt65xx.c:267: warning: Function parameter or member 'min_su_dat_ns' not described in 'i2c_spec_values'
>
> Is someone interested to fix these?
>
I just send a fix for that.
Regards,
Matthias
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