* [PATCH V6 00/12]PCI:Add SPEAr13xx PCie support
@ 2014-02-11 9:29 Mohit Kumar
2014-02-11 9:29 ` [PATCH V6 01/12] clk: SPEAr13XX: Fix pcie clock name Mohit Kumar
` (5 more replies)
0 siblings, 6 replies; 10+ messages in thread
From: Mohit Kumar @ 2014-02-11 9:29 UTC (permalink / raw)
To: linux-arm-kernel
Patch# 1 and 2: Improvement and fixes for SPEAr13xx support.
Patch# 3,5 and 8: Add DT bindings for miphy40lp, misc and pcie node
Patch# 4,6 and 7: Add miphy40lp skelten driver and support for spear1310/40
miphy wrapper.
Patch# 9-11: Add SPEAr13xx PCIe driver and dt support.
These pathes are tested with linux-3.14-rc1 with following patch on the top of
it:
Author: Balaji T K <balajitk@ti.com>
Date: Mon Jan 20 16:41:27 2014 +0200
ata: ahci_platform: Manage SATA PHY
Tested with SPEAr1310 evaluation board:
- INTEL PRO 100/100 EP card
- USB xhci gen2 card
- Above cards connected through LeCROY PTC switch
Modifications for SATA are tested with SPEAr1340-evb board
Changes since v5:
- Split DT bindings for misc, miphy-40lp and pcie node into sepearte patches
- Merge config options PCIE_SPEAR13XX and PCI_MSI into defconfig patch
- Incorporated other minor comments
Changes since v4:
- Uses per device function pointers passed from .data field to
the of_device_id instead of of_device_is_compatible.
- Incorporated other minor comments from v4
Changes since v3:
- Phy driver renamed to phy-miphy40lp
- ahci phy hook patch used as suggested by Arnd
- Incorporated other minor comments from v3
Changes since v2:
- Incorporated comments to move SPEAr13xx PCIe and SATA phy specific routines to
the phy framework
- Modify ahci driver to include phy hooks
- phy-core driver modifications for subsys_initcall()
Changes since v1:
- Few patches of the series are already accepted and applied to mainline e.g.
pcie designware driver improvements,fixes for IO translation bug, PCIe dw
driver maintainer. So dropped these from v2.
- Incorporated comment to move the common/reset PCIe code to the seperate driver
- PCIe and SATA share common PHY configuration registers, so move SATA
platform code to the system config driver
Fourth patch is improves pcie designware driver and fixes the IO
translation bug. IO translation bug fix leads to the working of PCIe EP devices
connected to RC through switch.
PCIe driver support for SPEAr1310/40 platform board is added.
These patches are tested with SPEAr1310 evaluation board:
- INTEL PRO 100/100 EP card
- USB xhci gen2 card
- Above cards connected through LeCROY PTC switch
Cc: linux-arm-kernel at lists.infradead.org
Cc: devicetree at vger.kernel.org
Cc: linux-ide at vger.kernel.org
Cc: linux-pci at vger.kernel.org
Cc: spear-devel at list.st.com
Cc: linux-kernel at vger.kernel.org
Cc: linux-pm at vger.kernel.org
Mohit Kumar (2):
SPEAr13xx: defconfig: Update
MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer
Pratyush Anand (10):
clk: SPEAr13XX: Fix pcie clock name
SPEAr13XX: Fix static mapping table
phy: st-miphy40lp: Add binding information
phy: st-miphy40lp: Add skeleton driver
SPEAr: misc: Add binding information
SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
SPEAr13xx: Add binding information for PCIe controller
SPEAr13XX: dts: Add PCIe node information
pcie: SPEAr13xx: Add designware wrapper support
.../devicetree/bindings/arm/spear-misc.txt | 9 +
.../devicetree/bindings/pci/spear13xx-pcie.txt | 14 +
.../devicetree/bindings/phy/st-miphy40lp.txt | 18 +
MAINTAINERS | 6 +
arch/arm/boot/dts/spear1310-evb.dts | 4 +
arch/arm/boot/dts/spear1310.dtsi | 93 ++++-
arch/arm/boot/dts/spear1340-evb.dts | 4 +
arch/arm/boot/dts/spear1340.dtsi | 31 ++-
arch/arm/boot/dts/spear13xx.dtsi | 9 +-
arch/arm/configs/spear13xx_defconfig | 16 +
arch/arm/mach-spear/Kconfig | 3 +
arch/arm/mach-spear/include/mach/spear.h | 4 +-
arch/arm/mach-spear/spear1340.c | 127 +-----
arch/arm/mach-spear/spear13xx.c | 2 +-
drivers/clk/spear/spear1310_clock.c | 6 +-
drivers/clk/spear/spear1340_clock.c | 2 +-
drivers/pci/host/Kconfig | 8 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pcie-spear13xx.c | 414 +++++++++++++++
drivers/phy/Kconfig | 7 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-miphy40lp.c | 543 ++++++++++++++++++++
22 files changed, 1183 insertions(+), 139 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
create mode 100644 Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
create mode 100644 drivers/pci/host/pcie-spear13xx.c
create mode 100644 drivers/phy/phy-miphy40lp.c
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH V6 01/12] clk: SPEAr13XX: Fix pcie clock name
2014-02-11 9:29 [PATCH V6 00/12]PCI:Add SPEAr13xx PCie support Mohit Kumar
@ 2014-02-11 9:29 ` Mohit Kumar
2014-02-11 9:29 ` [PATCH V6 02/12] SPEAr13XX: Fix static mapping table Mohit Kumar
` (4 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Mohit Kumar @ 2014-02-11 9:29 UTC (permalink / raw)
To: linux-arm-kernel
From: Pratyush Anand <pratyush.anand@st.com>
Follow dt clock naming convention for PCIe clocks.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: spear-devel at list.st.com
Cc: linux-arm-kernel at lists.infradead.org
---
drivers/clk/spear/spear1310_clock.c | 6 +++---
drivers/clk/spear/spear1340_clock.c | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
index 65894f7..4daa597 100644
--- a/drivers/clk/spear/spear1310_clock.c
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -742,19 +742,19 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB,
0, &_lock);
- clk_register_clkdev(clk, NULL, "dw_pcie.0");
+ clk_register_clkdev(clk, NULL, "b1000000.pcie");
clk_register_clkdev(clk, NULL, "b1000000.ahci");
clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB,
0, &_lock);
- clk_register_clkdev(clk, NULL, "dw_pcie.1");
+ clk_register_clkdev(clk, NULL, "b1800000.pcie");
clk_register_clkdev(clk, NULL, "b1800000.ahci");
clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0,
SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB,
0, &_lock);
- clk_register_clkdev(clk, NULL, "dw_pcie.2");
+ clk_register_clkdev(clk, NULL, "b4000000.pcie");
clk_register_clkdev(clk, NULL, "b4000000.ahci");
clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index fe835c1..5a5c664 100644
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -839,7 +839,7 @@ void __init spear1340_clk_init(void __iomem *misc_base)
clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0,
SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB,
0, &_lock);
- clk_register_clkdev(clk, NULL, "dw_pcie");
+ clk_register_clkdev(clk, NULL, "b1000000.pcie");
clk_register_clkdev(clk, NULL, "b1000000.ahci");
clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
--
1.7.0.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH V6 02/12] SPEAr13XX: Fix static mapping table
2014-02-11 9:29 [PATCH V6 00/12]PCI:Add SPEAr13xx PCie support Mohit Kumar
2014-02-11 9:29 ` [PATCH V6 01/12] clk: SPEAr13XX: Fix pcie clock name Mohit Kumar
@ 2014-02-11 9:29 ` Mohit Kumar
2014-02-11 9:30 ` [PATCH V6 06/12] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver Mohit Kumar
` (3 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Mohit Kumar @ 2014-02-11 9:29 UTC (permalink / raw)
To: linux-arm-kernel
From: Pratyush Anand <pratyush.anand@st.com>
SPEAr13XX was using virtual address space 0xFE000000 to map physical address
space 0xB3000000. pci_remap_io uses 0xFEE00000 as virtual address. So
change 0xFE000000 to 0xF9000000.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Cc: spear-devel at list.st.com
Cc: stable at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
arch/arm/mach-spear/include/mach/spear.h | 4 ++--
arch/arm/mach-spear/spear13xx.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-spear/include/mach/spear.h b/arch/arm/mach-spear/include/mach/spear.h
index 5cdc53d..f2d6a01 100644
--- a/arch/arm/mach-spear/include/mach/spear.h
+++ b/arch/arm/mach-spear/include/mach/spear.h
@@ -52,10 +52,10 @@
#ifdef CONFIG_ARCH_SPEAR13XX
#define PERIP_GRP2_BASE UL(0xB3000000)
-#define VA_PERIP_GRP2_BASE IOMEM(0xFE000000)
+#define VA_PERIP_GRP2_BASE IOMEM(0xF9000000)
#define MCIF_SDHCI_BASE UL(0xB3000000)
#define SYSRAM0_BASE UL(0xB3800000)
-#define VA_SYSRAM0_BASE IOMEM(0xFE800000)
+#define VA_SYSRAM0_BASE IOMEM(0xF9800000)
#define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600)
#define PERIP_GRP1_BASE UL(0xE0000000)
diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c
index 7aa6e8c..89212ff 100644
--- a/arch/arm/mach-spear/spear13xx.c
+++ b/arch/arm/mach-spear/spear13xx.c
@@ -52,7 +52,7 @@ void __init spear13xx_l2x0_init(void)
/*
* Following will create 16MB static virtual/physical mappings
* PHYSICAL VIRTUAL
- * 0xB3000000 0xFE000000
+ * 0xB3000000 0xF9000000
* 0xE0000000 0xFD000000
* 0xEC000000 0xFC000000
* 0xED000000 0xFB000000
--
1.7.0.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH V6 06/12] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
2014-02-11 9:29 [PATCH V6 00/12]PCI:Add SPEAr13xx PCie support Mohit Kumar
2014-02-11 9:29 ` [PATCH V6 01/12] clk: SPEAr13XX: Fix pcie clock name Mohit Kumar
2014-02-11 9:29 ` [PATCH V6 02/12] SPEAr13XX: Fix static mapping table Mohit Kumar
@ 2014-02-11 9:30 ` Mohit Kumar
2014-02-11 11:35 ` Kishon Vijay Abraham I
2014-02-11 9:30 ` [PATCH V6 07/12] phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support Mohit Kumar
` (2 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Mohit Kumar @ 2014-02-11 9:30 UTC (permalink / raw)
To: linux-arm-kernel
From: Pratyush Anand <pratyush.anand@st.com>
ahci driver needs some platform specific functions which are called at
init, exit, suspend and resume conditions. Till now these functions were
present in a platform driver with a fixme notes.
Similar functions modifying same set of registers will also be needed in
case of PCIe phy init/exit.
So move all these SATA platform code to phy-miphy40lp driver.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Tested-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Tejun Heo <tj@kernel.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: spear-devel at list.st.com
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
arch/arm/boot/dts/spear1310-evb.dts | 4 +
arch/arm/boot/dts/spear1310.dtsi | 39 +++++++++-
arch/arm/boot/dts/spear1340-evb.dts | 4 +
arch/arm/boot/dts/spear1340.dtsi | 13 +++-
arch/arm/boot/dts/spear13xx.dtsi | 5 +
arch/arm/mach-spear/Kconfig | 2 +
arch/arm/mach-spear/spear1340.c | 127 +------------------------------
drivers/phy/phy-miphy40lp.c | 144 +++++++++++++++++++++++++++++++++++
8 files changed, 208 insertions(+), 130 deletions(-)
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
index b56a801..d42c84b 100644
--- a/arch/arm/boot/dts/spear1310-evb.dts
+++ b/arch/arm/boot/dts/spear1310-evb.dts
@@ -106,6 +106,10 @@
status = "okay";
};
+ miphy at eb800000 {
+ status = "okay";
+ };
+
cf at b2800000 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index 122ae94..64e7dd5 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -29,24 +29,57 @@
#gpio-cells = <2>;
};
- ahci at b1000000 {
+ miphy0: miphy at eb800000 {
+ compatible = "st,miphy", "st,spear1310-miphy";
+ reg = <0xeb800000 0x4000>;
+ misc = <&misc>;
+ phy-id = <0>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
+ miphy1: miphy at eb804000 {
+ compatible = "st,miphy", "st,spear1310-miphy";
+ reg = <0xeb804000 0x4000>;
+ misc = <&misc>;
+ phy-id = <1>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
+ miphy2: miphy at eb808000 {
+ compatible = "st,miphy", "st,spear1310-miphy";
+ reg = <0xeb808000 0x4000>;
+ misc = <&misc>;
+ phy-id = <2>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
+ ahci0: ahci at b1000000 {
compatible = "snps,spear-ahci";
reg = <0xb1000000 0x10000>;
interrupts = <0 68 0x4>;
+ phys = <&miphy0 0>;
+ phy-names = "sata-phy";
status = "disabled";
};
- ahci at b1800000 {
+ ahci1: ahci at b1800000 {
compatible = "snps,spear-ahci";
reg = <0xb1800000 0x10000>;
interrupts = <0 69 0x4>;
+ phys = <&miphy1 0>;
+ phy-names = "sata-phy";
status = "disabled";
};
- ahci at b4000000 {
+ ahci2: ahci at b4000000 {
compatible = "snps,spear-ahci";
reg = <0xb4000000 0x10000>;
interrupts = <0 70 0x4>;
+ phys = <&miphy2 0>;
+ phy-names = "sata-phy";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
index d6c30ae..b23e05e 100644
--- a/arch/arm/boot/dts/spear1340-evb.dts
+++ b/arch/arm/boot/dts/spear1340-evb.dts
@@ -122,6 +122,10 @@
status = "okay";
};
+ miphy at eb800000 {
+ status = "okay";
+ };
+
dma at ea800000 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index 54d128d..7e3a04b 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -31,10 +31,21 @@
status = "disabled";
};
- ahci at b1000000 {
+ miphy0: miphy at eb800000 {
+ compatible = "st,miphy", "st,spear1340-miphy";
+ reg = <0xeb800000 0x4000>;
+ misc = <&misc>;
+ phy-id = <0>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
+ ahci0: ahci at b1000000 {
compatible = "snps,spear-ahci";
reg = <0xb1000000 0x10000>;
interrupts = <0 72 0x4>;
+ phys = <&miphy0 0>;
+ phy-names = "sata-phy";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 4382547..3a72508 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -220,6 +220,11 @@
0xd8000000 0xd8000000 0x01000000
0xe0000000 0xe0000000 0x10000000>;
+ misc: syscon at e0700000 {
+ compatible = "st,spear1340-misc", "syscon";
+ reg = <0xe0700000 0x1000>;
+ };
+
gpio0: gpio at e0600000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xe0600000 0x1000>;
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
index ac1710e..7e7f1b0 100644
--- a/arch/arm/mach-spear/Kconfig
+++ b/arch/arm/mach-spear/Kconfig
@@ -26,6 +26,8 @@ config ARCH_SPEAR13XX
select MIGHT_HAVE_CACHE_L2X0
select PINCTRL
select USE_OF
+ select MFD_SYSCON
+ select PHY_ST_MIPHY40LP
help
Supports for ARM's SPEAR13XX family
diff --git a/arch/arm/mach-spear/spear1340.c b/arch/arm/mach-spear/spear1340.c
index 3fb6834..8e27093 100644
--- a/arch/arm/mach-spear/spear1340.c
+++ b/arch/arm/mach-spear/spear1340.c
@@ -11,138 +11,13 @@
* warranty of any kind, whether express or implied.
*/
-#define pr_fmt(fmt) "SPEAr1340: " fmt
-
-#include <linux/ahci_platform.h>
-#include <linux/amba/serial.h>
-#include <linux/delay.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include "generic.h"
-#include <mach/spear.h>
-
-/* FIXME: Move SATA PHY code into a standalone driver */
-
-/* Base addresses */
-#define SPEAR1340_SATA_BASE UL(0xB1000000)
-
-/* Power Management Registers */
-#define SPEAR1340_PCM_CFG (VA_MISC_BASE + 0x100)
-#define SPEAR1340_PCM_WKUP_CFG (VA_MISC_BASE + 0x104)
-#define SPEAR1340_SWITCH_CTR (VA_MISC_BASE + 0x108)
-
-#define SPEAR1340_PERIP1_SW_RST (VA_MISC_BASE + 0x318)
-#define SPEAR1340_PERIP2_SW_RST (VA_MISC_BASE + 0x31C)
-#define SPEAR1340_PERIP3_SW_RST (VA_MISC_BASE + 0x320)
-
-/* PCIE - SATA configuration registers */
-#define SPEAR1340_PCIE_SATA_CFG (VA_MISC_BASE + 0x424)
- /* PCIE CFG MASks */
- #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11)
- #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10)
- #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9)
- #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8)
- #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4)
- #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3)
- #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2)
- #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1)
- #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
- #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
- #define SPEAR1340_SATA_PCIE_CFG_MASK 0xF1F
- #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
- SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
- SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
- SPEAR1340_PCIE_CFG_POWERUP_RESET | \
- SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
- #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
- SPEAR1340_SATA_CFG_PM_CLK_EN | \
- SPEAR1340_SATA_CFG_POWERUP_RESET | \
- SPEAR1340_SATA_CFG_RX_CLK_EN | \
- SPEAR1340_SATA_CFG_TX_CLK_EN)
-
-#define SPEAR1340_PCIE_MIPHY_CFG (VA_MISC_BASE + 0x428)
- #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31)
- #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27)
- #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
- #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
- #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
- #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
- (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
- SPEAR1340_MIPHY_CLK_REF_DIV2 | \
- SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
- #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
- (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
- #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
- (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
- SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
-
-/* SATA device registration */
-static int sata_miphy_init(struct device *dev, void __iomem *addr)
-{
- writel(SPEAR1340_SATA_CFG_VAL, SPEAR1340_PCIE_SATA_CFG);
- writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK,
- SPEAR1340_PCIE_MIPHY_CFG);
- /* Switch on sata power domain */
- writel((readl(SPEAR1340_PCM_CFG) | (0x800)), SPEAR1340_PCM_CFG);
- msleep(20);
- /* Disable PCIE SATA Controller reset */
- writel((readl(SPEAR1340_PERIP1_SW_RST) & (~0x1000)),
- SPEAR1340_PERIP1_SW_RST);
- msleep(20);
-
- return 0;
-}
-
-void sata_miphy_exit(struct device *dev)
-{
- writel(0, SPEAR1340_PCIE_SATA_CFG);
- writel(0, SPEAR1340_PCIE_MIPHY_CFG);
-
- /* Enable PCIE SATA Controller reset */
- writel((readl(SPEAR1340_PERIP1_SW_RST) | (0x1000)),
- SPEAR1340_PERIP1_SW_RST);
- msleep(20);
- /* Switch off sata power domain */
- writel((readl(SPEAR1340_PCM_CFG) & (~0x800)), SPEAR1340_PCM_CFG);
- msleep(20);
-}
-
-int sata_suspend(struct device *dev)
-{
- if (dev->power.power_state.event == PM_EVENT_FREEZE)
- return 0;
-
- sata_miphy_exit(dev);
-
- return 0;
-}
-
-int sata_resume(struct device *dev)
-{
- if (dev->power.power_state.event == PM_EVENT_THAW)
- return 0;
-
- return sata_miphy_init(dev, NULL);
-}
-
-static struct ahci_platform_data sata_pdata = {
- .init = sata_miphy_init,
- .exit = sata_miphy_exit,
- .suspend = sata_suspend,
- .resume = sata_resume,
-};
-
-/* Add SPEAr1340 auxdata to pass platform data */
-static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
- OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL,
- &sata_pdata),
- {}
-};
static void __init spear1340_dt_init(void)
{
- of_platform_populate(NULL, of_default_bus_match_table,
- spear1340_auxdata_lookup, NULL);
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static const char * const spear1340_dt_board_compat[] = {
diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
index 98859ff..16da55b 100644
--- a/drivers/phy/phy-miphy40lp.c
+++ b/drivers/phy/phy-miphy40lp.c
@@ -8,8 +8,10 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
+ * 04/02/2014: Adding support of SATA mode for SPEAr1340.
*/
+#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/kernel.h>
@@ -19,6 +21,60 @@
#include <linux/phy/phy.h>
#include <linux/regmap.h>
+/* SPEAr1340 Registers */
+/* Power Management Registers */
+#define SPEAR1340_PCM_CFG 0x100
+ #define SPEAR1340_PCM_CFG_SATA_POWER_EN BIT(11)
+#define SPEAR1340_PCM_WKUP_CFG 0x104
+#define SPEAR1340_SWITCH_CTR 0x108
+
+#define SPEAR1340_PERIP1_SW_RST 0x318
+ #define SPEAR1340_PERIP1_SW_RSATA BIT(12)
+#define SPEAR1340_PERIP2_SW_RST 0x31C
+#define SPEAR1340_PERIP3_SW_RST 0x320
+
+/* PCIE - SATA configuration registers */
+#define SPEAR1340_PCIE_SATA_CFG 0x424
+ /* PCIE CFG MASks */
+ #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT BIT(11)
+ #define SPEAR1340_PCIE_CFG_POWERUP_RESET BIT(10)
+ #define SPEAR1340_PCIE_CFG_CORE_CLK_EN BIT(9)
+ #define SPEAR1340_PCIE_CFG_AUX_CLK_EN BIT(8)
+ #define SPEAR1340_SATA_CFG_TX_CLK_EN BIT(4)
+ #define SPEAR1340_SATA_CFG_RX_CLK_EN BIT(3)
+ #define SPEAR1340_SATA_CFG_POWERUP_RESET BIT(2)
+ #define SPEAR1340_SATA_CFG_PM_CLK_EN BIT(1)
+ #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
+ #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
+ #define SPEAR1340_PCIE_SATA_CFG_MASK 0xF1F
+ #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
+ SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
+ SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
+ SPEAR1340_PCIE_CFG_POWERUP_RESET | \
+ SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
+ #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
+ SPEAR1340_SATA_CFG_PM_CLK_EN | \
+ SPEAR1340_SATA_CFG_POWERUP_RESET | \
+ SPEAR1340_SATA_CFG_RX_CLK_EN | \
+ SPEAR1340_SATA_CFG_TX_CLK_EN)
+
+#define SPEAR1340_PCIE_MIPHY_CFG 0x428
+ #define SPEAR1340_MIPHY_OSC_BYPASS_EXT BIT(31)
+ #define SPEAR1340_MIPHY_CLK_REF_DIV2 BIT(27)
+ #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
+ #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
+ #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
+ #define SPEAR1340_PCIE_MIPHY_CFG_MASK 0xF80000FF
+ #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
+ (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+ SPEAR1340_MIPHY_CLK_REF_DIV2 | \
+ SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
+ #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
+ (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
+ #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
+ (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+ SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
+
enum phy_mode {
SATA,
PCIE,
@@ -50,6 +106,93 @@ struct miphy40lp_priv {
const struct miphy40lp_plat_ops *plat_ops;
};
+static int miphy40lp_spear1340_sata_init(struct miphy40lp_priv *priv)
+{
+ regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
+ SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
+ regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+ SPEAR1340_PCIE_MIPHY_CFG_MASK,
+ SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
+ /* Switch on sata power domain */
+ regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG,
+ SPEAR1340_PCM_CFG_SATA_POWER_EN,
+ SPEAR1340_PCM_CFG_SATA_POWER_EN);
+ msleep(20);
+ /* Disable PCIE SATA Controller reset */
+ regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST,
+ SPEAR1340_PERIP1_SW_RSATA, 0);
+ msleep(20);
+
+ return 0;
+}
+
+static int miphy40lp_spear1340_sata_exit(struct miphy40lp_priv *priv)
+{
+ regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
+ SPEAR1340_PCIE_SATA_CFG_MASK, 0);
+ regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+ SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
+
+ /* Enable PCIE SATA Controller reset */
+ regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST,
+ SPEAR1340_PERIP1_SW_RSATA,
+ SPEAR1340_PERIP1_SW_RSATA);
+ msleep(20);
+ /* Switch off sata power domain */
+ regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG,
+ SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
+ msleep(20);
+
+ return 0;
+}
+
+static int miphy40lp_spear1340_init(struct miphy40lp_priv *priv)
+{
+ int ret = 0;
+
+ if (priv->mode == SATA)
+ ret = miphy40lp_spear1340_sata_init(priv);
+
+ return ret;
+}
+
+static int miphy40lp_spear1340_exit(struct miphy40lp_priv *priv)
+{
+ int ret = 0;
+
+ if (priv->mode == SATA)
+ ret = miphy40lp_spear1340_sata_exit(priv);
+
+ return ret;
+}
+
+static int miphy40lp_spear1340_suspend(struct miphy40lp_priv *priv)
+{
+ int ret = 0;
+
+ if (priv->mode == SATA)
+ ret = miphy40lp_spear1340_sata_exit(priv);
+
+ return ret;
+}
+
+static int miphy40lp_spear1340_resume(struct miphy40lp_priv *priv)
+{
+ int ret = 0;
+
+ if (priv->mode == SATA)
+ ret = miphy40lp_spear1340_sata_init(priv);
+
+ return ret;
+}
+
+static struct miphy40lp_plat_ops spear1340_phy_ops = {
+ .plat_init = miphy40lp_spear1340_init,
+ .plat_exit = miphy40lp_spear1340_exit,
+ .plat_suspend = miphy40lp_spear1340_suspend,
+ .plat_resume = miphy40lp_spear1340_resume,
+};
+
static int miphy40lp_init(struct phy *phy)
{
struct miphy40lp_priv *priv = phy_get_drvdata(phy);
@@ -100,6 +243,7 @@ static int miphy40lp_power_on(struct phy *phy)
static const struct of_device_id miphy40lp_of_match[] = {
{ .compatible = "st,miphy40lp-phy", .data = NULL },
+ { .compatible = "st,spear1340-miphy", .data = &spear1340_phy_ops },
{ },
};
MODULE_DEVICE_TABLE(of, miphy40lp_of_match);
--
1.7.0.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH V6 07/12] phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
2014-02-11 9:29 [PATCH V6 00/12]PCI:Add SPEAr13xx PCie support Mohit Kumar
` (2 preceding siblings ...)
2014-02-11 9:30 ` [PATCH V6 06/12] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver Mohit Kumar
@ 2014-02-11 9:30 ` Mohit Kumar
2014-02-11 12:06 ` Kishon Vijay Abraham I
2014-02-11 9:30 ` [PATCH V6 09/12] SPEAr13XX: dts: Add PCIe node information Mohit Kumar
2014-02-11 9:30 ` [PATCH V6 11/12] SPEAr13xx: defconfig: Update Mohit Kumar
5 siblings, 1 reply; 10+ messages in thread
From: Mohit Kumar @ 2014-02-11 9:30 UTC (permalink / raw)
To: linux-arm-kernel
From: Pratyush Anand <pratyush.anand@st.com>
SPEAr1310 and SPEAr1340 uses miphy40lp phy for PCIe. This driver adds
support for the same.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Tested-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: spear-devel at list.st.com
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
drivers/phy/phy-miphy40lp.c | 165 +++++++++++++++++++++++++++++++++++++++++++
1 files changed, 165 insertions(+), 0 deletions(-)
diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
index 16da55b..dec67ed 100644
--- a/drivers/phy/phy-miphy40lp.c
+++ b/drivers/phy/phy-miphy40lp.c
@@ -9,6 +9,7 @@
* published by the Free Software Foundation.
*
* 04/02/2014: Adding support of SATA mode for SPEAr1340.
+ * 04/02/2014: Adding support of PCIe mode for SPEAr1340 and SPEAr1310
*/
#include <linux/bitops.h>
@@ -74,6 +75,80 @@
#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
+/* SPEAr1310 Registers */
+#define SPEAR1310_PCIE_SATA_CFG 0x3A4
+ #define SPEAR1310_PCIE_SATA2_SEL_PCIE (0 << 31)
+ #define SPEAR1310_PCIE_SATA1_SEL_PCIE (0 << 30)
+ #define SPEAR1310_PCIE_SATA0_SEL_PCIE (0 << 29)
+ #define SPEAR1310_PCIE_SATA2_SEL_SATA BIT(31)
+ #define SPEAR1310_PCIE_SATA1_SEL_SATA BIT(30)
+ #define SPEAR1310_PCIE_SATA0_SEL_SATA BIT(29)
+ #define SPEAR1310_SATA2_CFG_TX_CLK_EN BIT(27)
+ #define SPEAR1310_SATA2_CFG_RX_CLK_EN BIT(26)
+ #define SPEAR1310_SATA2_CFG_POWERUP_RESET BIT(25)
+ #define SPEAR1310_SATA2_CFG_PM_CLK_EN BIT(24)
+ #define SPEAR1310_SATA1_CFG_TX_CLK_EN BIT(23)
+ #define SPEAR1310_SATA1_CFG_RX_CLK_EN BIT(22)
+ #define SPEAR1310_SATA1_CFG_POWERUP_RESET BIT(21)
+ #define SPEAR1310_SATA1_CFG_PM_CLK_EN BIT(20)
+ #define SPEAR1310_SATA0_CFG_TX_CLK_EN BIT(19)
+ #define SPEAR1310_SATA0_CFG_RX_CLK_EN BIT(18)
+ #define SPEAR1310_SATA0_CFG_POWERUP_RESET BIT(17)
+ #define SPEAR1310_SATA0_CFG_PM_CLK_EN BIT(16)
+ #define SPEAR1310_PCIE2_CFG_DEVICE_PRESENT BIT(11)
+ #define SPEAR1310_PCIE2_CFG_POWERUP_RESET BIT(10)
+ #define SPEAR1310_PCIE2_CFG_CORE_CLK_EN BIT(9)
+ #define SPEAR1310_PCIE2_CFG_AUX_CLK_EN BIT(8)
+ #define SPEAR1310_PCIE1_CFG_DEVICE_PRESENT BIT(7)
+ #define SPEAR1310_PCIE1_CFG_POWERUP_RESET BIT(6)
+ #define SPEAR1310_PCIE1_CFG_CORE_CLK_EN BIT(5)
+ #define SPEAR1310_PCIE1_CFG_AUX_CLK_EN BIT(4)
+ #define SPEAR1310_PCIE0_CFG_DEVICE_PRESENT BIT(3)
+ #define SPEAR1310_PCIE0_CFG_POWERUP_RESET BIT(2)
+ #define SPEAR1310_PCIE0_CFG_CORE_CLK_EN BIT(1)
+ #define SPEAR1310_PCIE0_CFG_AUX_CLK_EN BIT(0)
+
+ #define SPEAR1310_PCIE_CFG_MASK(x) ((0xF << (x * 4)) | BIT((x + 29)))
+ #define SPEAR1310_SATA_CFG_MASK(x) ((0xF << (x * 4 + 16)) | \
+ BIT((x + 29)))
+ #define SPEAR1310_PCIE_CFG_VAL(x) \
+ (SPEAR1310_PCIE_SATA##x##_SEL_PCIE | \
+ SPEAR1310_PCIE##x##_CFG_AUX_CLK_EN | \
+ SPEAR1310_PCIE##x##_CFG_CORE_CLK_EN | \
+ SPEAR1310_PCIE##x##_CFG_POWERUP_RESET | \
+ SPEAR1310_PCIE##x##_CFG_DEVICE_PRESENT)
+ #define SPEAR1310_SATA_CFG_VAL(x) \
+ (SPEAR1310_PCIE_SATA##x##_SEL_SATA | \
+ SPEAR1310_SATA##x##_CFG_PM_CLK_EN | \
+ SPEAR1310_SATA##x##_CFG_POWERUP_RESET | \
+ SPEAR1310_SATA##x##_CFG_RX_CLK_EN | \
+ SPEAR1310_SATA##x##_CFG_TX_CLK_EN)
+
+#define SPEAR1310_PCIE_MIPHY_CFG_1 0x3A8
+ #define SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT BIT(31)
+ #define SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 BIT(28)
+ #define SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(x) (x << 16)
+ #define SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT BIT(15)
+ #define SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 BIT(12)
+ #define SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(x) (x << 0)
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_MASK (0xFFFF)
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK (0xFFFF << 16)
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA \
+ (SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
+ SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 | \
+ SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(60) | \
+ SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
+ SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 | \
+ SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(60))
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
+ (SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(120))
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE \
+ (SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
+ SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(25) | \
+ SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
+ SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(25))
+
+#define SPEAR1310_PCIE_MIPHY_CFG_2 0x3AC
enum phy_mode {
SATA,
@@ -146,12 +221,35 @@ static int miphy40lp_spear1340_sata_exit(struct miphy40lp_priv *priv)
return 0;
}
+static int miphy40lp_spear1340_pcie_init(struct miphy40lp_priv *priv)
+{
+ regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+ SPEAR1340_PCIE_MIPHY_CFG_MASK,
+ SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE);
+ regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
+ SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_PCIE_CFG_VAL);
+
+ return 0;
+}
+
+static int miphy40lp_spear1340_pcie_exit(struct miphy40lp_priv *priv)
+{
+ regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+ SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
+ regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
+ SPEAR1340_PCIE_SATA_CFG_MASK, 0);
+
+ return 0;
+}
+
static int miphy40lp_spear1340_init(struct miphy40lp_priv *priv)
{
int ret = 0;
if (priv->mode == SATA)
ret = miphy40lp_spear1340_sata_init(priv);
+ else if (priv->mode == PCIE)
+ ret = miphy40lp_spear1340_pcie_init(priv);
return ret;
}
@@ -162,6 +260,8 @@ static int miphy40lp_spear1340_exit(struct miphy40lp_priv *priv)
if (priv->mode == SATA)
ret = miphy40lp_spear1340_sata_exit(priv);
+ else if (priv->mode == PCIE)
+ ret = miphy40lp_spear1340_pcie_exit(priv);
return ret;
}
@@ -193,6 +293,70 @@ static struct miphy40lp_plat_ops spear1340_phy_ops = {
.plat_resume = miphy40lp_spear1340_resume,
};
+static int miphy40lp_spear1310_pcie_init(struct miphy40lp_priv *priv)
+{
+ u32 val;
+
+ regmap_update_bits(priv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
+ SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK,
+ SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE);
+
+ switch (priv->id) {
+ case 0:
+ val = SPEAR1310_PCIE_CFG_VAL(0);
+ break;
+ case 1:
+ val = SPEAR1310_PCIE_CFG_VAL(1);
+ break;
+ case 2:
+ val = SPEAR1310_PCIE_CFG_VAL(2);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(priv->misc, SPEAR1310_PCIE_SATA_CFG,
+ SPEAR1310_PCIE_CFG_MASK(priv->id), val);
+
+ return 0;
+}
+
+static int miphy40lp_spear1310_pcie_exit(struct miphy40lp_priv *priv)
+{
+ regmap_update_bits(priv->misc, SPEAR1310_PCIE_SATA_CFG,
+ SPEAR1310_PCIE_CFG_MASK(priv->id), 0);
+
+ regmap_update_bits(priv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
+ SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK, 0);
+
+ return 0;
+}
+
+static int miphy40lp_spear1310_init(struct miphy40lp_priv *priv)
+{
+ int ret = 0;
+
+ if (priv->mode == PCIE)
+ ret = miphy40lp_spear1310_pcie_init(priv);
+
+ return ret;
+}
+
+static int miphy40lp_spear1310_exit(struct miphy40lp_priv *priv)
+{
+ int ret = 0;
+
+ if (priv->mode == PCIE)
+ ret = miphy40lp_spear1310_pcie_exit(priv);
+
+ return ret;
+}
+
+static struct miphy40lp_plat_ops spear1310_phy_ops = {
+ .plat_init = miphy40lp_spear1310_init,
+ .plat_exit = miphy40lp_spear1310_exit,
+};
+
static int miphy40lp_init(struct phy *phy)
{
struct miphy40lp_priv *priv = phy_get_drvdata(phy);
@@ -244,6 +408,7 @@ static int miphy40lp_power_on(struct phy *phy)
static const struct of_device_id miphy40lp_of_match[] = {
{ .compatible = "st,miphy40lp-phy", .data = NULL },
{ .compatible = "st,spear1340-miphy", .data = &spear1340_phy_ops },
+ { .compatible = "st,spear1310-miphy", .data = &spear1310_phy_ops },
{ },
};
MODULE_DEVICE_TABLE(of, miphy40lp_of_match);
--
1.7.0.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH V6 09/12] SPEAr13XX: dts: Add PCIe node information
2014-02-11 9:29 [PATCH V6 00/12]PCI:Add SPEAr13xx PCie support Mohit Kumar
` (3 preceding siblings ...)
2014-02-11 9:30 ` [PATCH V6 07/12] phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support Mohit Kumar
@ 2014-02-11 9:30 ` Mohit Kumar
2014-02-11 9:30 ` [PATCH V6 11/12] SPEAr13xx: defconfig: Update Mohit Kumar
5 siblings, 0 replies; 10+ messages in thread
From: Mohit Kumar @ 2014-02-11 9:30 UTC (permalink / raw)
To: linux-arm-kernel
From: Pratyush Anand <pratyush.anand@st.com>
SPEAr1310 and SPEAr1340 supports 3 and 1 PCIe controller respectively.
These controllers are based on synopsis designware controller.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: spear-devel at list.st.com
Cc: linux-arm-kernel at lists.infradead.org
---
arch/arm/boot/dts/spear1310.dtsi | 48 ++++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/spear1340.dtsi | 16 ++++++++++++
2 files changed, 64 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index 64e7dd5..136a12d 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -83,6 +83,54 @@
status = "disabled";
};
+ pcie0: pcie at b1000000 {
+ compatible = "st,spear1340-pcie", "snps,dw-pcie";
+ reg = <0xb1000000 0x4000>;
+ interrupts = <0 68 0x4>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0x0 0 &gic 68>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */
+ 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
+ status = "disabled";
+ };
+
+ pcie1: pcie at b1800000 {
+ compatible = "st,spear1340-pcie", "snps,dw-pcie";
+ reg = <0xb1800000 0x4000>;
+ interrupts = <0 69 0x4>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0x0 0 &gic 69>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x00000800 0 0x90000000 0x90000000 0 0x00020000 /* configuration space */
+ 0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */
+ status = "disabled";
+ };
+
+ pcie2: pcie at b4000000 {
+ compatible = "st,spear1340-pcie", "snps,dw-pcie";
+ reg = <0xb4000000 0x4000>;
+ interrupts = <0 70 0x4>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0x0 0 &gic 70>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x00000800 0 0xc0000000 0xc0000000 0 0x00020000 /* configuration space */
+ 0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
+ status = "disabled";
+ };
+
gmac1: eth at 5c400000 {
compatible = "st,spear600-gmac";
reg = <0x5c400000 0x8000>;
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index 7e3a04b..65a689c 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -49,6 +49,22 @@
status = "disabled";
};
+ pcie0: pcie at b1000000 {
+ compatible = "st,spear1340-pcie", "snps,dw-pcie";
+ reg = <0xb1000000 0x4000>;
+ interrupts = <0 68 0x4>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0x0 0 &gic 68>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */
+ 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
+ status = "disabled";
+ };
+
i2s-play at b2400000 {
compatible = "snps,designware-i2s";
reg = <0xb2400000 0x10000>;
--
1.7.0.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH V6 11/12] SPEAr13xx: defconfig: Update
2014-02-11 9:29 [PATCH V6 00/12]PCI:Add SPEAr13xx PCie support Mohit Kumar
` (4 preceding siblings ...)
2014-02-11 9:30 ` [PATCH V6 09/12] SPEAr13XX: dts: Add PCIe node information Mohit Kumar
@ 2014-02-11 9:30 ` Mohit Kumar
5 siblings, 0 replies; 10+ messages in thread
From: Mohit Kumar @ 2014-02-11 9:30 UTC (permalink / raw)
To: linux-arm-kernel
Enable PCIe, EABI, VFP and NFS configs in default configuration file for
SPEAr13xx.
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: spear-devel at list.st.com
Cc: linux-arm-kernel at lists.infradead.org
---
arch/arm/configs/spear13xx_defconfig | 16 ++++++++++++++++
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig
index 82eaa55..d271b26 100644
--- a/arch/arm/configs/spear13xx_defconfig
+++ b/arch/arm/configs/spear13xx_defconfig
@@ -11,13 +11,24 @@ CONFIG_ARCH_SPEAR13XX=y
CONFIG_MACH_SPEAR1310=y
CONFIG_MACH_SPEAR1340=y
# CONFIG_SWP_EMULATE is not set
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCIE_SPEAR13XX=y
CONFIG_SMP=y
# CONFIG_SMP_ON_UP is not set
# CONFIG_ARM_CPU_TOPOLOGY is not set
+CONFIG_AEABI=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_VFP=y
CONFIG_BINFMT_MISC=y
CONFIG_NET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_NET_IPIP=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_OF_PARTS=y
@@ -27,6 +38,7 @@ CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_FSMC=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_BLK_DEV_SD=y
CONFIG_ATA=y
# CONFIG_SATA_PMP is not set
CONFIG_SATA_AHCI_PLATFORM=y
@@ -66,6 +78,7 @@ CONFIG_USB=y
# CONFIG_USB_DEVICE_CLASS is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SPEAR=y
@@ -79,11 +92,14 @@ CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_SECURITY=y
CONFIG_AUTOFS4_FS=m
+CONFIG_FUSE_FS=y
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=m
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=m
--
1.7.0.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH V6 06/12] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
2014-02-11 9:30 ` [PATCH V6 06/12] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver Mohit Kumar
@ 2014-02-11 11:35 ` Kishon Vijay Abraham I
0 siblings, 0 replies; 10+ messages in thread
From: Kishon Vijay Abraham I @ 2014-02-11 11:35 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Tuesday 11 February 2014 03:00 PM, Mohit Kumar wrote:
> From: Pratyush Anand <pratyush.anand@st.com>
>
> ahci driver needs some platform specific functions which are called at
> init, exit, suspend and resume conditions. Till now these functions were
> present in a platform driver with a fixme notes.
>
> Similar functions modifying same set of registers will also be needed in
> case of PCIe phy init/exit.
>
> So move all these SATA platform code to phy-miphy40lp driver.
>
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Tested-by: Mohit Kumar <mohit.kumar@st.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Viresh Kumar <viresh.linux@gmail.com>
> Cc: Tejun Heo <tj@kernel.org>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Cc: spear-devel at list.st.com
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> ---
> arch/arm/boot/dts/spear1310-evb.dts | 4 +
> arch/arm/boot/dts/spear1310.dtsi | 39 +++++++++-
> arch/arm/boot/dts/spear1340-evb.dts | 4 +
> arch/arm/boot/dts/spear1340.dtsi | 13 +++-
> arch/arm/boot/dts/spear13xx.dtsi | 5 +
> arch/arm/mach-spear/Kconfig | 2 +
> arch/arm/mach-spear/spear1340.c | 127 +------------------------------
> drivers/phy/phy-miphy40lp.c | 144 +++++++++++++++++++++++++++++++++++
> 8 files changed, 208 insertions(+), 130 deletions(-)
>
> diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
> index b56a801..d42c84b 100644
> --- a/arch/arm/boot/dts/spear1310-evb.dts
> +++ b/arch/arm/boot/dts/spear1310-evb.dts
> @@ -106,6 +106,10 @@
> status = "okay";
> };
>
> + miphy at eb800000 {
> + status = "okay";
> + };
> +
> cf at b2800000 {
> status = "okay";
> };
> diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
> index 122ae94..64e7dd5 100644
> --- a/arch/arm/boot/dts/spear1310.dtsi
> +++ b/arch/arm/boot/dts/spear1310.dtsi
> @@ -29,24 +29,57 @@
> #gpio-cells = <2>;
> };
>
> - ahci at b1000000 {
> + miphy0: miphy at eb800000 {
> + compatible = "st,miphy", "st,spear1310-miphy";
> + reg = <0xeb800000 0x4000>;
> + misc = <&misc>;
> + phy-id = <0>;
> + #phy-cells = <1>;
> + status = "disabled";
> + };
> +
> + miphy1: miphy at eb804000 {
> + compatible = "st,miphy", "st,spear1310-miphy";
> + reg = <0xeb804000 0x4000>;
> + misc = <&misc>;
> + phy-id = <1>;
> + #phy-cells = <1>;
> + status = "disabled";
> + };
> +
> + miphy2: miphy at eb808000 {
> + compatible = "st,miphy", "st,spear1310-miphy";
> + reg = <0xeb808000 0x4000>;
> + misc = <&misc>;
> + phy-id = <2>;
> + #phy-cells = <1>;
> + status = "disabled";
> + };
> +
> + ahci0: ahci at b1000000 {
> compatible = "snps,spear-ahci";
> reg = <0xb1000000 0x10000>;
> interrupts = <0 68 0x4>;
> + phys = <&miphy0 0>;
> + phy-names = "sata-phy";
> status = "disabled";
> };
>
> - ahci at b1800000 {
> + ahci1: ahci at b1800000 {
> compatible = "snps,spear-ahci";
> reg = <0xb1800000 0x10000>;
> interrupts = <0 69 0x4>;
> + phys = <&miphy1 0>;
> + phy-names = "sata-phy";
> status = "disabled";
> };
>
> - ahci at b4000000 {
> + ahci2: ahci at b4000000 {
> compatible = "snps,spear-ahci";
> reg = <0xb4000000 0x10000>;
> interrupts = <0 70 0x4>;
> + phys = <&miphy2 0>;
> + phy-names = "sata-phy";
> status = "disabled";
> };
>
> diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
> index d6c30ae..b23e05e 100644
> --- a/arch/arm/boot/dts/spear1340-evb.dts
> +++ b/arch/arm/boot/dts/spear1340-evb.dts
> @@ -122,6 +122,10 @@
> status = "okay";
> };
>
> + miphy at eb800000 {
> + status = "okay";
> + };
> +
> dma at ea800000 {
> status = "okay";
> };
> diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
> index 54d128d..7e3a04b 100644
> --- a/arch/arm/boot/dts/spear1340.dtsi
> +++ b/arch/arm/boot/dts/spear1340.dtsi
> @@ -31,10 +31,21 @@
> status = "disabled";
> };
>
> - ahci at b1000000 {
> + miphy0: miphy at eb800000 {
> + compatible = "st,miphy", "st,spear1340-miphy";
> + reg = <0xeb800000 0x4000>;
> + misc = <&misc>;
> + phy-id = <0>;
> + #phy-cells = <1>;
> + status = "disabled";
> + };
> +
> + ahci0: ahci at b1000000 {
> compatible = "snps,spear-ahci";
> reg = <0xb1000000 0x10000>;
> interrupts = <0 72 0x4>;
> + phys = <&miphy0 0>;
> + phy-names = "sata-phy";
> status = "disabled";
> };
>
> diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
> index 4382547..3a72508 100644
> --- a/arch/arm/boot/dts/spear13xx.dtsi
> +++ b/arch/arm/boot/dts/spear13xx.dtsi
> @@ -220,6 +220,11 @@
> 0xd8000000 0xd8000000 0x01000000
> 0xe0000000 0xe0000000 0x10000000>;
>
> + misc: syscon at e0700000 {
> + compatible = "st,spear1340-misc", "syscon";
> + reg = <0xe0700000 0x1000>;
> + };
> +
> gpio0: gpio at e0600000 {
> compatible = "arm,pl061", "arm,primecell";
> reg = <0xe0600000 0x1000>;
> diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
> index ac1710e..7e7f1b0 100644
> --- a/arch/arm/mach-spear/Kconfig
> +++ b/arch/arm/mach-spear/Kconfig
> @@ -26,6 +26,8 @@ config ARCH_SPEAR13XX
> select MIGHT_HAVE_CACHE_L2X0
> select PINCTRL
> select USE_OF
> + select MFD_SYSCON
> + select PHY_ST_MIPHY40LP
> help
> Supports for ARM's SPEAR13XX family
>
> diff --git a/arch/arm/mach-spear/spear1340.c b/arch/arm/mach-spear/spear1340.c
> index 3fb6834..8e27093 100644
> --- a/arch/arm/mach-spear/spear1340.c
> +++ b/arch/arm/mach-spear/spear1340.c
> @@ -11,138 +11,13 @@
> * warranty of any kind, whether express or implied.
> */
>
> -#define pr_fmt(fmt) "SPEAr1340: " fmt
> -
> -#include <linux/ahci_platform.h>
> -#include <linux/amba/serial.h>
> -#include <linux/delay.h>
> #include <linux/of_platform.h>
> #include <asm/mach/arch.h>
> #include "generic.h"
> -#include <mach/spear.h>
> -
> -/* FIXME: Move SATA PHY code into a standalone driver */
> -
> -/* Base addresses */
> -#define SPEAR1340_SATA_BASE UL(0xB1000000)
> -
> -/* Power Management Registers */
> -#define SPEAR1340_PCM_CFG (VA_MISC_BASE + 0x100)
> -#define SPEAR1340_PCM_WKUP_CFG (VA_MISC_BASE + 0x104)
> -#define SPEAR1340_SWITCH_CTR (VA_MISC_BASE + 0x108)
> -
> -#define SPEAR1340_PERIP1_SW_RST (VA_MISC_BASE + 0x318)
> -#define SPEAR1340_PERIP2_SW_RST (VA_MISC_BASE + 0x31C)
> -#define SPEAR1340_PERIP3_SW_RST (VA_MISC_BASE + 0x320)
> -
> -/* PCIE - SATA configuration registers */
> -#define SPEAR1340_PCIE_SATA_CFG (VA_MISC_BASE + 0x424)
> - /* PCIE CFG MASks */
> - #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11)
> - #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10)
> - #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9)
> - #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8)
> - #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4)
> - #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3)
> - #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2)
> - #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1)
> - #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
> - #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
> - #define SPEAR1340_SATA_PCIE_CFG_MASK 0xF1F
> - #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
> - SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
> - SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
> - SPEAR1340_PCIE_CFG_POWERUP_RESET | \
> - SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
> - #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
> - SPEAR1340_SATA_CFG_PM_CLK_EN | \
> - SPEAR1340_SATA_CFG_POWERUP_RESET | \
> - SPEAR1340_SATA_CFG_RX_CLK_EN | \
> - SPEAR1340_SATA_CFG_TX_CLK_EN)
> -
> -#define SPEAR1340_PCIE_MIPHY_CFG (VA_MISC_BASE + 0x428)
> - #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31)
> - #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27)
> - #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
> - #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
> - #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
> - #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
> - (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> - SPEAR1340_MIPHY_CLK_REF_DIV2 | \
> - SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
> - #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
> - (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
> - #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
> - (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> - SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
> -
> -/* SATA device registration */
> -static int sata_miphy_init(struct device *dev, void __iomem *addr)
> -{
> - writel(SPEAR1340_SATA_CFG_VAL, SPEAR1340_PCIE_SATA_CFG);
> - writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK,
> - SPEAR1340_PCIE_MIPHY_CFG);
> - /* Switch on sata power domain */
> - writel((readl(SPEAR1340_PCM_CFG) | (0x800)), SPEAR1340_PCM_CFG);
> - msleep(20);
> - /* Disable PCIE SATA Controller reset */
> - writel((readl(SPEAR1340_PERIP1_SW_RST) & (~0x1000)),
> - SPEAR1340_PERIP1_SW_RST);
> - msleep(20);
> -
> - return 0;
> -}
> -
> -void sata_miphy_exit(struct device *dev)
> -{
> - writel(0, SPEAR1340_PCIE_SATA_CFG);
> - writel(0, SPEAR1340_PCIE_MIPHY_CFG);
> -
> - /* Enable PCIE SATA Controller reset */
> - writel((readl(SPEAR1340_PERIP1_SW_RST) | (0x1000)),
> - SPEAR1340_PERIP1_SW_RST);
> - msleep(20);
> - /* Switch off sata power domain */
> - writel((readl(SPEAR1340_PCM_CFG) & (~0x800)), SPEAR1340_PCM_CFG);
> - msleep(20);
> -}
> -
> -int sata_suspend(struct device *dev)
> -{
> - if (dev->power.power_state.event == PM_EVENT_FREEZE)
> - return 0;
> -
> - sata_miphy_exit(dev);
> -
> - return 0;
> -}
> -
> -int sata_resume(struct device *dev)
> -{
> - if (dev->power.power_state.event == PM_EVENT_THAW)
> - return 0;
> -
> - return sata_miphy_init(dev, NULL);
> -}
> -
> -static struct ahci_platform_data sata_pdata = {
> - .init = sata_miphy_init,
> - .exit = sata_miphy_exit,
> - .suspend = sata_suspend,
> - .resume = sata_resume,
> -};
> -
> -/* Add SPEAr1340 auxdata to pass platform data */
> -static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
> - OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL,
> - &sata_pdata),
> - {}
> -};
>
> static void __init spear1340_dt_init(void)
> {
> - of_platform_populate(NULL, of_default_bus_match_table,
> - spear1340_auxdata_lookup, NULL);
> + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
> }
>
> static const char * const spear1340_dt_board_compat[] = {
> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> index 98859ff..16da55b 100644
> --- a/drivers/phy/phy-miphy40lp.c
> +++ b/drivers/phy/phy-miphy40lp.c
> @@ -8,8 +8,10 @@
> * it under the terms of the GNU General Public License version 2 as
> * published by the Free Software Foundation.
> *
> + * 04/02/2014: Adding support of SATA mode for SPEAr1340.
> */
>
> +#include <linux/bitops.h>
> #include <linux/delay.h>
> #include <linux/dma-mapping.h>
> #include <linux/kernel.h>
> @@ -19,6 +21,60 @@
> #include <linux/phy/phy.h>
> #include <linux/regmap.h>
>
> +/* SPEAr1340 Registers */
> +/* Power Management Registers */
> +#define SPEAR1340_PCM_CFG 0x100
> + #define SPEAR1340_PCM_CFG_SATA_POWER_EN BIT(11)
No tabs in the beginning. Just my personal preference though. No strong feelings.
> +#define SPEAR1340_PCM_WKUP_CFG 0x104
> +#define SPEAR1340_SWITCH_CTR 0x108
> +
> +#define SPEAR1340_PERIP1_SW_RST 0x318
> + #define SPEAR1340_PERIP1_SW_RSATA BIT(12)
> +#define SPEAR1340_PERIP2_SW_RST 0x31C
> +#define SPEAR1340_PERIP3_SW_RST 0x320
> +
> +/* PCIE - SATA configuration registers */
> +#define SPEAR1340_PCIE_SATA_CFG 0x424
> + /* PCIE CFG MASks */
> + #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT BIT(11)
> + #define SPEAR1340_PCIE_CFG_POWERUP_RESET BIT(10)
> + #define SPEAR1340_PCIE_CFG_CORE_CLK_EN BIT(9)
> + #define SPEAR1340_PCIE_CFG_AUX_CLK_EN BIT(8)
> + #define SPEAR1340_SATA_CFG_TX_CLK_EN BIT(4)
> + #define SPEAR1340_SATA_CFG_RX_CLK_EN BIT(3)
> + #define SPEAR1340_SATA_CFG_POWERUP_RESET BIT(2)
> + #define SPEAR1340_SATA_CFG_PM_CLK_EN BIT(1)
> + #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
> + #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
> + #define SPEAR1340_PCIE_SATA_CFG_MASK 0xF1F
> + #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
> + SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
> + SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
> + SPEAR1340_PCIE_CFG_POWERUP_RESET | \
> + SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
> + #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
> + SPEAR1340_SATA_CFG_PM_CLK_EN | \
> + SPEAR1340_SATA_CFG_POWERUP_RESET | \
> + SPEAR1340_SATA_CFG_RX_CLK_EN | \
> + SPEAR1340_SATA_CFG_TX_CLK_EN)
> +
> +#define SPEAR1340_PCIE_MIPHY_CFG 0x428
> + #define SPEAR1340_MIPHY_OSC_BYPASS_EXT BIT(31)
> + #define SPEAR1340_MIPHY_CLK_REF_DIV2 BIT(27)
> + #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
> + #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
This doesn't look very nice. But I'm not sure if there are similar macros to
handle sequence of bits.
> + #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
> + #define SPEAR1340_PCIE_MIPHY_CFG_MASK 0xF80000FF
> + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
> + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> + SPEAR1340_MIPHY_CLK_REF_DIV2 | \
> + SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
> + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
> + (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
> + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
> + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> + SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
> +
> enum phy_mode {
> SATA,
> PCIE,
> @@ -50,6 +106,93 @@ struct miphy40lp_priv {
> const struct miphy40lp_plat_ops *plat_ops;
> };
>
> +static int miphy40lp_spear1340_sata_init(struct miphy40lp_priv *priv)
> +{
> + regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
> + SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
> + regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> + SPEAR1340_PCIE_MIPHY_CFG_MASK,
> + SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
> + /* Switch on sata power domain */
> + regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG,
> + SPEAR1340_PCM_CFG_SATA_POWER_EN,
> + SPEAR1340_PCM_CFG_SATA_POWER_EN);
> + msleep(20);
> + /* Disable PCIE SATA Controller reset */
> + regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST,
> + SPEAR1340_PERIP1_SW_RSATA, 0);
> + msleep(20);
> +
> + return 0;
> +}
> +
> +static int miphy40lp_spear1340_sata_exit(struct miphy40lp_priv *priv)
> +{
> + regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
> + SPEAR1340_PCIE_SATA_CFG_MASK, 0);
> + regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> + SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
> +
> + /* Enable PCIE SATA Controller reset */
> + regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST,
> + SPEAR1340_PERIP1_SW_RSATA,
> + SPEAR1340_PERIP1_SW_RSATA);
> + msleep(20);
> + /* Switch off sata power domain */
> + regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG,
> + SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
> + msleep(20);
> +
> + return 0;
> +}
> +
> +static int miphy40lp_spear1340_init(struct miphy40lp_priv *priv)
> +{
> + int ret = 0;
> +
> + if (priv->mode == SATA)
> + ret = miphy40lp_spear1340_sata_init(priv);
> +
> + return ret;
> +}
> +
> +static int miphy40lp_spear1340_exit(struct miphy40lp_priv *priv)
> +{
> + int ret = 0;
> +
> + if (priv->mode == SATA)
> + ret = miphy40lp_spear1340_sata_exit(priv);
> +
> + return ret;
> +}
> +
> +static int miphy40lp_spear1340_suspend(struct miphy40lp_priv *priv)
> +{
> + int ret = 0;
> +
> + if (priv->mode == SATA)
> + ret = miphy40lp_spear1340_sata_exit(priv);
> +
> + return ret;
> +}
> +
> +static int miphy40lp_spear1340_resume(struct miphy40lp_priv *priv)
> +{
> + int ret = 0;
> +
> + if (priv->mode == SATA)
> + ret = miphy40lp_spear1340_sata_init(priv);
> +
> + return ret;
> +}
> +
> +static struct miphy40lp_plat_ops spear1340_phy_ops = {
> + .plat_init = miphy40lp_spear1340_init,
> + .plat_exit = miphy40lp_spear1340_exit,
> + .plat_suspend = miphy40lp_spear1340_suspend,
> + .plat_resume = miphy40lp_spear1340_resume,
> +};
> +
> static int miphy40lp_init(struct phy *phy)
> {
> struct miphy40lp_priv *priv = phy_get_drvdata(phy);
> @@ -100,6 +243,7 @@ static int miphy40lp_power_on(struct phy *phy)
>
> static const struct of_device_id miphy40lp_of_match[] = {
> { .compatible = "st,miphy40lp-phy", .data = NULL },
Do we still need this compatible? Because it doesn't do anything anyways?
Thanks
Kishon
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH V6 07/12] phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
2014-02-11 9:30 ` [PATCH V6 07/12] phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support Mohit Kumar
@ 2014-02-11 12:06 ` Kishon Vijay Abraham I
2014-02-12 4:07 ` Mohit KUMAR DCG
0 siblings, 1 reply; 10+ messages in thread
From: Kishon Vijay Abraham I @ 2014-02-11 12:06 UTC (permalink / raw)
To: linux-arm-kernel
On Tuesday 11 February 2014 03:00 PM, Mohit Kumar wrote:
> From: Pratyush Anand <pratyush.anand@st.com>
>
> SPEAr1310 and SPEAr1340 uses miphy40lp phy for PCIe. This driver adds
> support for the same.
What's up with SATA support for SPEAr1310? Do you have plans of adding it soon?
>
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Tested-by: Mohit Kumar <mohit.kumar@st.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Viresh Kumar <viresh.linux@gmail.com>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Cc: spear-devel at list.st.com
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> ---
> drivers/phy/phy-miphy40lp.c | 165 +++++++++++++++++++++++++++++++++++++++++++
> 1 files changed, 165 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> index 16da55b..dec67ed 100644
> --- a/drivers/phy/phy-miphy40lp.c
> +++ b/drivers/phy/phy-miphy40lp.c
> @@ -9,6 +9,7 @@
> * published by the Free Software Foundation.
> *
> * 04/02/2014: Adding support of SATA mode for SPEAr1340.
> + * 04/02/2014: Adding support of PCIe mode for SPEAr1340 and SPEAr1310
> */
>
> #include <linux/bitops.h>
> @@ -74,6 +75,80 @@
> #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
> (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
> +/* SPEAr1310 Registers */
> +#define SPEAR1310_PCIE_SATA_CFG 0x3A4
> + #define SPEAR1310_PCIE_SATA2_SEL_PCIE (0 << 31)
> + #define SPEAR1310_PCIE_SATA1_SEL_PCIE (0 << 30)
> + #define SPEAR1310_PCIE_SATA0_SEL_PCIE (0 << 29)
> + #define SPEAR1310_PCIE_SATA2_SEL_SATA BIT(31)
> + #define SPEAR1310_PCIE_SATA1_SEL_SATA BIT(30)
> + #define SPEAR1310_PCIE_SATA0_SEL_SATA BIT(29)
> + #define SPEAR1310_SATA2_CFG_TX_CLK_EN BIT(27)
> + #define SPEAR1310_SATA2_CFG_RX_CLK_EN BIT(26)
> + #define SPEAR1310_SATA2_CFG_POWERUP_RESET BIT(25)
> + #define SPEAR1310_SATA2_CFG_PM_CLK_EN BIT(24)
> + #define SPEAR1310_SATA1_CFG_TX_CLK_EN BIT(23)
> + #define SPEAR1310_SATA1_CFG_RX_CLK_EN BIT(22)
> + #define SPEAR1310_SATA1_CFG_POWERUP_RESET BIT(21)
> + #define SPEAR1310_SATA1_CFG_PM_CLK_EN BIT(20)
> + #define SPEAR1310_SATA0_CFG_TX_CLK_EN BIT(19)
> + #define SPEAR1310_SATA0_CFG_RX_CLK_EN BIT(18)
> + #define SPEAR1310_SATA0_CFG_POWERUP_RESET BIT(17)
> + #define SPEAR1310_SATA0_CFG_PM_CLK_EN BIT(16)
> + #define SPEAR1310_PCIE2_CFG_DEVICE_PRESENT BIT(11)
> + #define SPEAR1310_PCIE2_CFG_POWERUP_RESET BIT(10)
> + #define SPEAR1310_PCIE2_CFG_CORE_CLK_EN BIT(9)
> + #define SPEAR1310_PCIE2_CFG_AUX_CLK_EN BIT(8)
> + #define SPEAR1310_PCIE1_CFG_DEVICE_PRESENT BIT(7)
> + #define SPEAR1310_PCIE1_CFG_POWERUP_RESET BIT(6)
> + #define SPEAR1310_PCIE1_CFG_CORE_CLK_EN BIT(5)
> + #define SPEAR1310_PCIE1_CFG_AUX_CLK_EN BIT(4)
> + #define SPEAR1310_PCIE0_CFG_DEVICE_PRESENT BIT(3)
> + #define SPEAR1310_PCIE0_CFG_POWERUP_RESET BIT(2)
> + #define SPEAR1310_PCIE0_CFG_CORE_CLK_EN BIT(1)
> + #define SPEAR1310_PCIE0_CFG_AUX_CLK_EN BIT(0)
> +
> + #define SPEAR1310_PCIE_CFG_MASK(x) ((0xF << (x * 4)) | BIT((x + 29)))
> + #define SPEAR1310_SATA_CFG_MASK(x) ((0xF << (x * 4 + 16)) | \
> + BIT((x + 29)))
> + #define SPEAR1310_PCIE_CFG_VAL(x) \
> + (SPEAR1310_PCIE_SATA##x##_SEL_PCIE | \
> + SPEAR1310_PCIE##x##_CFG_AUX_CLK_EN | \
> + SPEAR1310_PCIE##x##_CFG_CORE_CLK_EN | \
> + SPEAR1310_PCIE##x##_CFG_POWERUP_RESET | \
> + SPEAR1310_PCIE##x##_CFG_DEVICE_PRESENT)
> + #define SPEAR1310_SATA_CFG_VAL(x) \
> + (SPEAR1310_PCIE_SATA##x##_SEL_SATA | \
> + SPEAR1310_SATA##x##_CFG_PM_CLK_EN | \
> + SPEAR1310_SATA##x##_CFG_POWERUP_RESET | \
> + SPEAR1310_SATA##x##_CFG_RX_CLK_EN | \
> + SPEAR1310_SATA##x##_CFG_TX_CLK_EN)
> +
> +#define SPEAR1310_PCIE_MIPHY_CFG_1 0x3A8
> + #define SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT BIT(31)
> + #define SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 BIT(28)
> + #define SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(x) (x << 16)
> + #define SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT BIT(15)
> + #define SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 BIT(12)
> + #define SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(x) (x << 0)
> + #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_MASK (0xFFFF)
> + #define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK (0xFFFF << 16)
> + #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA \
> + (SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
> + SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 | \
> + SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(60) | \
> + SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
> + SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 | \
> + SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(60))
> + #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
> + (SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(120))
> + #define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE \
> + (SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
> + SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(25) | \
> + SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
> + SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(25))
> +
> +#define SPEAR1310_PCIE_MIPHY_CFG_2 0x3AC
>
> enum phy_mode {
> SATA,
> @@ -146,12 +221,35 @@ static int miphy40lp_spear1340_sata_exit(struct miphy40lp_priv *priv)
> return 0;
> }
>
> +static int miphy40lp_spear1340_pcie_init(struct miphy40lp_priv *priv)
> +{
> + regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> + SPEAR1340_PCIE_MIPHY_CFG_MASK,
> + SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE);
> + regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
> + SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_PCIE_CFG_VAL);
> +
> + return 0;
> +}
> +
> +static int miphy40lp_spear1340_pcie_exit(struct miphy40lp_priv *priv)
> +{
> + regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> + SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
> + regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
> + SPEAR1340_PCIE_SATA_CFG_MASK, 0);
> +
> + return 0;
> +}
> +
> static int miphy40lp_spear1340_init(struct miphy40lp_priv *priv)
> {
> int ret = 0;
>
> if (priv->mode == SATA)
> ret = miphy40lp_spear1340_sata_init(priv);
> + else if (priv->mode == PCIE)
> + ret = miphy40lp_spear1340_pcie_init(priv);
>
> return ret;
> }
> @@ -162,6 +260,8 @@ static int miphy40lp_spear1340_exit(struct miphy40lp_priv *priv)
>
> if (priv->mode == SATA)
> ret = miphy40lp_spear1340_sata_exit(priv);
> + else if (priv->mode == PCIE)
> + ret = miphy40lp_spear1340_pcie_exit(priv);
>
> return ret;
> }
> @@ -193,6 +293,70 @@ static struct miphy40lp_plat_ops spear1340_phy_ops = {
> .plat_resume = miphy40lp_spear1340_resume,
> };
>
> +static int miphy40lp_spear1310_pcie_init(struct miphy40lp_priv *priv)
> +{
> + u32 val;
> +
> + regmap_update_bits(priv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
> + SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK,
> + SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE);
> +
> + switch (priv->id) {
'id' should be made as optional dt property since it's not used for 1340 no?
Thanks
Kishon
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH V6 07/12] phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
2014-02-11 12:06 ` Kishon Vijay Abraham I
@ 2014-02-12 4:07 ` Mohit KUMAR DCG
0 siblings, 0 replies; 10+ messages in thread
From: Mohit KUMAR DCG @ 2014-02-12 4:07 UTC (permalink / raw)
To: linux-arm-kernel
Hello Kishon,
> -----Original Message-----
> From: Kishon Vijay Abraham I [mailto:kishon at ti.com]
> Sent: Tuesday, February 11, 2014 5:36 PM
> To: Mohit KUMAR DCG; arnd at arndb.de
> Cc: Pratyush ANAND; Viresh Kumar; spear-devel; linux-arm-
> kernel at lists.infradead.org; linux-kernel at vger.kernel.org
> Subject: Re: [PATCH V6 07/12] phy: st-miphy-40lp: Add SPEAr1310 and
> SPEAr1340 PCIe phy support
>
> On Tuesday 11 February 2014 03:00 PM, Mohit Kumar wrote:
> > From: Pratyush Anand <pratyush.anand@st.com>
> >
> > SPEAr1310 and SPEAr1340 uses miphy40lp phy for PCIe. This driver adds
> > support for the same.
>
> What's up with SATA support for SPEAr1310? Do you have plans of adding it
> soon?
> >
- yes we will be doing it after this series is finalized.
[...]
> > +
> > + regmap_update_bits(priv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
> > + SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK,
> > + SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE);
> > +
> > + switch (priv->id) {
>
> 'id' should be made as optional dt property since it's not used for 1340 no?
>
- ok
Thanks
Mohit
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2014-02-12 4:07 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-02-11 9:29 [PATCH V6 00/12]PCI:Add SPEAr13xx PCie support Mohit Kumar
2014-02-11 9:29 ` [PATCH V6 01/12] clk: SPEAr13XX: Fix pcie clock name Mohit Kumar
2014-02-11 9:29 ` [PATCH V6 02/12] SPEAr13XX: Fix static mapping table Mohit Kumar
2014-02-11 9:30 ` [PATCH V6 06/12] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver Mohit Kumar
2014-02-11 11:35 ` Kishon Vijay Abraham I
2014-02-11 9:30 ` [PATCH V6 07/12] phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support Mohit Kumar
2014-02-11 12:06 ` Kishon Vijay Abraham I
2014-02-12 4:07 ` Mohit KUMAR DCG
2014-02-11 9:30 ` [PATCH V6 09/12] SPEAr13XX: dts: Add PCIe node information Mohit Kumar
2014-02-11 9:30 ` [PATCH V6 11/12] SPEAr13xx: defconfig: Update Mohit Kumar
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