Re: [PATCH v2 7/8] dt-bindings: usb: convert mediatek,mtu3.txt to YAML schema

Re: [PATCH v2 7/8] dt-bindings: usb: convert mediatek,mtu3.txt to YAML schema

[Rob Herring]

On Tue, 13 Oct 2020 16:52:06 +0800, Chunfeng Yun wrote:
> Convert mediatek,mtu3.txt to YAML schema mediatek,mtu3.yaml
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v2: new patch
> ---
>  .../devicetree/bindings/usb/mediatek,mtu3.txt | 108 ---------
>  .../bindings/usb/mediatek,mtu3.yaml           | 227 ++++++++++++++++++
>  2 files changed, 227 insertions(+), 108 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
>  create mode 100644 Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml
> 


My bot found errors running 'make dt_binding_check' on your patch:

/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/mediatek,tphy.example.dt.yaml: usb@11271000: compatible: ['mediatek,mt8173-mtu3'] is too short
	From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/mediatek,tphy.example.dt.yaml: usb@11271000: 'clocks' is a required property
	From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/mediatek,tphy.example.dt.yaml: usb@11271000: 'clock-names' is a required property
	From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml


See https://patchwork.ozlabs.org/patch/1381414

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure dt-schema is up to date:

pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade

Please check and re-submit.


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Re: [PATCH v2 1/8] dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema

[Rob Herring]

On Tue, Oct 13, 2020 at 04:52:00PM +0800, Chunfeng Yun wrote:
> Convert phy-mtk-xsphy.txt to YAML schema mediatek,xsphy.yaml
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v2: modify description and compatible definition suggested by Rob
> ---
>  .../bindings/phy/mediatek,xsphy.yaml          | 200 ++++++++++++++++++
>  .../devicetree/bindings/phy/phy-mtk-xsphy.txt | 109 ----------
>  2 files changed, 200 insertions(+), 109 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
>  delete mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt
> 
> diff --git a/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
> new file mode 100644
> index 000000000000..86511f19277a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
> @@ -0,0 +1,200 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2020 MediaTek
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/mediatek,xsphy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek XS-PHY Controller Device Tree Bindings
> +
> +maintainers:
> +  - Chunfeng Yun <chunfeng.yun@mediatek.com>
> +
> +description: |
> +  The XS-PHY controller supports physical layer functionality for USB3.1
> +  GEN2 controller on MediaTek SoCs.
> +
> +  Banks layout of xsphy
> +  ----------------------------------
> +  port        offset    bank
> +  u2 port0    0x0000    MISC
> +              0x0100    FMREG
> +              0x0300    U2PHY_COM
> +  u2 port1    0x1000    MISC
> +              0x1100    FMREG
> +              0x1300    U2PHY_COM
> +  u2 port2    0x2000    MISC
> +              ...
> +  u31 common  0x3000    DIG_GLB
> +              0x3100    PHYA_GLB
> +  u31 port0   0x3400    DIG_LN_TOP
> +              0x3500    DIG_LN_TX0
> +              0x3600    DIG_LN_RX0
> +              0x3700    DIG_LN_DAIF
> +              0x3800    PHYA_LN
> +  u31 port1   0x3a00    DIG_LN_TOP
> +              0x3b00    DIG_LN_TX0
> +              0x3c00    DIG_LN_RX0
> +              0x3d00    DIG_LN_DAIF
> +              0x3e00    PHYA_LN
> +              ...
> +  DIG_GLB & PHYA_GLB are shared by U31 ports.
> +
> +properties:
> +  $nodename:
> +    pattern: "^xs-phy@[0-9a-f]+$"
> +
> +  compatible:
> +    items:
> +      - enum:
> +          - mediatek,mt3611-xsphy
> +          - mediatek,mt3612-xsphy
> +      - const: mediatek,xsphy
> +
> +  reg:
> +    description: |
> +      Register shared by multiple U3 ports, exclude port's private register,
> +      if only U2 ports provided, shouldn't use the property.
> +    maxItems: 1
> +
> +  "#address-cells":
> +      enum: [1, 2]
> +
> +  "#size-cells":
> +      enum: [1, 2]
> +
> +  ranges: true
> +
> +  mediatek,src-ref-clk-mhz:
> +    description:
> +      Frequency of reference clock for slew rate calibrate
> +    $ref: /schemas/types.yaml#/definitions/uint32

Properties with a standard unit suffix don't need a type.

> +    default: 26
> +
> +  mediatek,src-coef:
> +    description:
> +      Coefficient for slew rate calibrate, depends on SoC process
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    default: 17
> +
> +# Required child node:
> +patternProperties:
> +  "^usb-phy@[0-9a-f]+$":
> +    type: object
> +    description: |
> +      A sub-node is required for each port the controller provides.
> +      Address range information including the usual 'reg' property
> +      is used inside these nodes to describe the controller's topology.
> +
> +    properties:
> +      reg:
> +        maxItems: 1
> +
> +      clocks:
> +        items:
> +          - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
> +
> +      clock-names:
> +        items:
> +          - const: ref
> +
> +      "#phy-cells":
> +        const: 1
> +        description: |
> +          The cells contain the following arguments.
> +
> +          - description: The PHY type
> +              enum:
> +                - PHY_TYPE_USB2
> +                - PHY_TYPE_USB3
> +
> +      #The following optional vendor properties are only for debug or HQA test
> +      mediatek,eye-src:
> +        description:
> +          The value of slew rate calibrate (U2 phy)
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        minimum: 1
> +        maximum: 7
> +
> +      mediatek,eye-vrt:
> +        description:
> +          The selection of VRT reference voltage (U2 phy)
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        minimum: 1
> +        maximum: 7
> +
> +      mediatek,eye-term:
> +        description:
> +          The selection of HS_TX TERM reference voltage (U2 phy)
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        minimum: 1
> +        maximum: 7
> +
> +      mediatek,efuse-intr:
> +        description:
> +          The selection of Internal Resistor (U2/U3 phy)
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        minimum: 1
> +        maximum: 63
> +
> +      mediatek,efuse-tx-imp:
> +        description:
> +          The selection of TX Impedance (U3 phy)
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        minimum: 1
> +        maximum: 31
> +
> +      mediatek,efuse-rx-imp:
> +        description:
> +          The selection of RX Impedance (U3 phy)
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        minimum: 1
> +        maximum: 31
> +
> +    required:
> +      - reg
> +      - clocks
> +      - clock-names
> +      - "#phy-cells"
> +
> +    additionalProperties: false
> +
> +required:
> +  - compatible
> +  - "#address-cells"
> +  - "#size-cells"
> +  - ranges
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/phy/phy.h>
> +
> +    u3phy: xs-phy@11c40000 {
> +        compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy";
> +        reg = <0x11c43000 0x0200>;
> +        mediatek,src-ref-clk-mhz = <26>;
> +        mediatek,src-coef = <17>;
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +        ranges;
> +
> +        u2port0: usb-phy@11c40000 {
> +            reg = <0x11c40000 0x0400>;
> +            clocks = <&clk48m>;
> +            clock-names = "ref";
> +            mediatek,eye-src = <4>;
> +            #phy-cells = <1>;
> +        };
> +
> +        u3port0: usb-phy@11c43000 {
> +            reg = <0x11c43400 0x0500>;
> +            clocks = <&clk26m>;
> +            clock-names = "ref";
> +            mediatek,efuse-intr = <28>;
> +            #phy-cells = <1>;
> +        };
> +    };
> +
> +...
> diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt
> deleted file mode 100644
> index e7caefa0b9c2..000000000000
> --- a/Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt
> +++ /dev/null
> @@ -1,109 +0,0 @@
> -MediaTek XS-PHY binding
> ---------------------------
> -
> -The XS-PHY controller supports physical layer functionality for USB3.1
> -GEN2 controller on MediaTek SoCs.
> -
> -Required properties (controller (parent) node):
> - - compatible	: should be "mediatek,<soc-model>-xsphy", "mediatek,xsphy",
> -		  soc-model is the name of SoC, such as mt3611 etc;
> -		  when using "mediatek,xsphy" compatible string, you need SoC specific
> -		  ones in addition, one of:
> -		  - "mediatek,mt3611-xsphy"
> -
> - - #address-cells, #size-cells : should use the same values as the root node
> - - ranges: must be present
> -
> -Optional properties (controller (parent) node):
> - - reg		: offset and length of register shared by multiple U3 ports,
> -		  exclude port's private register, if only U2 ports provided,
> -		  shouldn't use the property.
> - - mediatek,src-ref-clk-mhz	: u32, frequency of reference clock for slew rate
> -		  calibrate
> - - mediatek,src-coef	: u32, coefficient for slew rate calibrate, depends on
> -		  SoC process
> -
> -Required nodes	: a sub-node is required for each port the controller
> -		  provides. Address range information including the usual
> -		  'reg' property is used inside these nodes to describe
> -		  the controller's topology.
> -
> -Required properties (port (child) node):
> -- reg		: address and length of the register set for the port.
> -- clocks	: a list of phandle + clock-specifier pairs, one for each
> -		  entry in clock-names
> -- clock-names	: must contain
> -		  "ref": 48M reference clock for HighSpeed analog phy; and 26M
> -			reference clock for SuperSpeedPlus analog phy, sometimes is
> -			24M, 25M or 27M, depended on platform.
> -- #phy-cells	: should be 1
> -		  cell after port phandle is phy type from:
> -			- PHY_TYPE_USB2
> -			- PHY_TYPE_USB3
> -
> -The following optional properties are only for debug or HQA test
> -Optional properties (PHY_TYPE_USB2 port (child) node):
> -- mediatek,eye-src	: u32, the value of slew rate calibrate
> -- mediatek,eye-vrt	: u32, the selection of VRT reference voltage
> -- mediatek,eye-term	: u32, the selection of HS_TX TERM reference voltage
> -- mediatek,efuse-intr	: u32, the selection of Internal Resistor
> -
> -Optional properties (PHY_TYPE_USB3 port (child) node):
> -- mediatek,efuse-intr	: u32, the selection of Internal Resistor
> -- mediatek,efuse-tx-imp	: u32, the selection of TX Impedance
> -- mediatek,efuse-rx-imp	: u32, the selection of RX Impedance
> -
> -Banks layout of xsphy
> --------------------------------------------------------------
> -port        offset    bank
> -u2 port0    0x0000    MISC
> -            0x0100    FMREG
> -            0x0300    U2PHY_COM
> -u2 port1    0x1000    MISC
> -            0x1100    FMREG
> -            0x1300    U2PHY_COM
> -u2 port2    0x2000    MISC
> -            ...
> -u31 common  0x3000    DIG_GLB
> -            0x3100    PHYA_GLB
> -u31 port0   0x3400    DIG_LN_TOP
> -            0x3500    DIG_LN_TX0
> -            0x3600    DIG_LN_RX0
> -            0x3700    DIG_LN_DAIF
> -            0x3800    PHYA_LN
> -u31 port1   0x3a00    DIG_LN_TOP
> -            0x3b00    DIG_LN_TX0
> -            0x3c00    DIG_LN_RX0
> -            0x3d00    DIG_LN_DAIF
> -            0x3e00    PHYA_LN
> -            ...
> -
> -DIG_GLB & PHYA_GLB are shared by U31 ports.
> -
> -Example:
> -
> -u3phy: usb-phy@11c40000 {
> -	compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy";
> -	reg = <0 0x11c43000 0 0x0200>;
> -	mediatek,src-ref-clk-mhz = <26>;
> -	mediatek,src-coef = <17>;
> -	#address-cells = <2>;
> -	#size-cells = <2>;
> -	ranges;
> -
> -	u2port0: usb-phy@11c40000 {
> -		reg = <0 0x11c40000 0 0x0400>;
> -		clocks = <&clk48m>;
> -		clock-names = "ref";
> -		mediatek,eye-src = <4>;
> -		#phy-cells = <1>;
> -	};
> -
> -	u3port0: usb-phy@11c43000 {
> -		reg = <0 0x11c43400 0 0x0500>;
> -		clocks = <&clk26m>;
> -		clock-names = "ref";
> -		mediatek,efuse-intr = <28>;
> -		#phy-cells = <1>;
> -	};
> -};
> -- 
> 2.18.0

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Re: [PATCH v2 1/8] dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema

[Chunfeng Yun]

On Fri, 2020-10-16 at 12:00 -0500, Rob Herring wrote:
> On Tue, Oct 13, 2020 at 04:52:00PM +0800, Chunfeng Yun wrote:
> > Convert phy-mtk-xsphy.txt to YAML schema mediatek,xsphy.yaml
> > 
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > ---
> > v2: modify description and compatible definition suggested by Rob
> > ---
> >  .../bindings/phy/mediatek,xsphy.yaml          | 200 ++++++++++++++++++
> >  .../devicetree/bindings/phy/phy-mtk-xsphy.txt | 109 ----------
> >  2 files changed, 200 insertions(+), 109 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
> >  delete mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
> > new file mode 100644
> > index 000000000000..86511f19277a
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
> > @@ -0,0 +1,200 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +# Copyright (c) 2020 MediaTek
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/phy/mediatek,xsphy.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MediaTek XS-PHY Controller Device Tree Bindings
> > +
> > +maintainers:
> > +  - Chunfeng Yun <chunfeng.yun@mediatek.com>
> > +
> > +description: |
> > +  The XS-PHY controller supports physical layer functionality for USB3.1
> > +  GEN2 controller on MediaTek SoCs.
[...]
> > +
> > +  ranges: true
> > +
> > +  mediatek,src-ref-clk-mhz:
> > +    description:
> > +      Frequency of reference clock for slew rate calibrate
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> 
> Properties with a standard unit suffix don't need a type.
Ok, will remove it, and also do it for other patches, thanks

> > -- 
[...]
> > 2.18.0

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Re: [PATCH v2 2/8] dt-bindings: phy: convert phy-mtk-tphy.txt to YAML schema

[Rob Herring]

On Tue, Oct 13, 2020 at 04:52:01PM +0800, Chunfeng Yun wrote:
> Convert phy-mtk-tphy.txt to YAML schema mediatek,tphy.yaml
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v2: modify description and compatible
> ---
>  .../bindings/phy/mediatek,tphy.yaml           | 263 ++++++++++++++++++
>  .../devicetree/bindings/phy/phy-mtk-tphy.txt  | 162 -----------
>  2 files changed, 263 insertions(+), 162 deletions(-)
>  create mode 100755 Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
>  delete mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
> 
> diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
> new file mode 100755
> index 000000000000..56ad8be69095
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
> @@ -0,0 +1,263 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2020 MediaTek
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek T-PHY Controller Device Tree Bindings
> +
> +maintainers:
> +  - Chunfeng Yun <chunfeng.yun@mediatek.com>
> +
> +description: |
> +  The T-PHY controller supports physical layer functionality for a number of
> +  controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
> +
> +  Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
> +  T-PHY V2 (mt2712) when works on USB mode:
> +  -----------------------------------
> +  Version 1:
> +  port        offset    bank
> +  shared      0x0000    SPLLC
> +              0x0100    FMREG
> +  u2 port0    0x0800    U2PHY_COM
> +  u3 port0    0x0900    U3PHYD
> +              0x0a00    U3PHYD_BANK2
> +              0x0b00    U3PHYA
> +              0x0c00    U3PHYA_DA
> +  u2 port1    0x1000    U2PHY_COM
> +  u3 port1    0x1100    U3PHYD
> +              0x1200    U3PHYD_BANK2
> +              0x1300    U3PHYA
> +              0x1400    U3PHYA_DA
> +  u2 port2    0x1800    U2PHY_COM
> +              ...
> +
> +  Version 2:
> +  port        offset    bank
> +  u2 port0    0x0000    MISC
> +              0x0100    FMREG
> +              0x0300    U2PHY_COM
> +  u3 port0    0x0700    SPLLC
> +              0x0800    CHIP
> +              0x0900    U3PHYD
> +              0x0a00    U3PHYD_BANK2
> +              0x0b00    U3PHYA
> +              0x0c00    U3PHYA_DA
> +  u2 port1    0x1000    MISC
> +              0x1100    FMREG
> +              0x1300    U2PHY_COM
> +  u3 port1    0x1700    SPLLC
> +              0x1800    CHIP
> +              0x1900    U3PHYD
> +              0x1a00    U3PHYD_BANK2
> +              0x1b00    U3PHYA
> +              0x1c00    U3PHYA_DA
> +  u2 port2    0x2000    MISC
> +              ...
> +
> +  SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back
> +  into each port; a new bank MISC for u2 ports and CHIP for u3 ports are
> +  added on V2.
> +
> +properties:
> +  $nodename:
> +     pattern: "^t-phy@[0-9a-f]+$"

Wrong indentation. Should be 1 less.

> +
> +  compatible:
> +    oneOf:
> +      - items:
> +          - enum:
> +              - mediatek,mt2701-tphy
> +              - mediatek,mt7623-tphy
> +              - mediatek,mt7622-tphy
> +              - mediatek,mt8516-tphy
> +          - const: mediatek,generic-tphy-v1
> +      - items:
> +          - enum:
> +              - mediatek,mt2712-tphy
> +              - mediatek,mt7629-tphy
> +              - mediatek,mt8183-tphy
> +          - const: mediatek,generic-tphy-v2
> +      - const: mediatek,mt2701-u3phy
> +        deprecated: true
> +      - const: mediatek,mt2712-u3phy
> +        deprecated: true
> +      - const: mediatek,mt8173-u3phy
> +
> +  reg:
> +    description: |

Don't need '|' if there's no formatting to preserve.

> +      Register shared by multiple ports, exclude port's private register.
> +      It is needed for T-PHY V1, such as mt2701 and mt8173, but not for
> +      T-PHY V2, such as mt2712.
> +    maxItems: 1
> +
> +  "#address-cells":
> +      enum: [1, 2]
> +
> +  "#size-cells":
> +      enum: [1, 2]

Wrong indent.

> +
> +  # Used with non-empty value if optional 'reg' is not provided.
> +  # The format of the value is an arbitrary number of triplets of
> +  # (child-bus-address, parent-bus-address, length).
> +  ranges: true
> +
> +  mediatek,src-ref-clk-mhz:
> +    description:
> +      Frequency of reference clock for slew rate calibrate
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    default: 26
> +
> +  mediatek,src-coef:
> +    description:
> +      Coefficient for slew rate calibrate, depends on SoC process
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    default: 28
> +
> +# Required child node:
> +patternProperties:
> +  "^usb-phy@[0-9a-f]+$":
> +    type: object
> +    description: |
> +      A sub-node is required for each port the controller provides.
> +      Address range information including the usual 'reg' property
> +      is used inside these nodes to describe the controller's topology.
> +
> +    properties:
> +      reg:
> +        maxItems: 1
> +
> +      clocks:
> +        minItems: 1
> +        maxItems: 2
> +        items:
> +          - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
> +          - description: Reference clock of analog phy
> +        description: |
> +          Uses both clocks if the clock of analog and digital phys are
> +          separated, otherwise uses "ref" clock only if needed.
> +
> +      clock-names:
> +        minItems: 1
> +        maxItems: 2
> +        items:
> +          - const: ref
> +          - const: da_ref
> +
> +      "#phy-cells":
> +        const: 1
> +        description: |
> +          The cells contain the following arguments.
> +
> +          - description: The PHY type
> +              enum:
> +                - PHY_TYPE_USB2
> +                - PHY_TYPE_USB3
> +                - PHY_TYPE_PCIE
> +                - PHY_TYPE_SATA
> +
> +      #The following optional vendor properties are only for debug or HQA test

space     ^

> +      mediatek,eye-src:
> +        description:
> +          The value of slew rate calibrate (U2 phy)
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        minimum: 1
> +        maximum: 7
> +
> +      mediatek,eye-vrt:
> +        description:
> +          The selection of VRT reference voltage (U2 phy)
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        minimum: 1
> +        maximum: 7
> +
> +      mediatek,eye-term:
> +        description:
> +          The selection of HS_TX TERM reference voltage (U2 phy)
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        minimum: 1
> +        maximum: 7
> +
> +      mediatek,intr:
> +        description:
> +          The selection of internal resistor (U2 phy)
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        minimum: 1
> +        maximum: 31
> +
> +      mediatek,discth:
> +        description:
> +          The selection of disconnect threshold (U2 phy)
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        minimum: 1
> +        maximum: 15
> +
> +      mediatek,bc12:
> +        description:
> +          Specify the flag to enable BC1.2 if support it
> +        type: boolean
> +
> +    required:
> +      - reg
> +      - "#phy-cells"
> +
> +    additionalProperties: false
> +
> +required:
> +  - compatible
> +  - "#address-cells"
> +  - "#size-cells"
> +  - ranges
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/mt8173-clk.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +    #include <dt-bindings/phy/phy.h>
> +    susb: usb@11271000 {

Drop unused labels.

> +        compatible = "mediatek,mt8173-mtu3";
> +        reg = <0x11271000 0x3000>, <0x11280700 0x0100>;
> +        reg-names = "mac", "ippc";
> +        phys = <&u2port0 PHY_TYPE_USB2>,
> +               <&u3port0 PHY_TYPE_USB3>,
> +               <&u2port1 PHY_TYPE_USB2>;
> +        interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
> +    };
> +
> +    u3phy: t-phy@11290000 {
> +        compatible = "mediatek,mt8173-u3phy";
> +        reg = <0x11290000 0x800>;
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +        ranges;
> +        status = "okay";

Don't show status in examples.

> +
> +        u2port0: usb-phy@11290800 {
> +            reg = <0x11290800 0x100>;
> +            clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk48m>;
> +            clock-names = "ref", "da_ref";
> +            #phy-cells = <1>;
> +            status = "okay";
> +        };
> +
> +        u3port0: usb-phy@11290900 {
> +            reg = <0x11290900 0x700>;
> +            clocks = <&clk26m>;
> +            clock-names = "ref";
> +            #phy-cells = <1>;
> +            status = "okay";
> +        };
> +
> +        u2port1: usb-phy@11291000 {
> +            reg = <0x11291000 0x100>;
> +            #phy-cells = <1>;
> +            status = "okay";
> +        };
> +    };
> +
> +...
> diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
> deleted file mode 100644
> index dd75b676b71d..000000000000
> --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
> +++ /dev/null
> @@ -1,162 +0,0 @@
> -MediaTek T-PHY binding
> ---------------------------
> -
> -T-phy controller supports physical layer functionality for a number of
> -controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.
> -
> -Required properties (controller (parent) node):
> - - compatible	: should be one of
> -		  "mediatek,generic-tphy-v1"
> -		  "mediatek,generic-tphy-v2"
> -		  "mediatek,mt2701-u3phy" (deprecated)
> -		  "mediatek,mt2712-u3phy" (deprecated)
> -		  "mediatek,mt8173-u3phy";
> -		  make use of "mediatek,generic-tphy-v1" on mt2701 instead and
> -		  "mediatek,generic-tphy-v2" on mt2712 instead.
> -
> -- #address-cells:	the number of cells used to represent physical
> -		base addresses.
> -- #size-cells:	the number of cells used to represent the size of an address.
> -- ranges:	the address mapping relationship to the parent, defined with
> -		- empty value: if optional 'reg' is used.
> -		- non-empty value: if optional 'reg' is not used. should set
> -			the child's base address to 0, the physical address
> -			within parent's address space, and the length of
> -			the address map.
> -
> -Required nodes	: a sub-node is required for each port the controller
> -		  provides. Address range information including the usual
> -		  'reg' property is used inside these nodes to describe
> -		  the controller's topology.
> -
> -Optional properties (controller (parent) node):
> - - reg		: offset and length of register shared by multiple ports,
> -		  exclude port's private register. It is needed on mt2701
> -		  and mt8173, but not on mt2712.
> - - mediatek,src-ref-clk-mhz	: frequency of reference clock for slew rate
> -		  calibrate
> - - mediatek,src-coef	: coefficient for slew rate calibrate, depends on
> -		  SoC process
> -
> -Required properties (port (child) node):
> -- reg		: address and length of the register set for the port.
> -- #phy-cells	: should be 1 (See second example)
> -		  cell after port phandle is phy type from:
> -			- PHY_TYPE_USB2
> -			- PHY_TYPE_USB3
> -			- PHY_TYPE_PCIE
> -			- PHY_TYPE_SATA
> -
> -Optional properties (PHY_TYPE_USB2 port (child) node):
> -- clocks	: a list of phandle + clock-specifier pairs, one for each
> -		  entry in clock-names
> -- clock-names	: may contain
> -		  "ref": 48M reference clock for HighSpeed (digital) phy; and 26M
> -			reference clock for SuperSpeed (digital) phy, sometimes is
> -			24M, 25M or 27M, depended on platform.
> -		  "da_ref": the reference clock of analog phy, used if the clocks
> -			of analog and digital phys are separated, otherwise uses
> -			"ref" clock only if needed.
> -
> -- mediatek,eye-src	: u32, the value of slew rate calibrate
> -- mediatek,eye-vrt	: u32, the selection of VRT reference voltage
> -- mediatek,eye-term	: u32, the selection of HS_TX TERM reference voltage
> -- mediatek,bc12	: bool, enable BC12 of u2phy if support it
> -- mediatek,discth	: u32, the selection of disconnect threshold
> -- mediatek,intr	: u32, the selection of internal R (resistance)
> -
> -Example:
> -
> -u3phy: usb-phy@11290000 {
> -	compatible = "mediatek,mt8173-u3phy";
> -	reg = <0 0x11290000 0 0x800>;
> -	#address-cells = <2>;
> -	#size-cells = <2>;
> -	ranges;
> -
> -	u2port0: usb-phy@11290800 {
> -		reg = <0 0x11290800 0 0x100>;
> -		clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
> -		clock-names = "ref";
> -		#phy-cells = <1>;
> -	};
> -
> -	u3port0: usb-phy@11290900 {
> -		reg = <0 0x11290800 0 0x700>;
> -		clocks = <&clk26m>;
> -		clock-names = "ref";
> -		#phy-cells = <1>;
> -	};
> -
> -	u2port1: usb-phy@11291000 {
> -		reg = <0 0x11291000 0 0x100>;
> -		clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
> -		clock-names = "ref";
> -		#phy-cells = <1>;
> -	};
> -};
> -
> -Specifying phy control of devices
> ----------------------------------
> -
> -Device nodes should specify the configuration required in their "phys"
> -property, containing a phandle to the phy port node and a device type;
> -phy-names for each port are optional.
> -
> -Example:
> -
> -#include <dt-bindings/phy/phy.h>
> -
> -usb30: usb@11270000 {
> -	...
> -	phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
> -	phy-names = "usb2-0", "usb3-0";
> -	...
> -};
> -
> -
> -Layout differences of banks between mt8173/mt2701 and mt2712
> --------------------------------------------------------------
> -mt8173 and mt2701:
> -port        offset    bank
> -shared      0x0000    SPLLC
> -            0x0100    FMREG
> -u2 port0    0x0800    U2PHY_COM
> -u3 port0    0x0900    U3PHYD
> -            0x0a00    U3PHYD_BANK2
> -            0x0b00    U3PHYA
> -            0x0c00    U3PHYA_DA
> -u2 port1    0x1000    U2PHY_COM
> -u3 port1    0x1100    U3PHYD
> -            0x1200    U3PHYD_BANK2
> -            0x1300    U3PHYA
> -            0x1400    U3PHYA_DA
> -u2 port2    0x1800    U2PHY_COM
> -            ...
> -
> -mt2712:
> -port        offset    bank
> -u2 port0    0x0000    MISC
> -            0x0100    FMREG
> -            0x0300    U2PHY_COM
> -u3 port0    0x0700    SPLLC
> -            0x0800    CHIP
> -            0x0900    U3PHYD
> -            0x0a00    U3PHYD_BANK2
> -            0x0b00    U3PHYA
> -            0x0c00    U3PHYA_DA
> -u2 port1    0x1000    MISC
> -            0x1100    FMREG
> -            0x1300    U2PHY_COM
> -u3 port1    0x1700    SPLLC
> -            0x1800    CHIP
> -            0x1900    U3PHYD
> -            0x1a00    U3PHYD_BANK2
> -            0x1b00    U3PHYA
> -            0x1c00    U3PHYA_DA
> -u2 port2    0x2000    MISC
> -            ...
> -
> -    SPLLC shared by u3 ports and FMREG shared by u2 ports on
> -mt8173/mt2701 are put back into each port; a new bank MISC for
> -u2 ports and CHIP for u3 ports are added on mt2712.
> -- 
> 2.18.0

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Re: [PATCH v2 2/8] dt-bindings: phy: convert phy-mtk-tphy.txt to YAML schema

[Chunfeng Yun]

On Fri, 2020-10-16 at 12:04 -0500, Rob Herring wrote:
> On Tue, Oct 13, 2020 at 04:52:01PM +0800, Chunfeng Yun wrote:
> > Convert phy-mtk-tphy.txt to YAML schema mediatek,tphy.yaml
> > 
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > ---
> > v2: modify description and compatible
> > ---
> >  .../bindings/phy/mediatek,tphy.yaml           | 263 ++++++++++++++++++
> >  .../devicetree/bindings/phy/phy-mtk-tphy.txt  | 162 -----------
> >  2 files changed, 263 insertions(+), 162 deletions(-)
> >  create mode 100755 Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
> >  delete mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
> > new file mode 100755
> > index 000000000000..56ad8be69095
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
> > @@ -0,0 +1,263 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +# Copyright (c) 2020 MediaTek
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MediaTek T-PHY Controller Device Tree Bindings
> > +
> > +maintainers:
> > +  - Chunfeng Yun <chunfeng.yun@mediatek.com>
> > +
> > +description: |
> > +  The T-PHY controller supports physical layer functionality for a number of
> > +  controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
[...]
> > +properties:
> > +  $nodename:
> > +     pattern: "^t-phy@[0-9a-f]+$"
> 
> Wrong indentation. Should be 1 less.
Yes, will fix it
> 
> > +
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - enum:
> > +              - mediatek,mt2701-tphy
> > +              - mediatek,mt7623-tphy
> > +              - mediatek,mt7622-tphy
> > +              - mediatek,mt8516-tphy
> > +          - const: mediatek,generic-tphy-v1
> > +      - items:
> > +          - enum:
> > +              - mediatek,mt2712-tphy
> > +              - mediatek,mt7629-tphy
> > +              - mediatek,mt8183-tphy
> > +          - const: mediatek,generic-tphy-v2
> > +      - const: mediatek,mt2701-u3phy
> > +        deprecated: true
> > +      - const: mediatek,mt2712-u3phy
> > +        deprecated: true
> > +      - const: mediatek,mt8173-u3phy
> > +
> > +  reg:
> > +    description: |
> 
> Don't need '|' if there's no formatting to preserve.
Got it
> 
> > +      Register shared by multiple ports, exclude port's private register.
> > +      It is needed for T-PHY V1, such as mt2701 and mt8173, but not for
> > +      T-PHY V2, such as mt2712.
> > +    maxItems: 1
> > +
> > +  "#address-cells":
> > +      enum: [1, 2]
> > +
> > +  "#size-cells":
> > +      enum: [1, 2]
> 
> Wrong indent.
Will fix it and check it in other patches
> 
> > +
> > +  # Used with non-empty value if optional 'reg' is not provided.
> > +  # The format of the value is an arbitrary number of triplets of
> > +  # (child-bus-address, parent-bus-address, length).
> > +  ranges: true
> > +
> > +  mediatek,src-ref-clk-mhz:
> > +    description:
> > +      Frequency of reference clock for slew rate calibrate
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    default: 26
> > +
> > +  mediatek,src-coef:
> > +    description:
> > +      Coefficient for slew rate calibrate, depends on SoC process
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    default: 28
> > +
> > +# Required child node:
> > +patternProperties:
> > +  "^usb-phy@[0-9a-f]+$":
> > +    type: object
> > +    description: |
> > +      A sub-node is required for each port the controller provides.
> > +      Address range information including the usual 'reg' property
> > +      is used inside these nodes to describe the controller's topology.
> > +
> > +    properties:
> > +      reg:
> > +        maxItems: 1
> > +
> > +      clocks:
> > +        minItems: 1
> > +        maxItems: 2
> > +        items:
> > +          - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
> > +          - description: Reference clock of analog phy
> > +        description: |
> > +          Uses both clocks if the clock of analog and digital phys are
> > +          separated, otherwise uses "ref" clock only if needed.
> > +
> > +      clock-names:
> > +        minItems: 1
> > +        maxItems: 2
> > +        items:
> > +          - const: ref
> > +          - const: da_ref
> > +
> > +      "#phy-cells":
> > +        const: 1
> > +        description: |
> > +          The cells contain the following arguments.
> > +
> > +          - description: The PHY type
> > +              enum:
> > +                - PHY_TYPE_USB2
> > +                - PHY_TYPE_USB3
> > +                - PHY_TYPE_PCIE
> > +                - PHY_TYPE_SATA
> > +
> > +      #The following optional vendor properties are only for debug or HQA test
> 
> space     ^
Ok, will add it
> 
> > +      mediatek,eye-src:
> > +        description:
> > +          The value of slew rate calibrate (U2 phy)
> > +        $ref: /schemas/types.yaml#/definitions/uint32
> > +        minimum: 1
> > +        maximum: 7
> > +
> > +      mediatek,eye-vrt:
> > +        description:
> > +          The selection of VRT reference voltage (U2 phy)
> > +        $ref: /schemas/types.yaml#/definitions/uint32
> > +        minimum: 1
> > +        maximum: 7
> > +
> > +      mediatek,eye-term:
> > +        description:
> > +          The selection of HS_TX TERM reference voltage (U2 phy)
> > +        $ref: /schemas/types.yaml#/definitions/uint32
> > +        minimum: 1
> > +        maximum: 7
> > +
> > +      mediatek,intr:
> > +        description:
> > +          The selection of internal resistor (U2 phy)
> > +        $ref: /schemas/types.yaml#/definitions/uint32
> > +        minimum: 1
> > +        maximum: 31
> > +
> > +      mediatek,discth:
> > +        description:
> > +          The selection of disconnect threshold (U2 phy)
> > +        $ref: /schemas/types.yaml#/definitions/uint32
> > +        minimum: 1
> > +        maximum: 15
> > +
> > +      mediatek,bc12:
> > +        description:
> > +          Specify the flag to enable BC1.2 if support it
> > +        type: boolean
> > +
> > +    required:
> > +      - reg
> > +      - "#phy-cells"
> > +
> > +    additionalProperties: false
> > +
> > +required:
> > +  - compatible
> > +  - "#address-cells"
> > +  - "#size-cells"
> > +  - ranges
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/mt8173-clk.h>
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +    #include <dt-bindings/interrupt-controller/irq.h>
> > +    #include <dt-bindings/phy/phy.h>
> > +    susb: usb@11271000 {
> 
> Drop unused labels.
Ok
> 
> > +        compatible = "mediatek,mt8173-mtu3";
> > +        reg = <0x11271000 0x3000>, <0x11280700 0x0100>;
> > +        reg-names = "mac", "ippc";
> > +        phys = <&u2port0 PHY_TYPE_USB2>,
> > +               <&u3port0 PHY_TYPE_USB3>,
> > +               <&u2port1 PHY_TYPE_USB2>;
> > +        interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
> > +    };
> > +
> > +    u3phy: t-phy@11290000 {
> > +        compatible = "mediatek,mt8173-u3phy";
> > +        reg = <0x11290000 0x800>;
> > +        #address-cells = <1>;
> > +        #size-cells = <1>;
> > +        ranges;
> > +        status = "okay";
> 
> Don't show status in examples.
Ok, will remove it

Thanks a lot

> 
> > +
> > +        u2port0: usb-phy@11290800 {
> > +            reg = <0x11290800 0x100>;
> > +            clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk48m>;
> > +            clock-names = "ref", "da_ref";
> > +            #phy-cells = <1>;
> > +            status = "okay";
> > +        };
[...]
> > 2.18.0

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Re: [PATCH v2 2/8] dt-bindings: phy: convert phy-mtk-tphy.txt to YAML schema

[Rob Herring]

On Tue, Oct 13, 2020 at 04:52:01PM +0800, Chunfeng Yun wrote:
> Convert phy-mtk-tphy.txt to YAML schema mediatek,tphy.yaml
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v2: modify description and compatible
> ---
>  .../bindings/phy/mediatek,tphy.yaml           | 263 ++++++++++++++++++
>  .../devicetree/bindings/phy/phy-mtk-tphy.txt  | 162 -----------
>  2 files changed, 263 insertions(+), 162 deletions(-)
>  create mode 100755 Documentation/devicetree/bindings/phy/mediatek,tphy.yaml

Also, need to fix the mode.

>  delete mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt

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Re: [PATCH v2 2/8] dt-bindings: phy: convert phy-mtk-tphy.txt to YAML schema

[Chunfeng Yun]

On Fri, 2020-10-16 at 12:05 -0500, Rob Herring wrote:
> On Tue, Oct 13, 2020 at 04:52:01PM +0800, Chunfeng Yun wrote:
> > Convert phy-mtk-tphy.txt to YAML schema mediatek,tphy.yaml
> > 
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > ---
> > v2: modify description and compatible
> > ---
> >  .../bindings/phy/mediatek,tphy.yaml           | 263 ++++++++++++++++++
> >  .../devicetree/bindings/phy/phy-mtk-tphy.txt  | 162 -----------
> >  2 files changed, 263 insertions(+), 162 deletions(-)
> >  create mode 100755 Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
> 
> Also, need to fix the mode.
Ok, thanks

> 
> >  delete mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt

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Re: [PATCH v2 3/8] dt-bindings: phy: convert phy-mtk-ufs.txt to YAML schema

[Rob Herring]

On Tue, 13 Oct 2020 16:52:02 +0800, Chunfeng Yun wrote:
> Convert phy-mtk-ufs.txt to YAML schema mediatek,ufs-phy.yaml
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v2: fix binding check warning of reg in example
> ---
>  .../bindings/phy/mediatek,ufs-phy.yaml        | 64 +++++++++++++++++++
>  .../devicetree/bindings/phy/phy-mtk-ufs.txt   | 38 -----------
>  2 files changed, 64 insertions(+), 38 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml
>  delete mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-ufs.txt
> 

Reviewed-by: Rob Herring <robh@kernel.org>

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Re: [PATCH v2 4/8] dt-bindings: phy: convert HDMI PHY binding to YAML schema

[CK Hu]

Hi, Chunfeng:

On Tue, 2020-10-13 at 16:52 +0800, Chunfeng Yun wrote:
> Convert HDMI PHY binding to YAML schema mediatek,ufs-phy.yaml
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v2: fix binding check warning of reg in example
> ---
>  .../display/mediatek/mediatek,hdmi.txt        | 17 +---
>  .../bindings/phy/mediatek,hdmi-phy.yaml       | 90 +++++++++++++++++++
>  2 files changed, 91 insertions(+), 16 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
> 
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
> index 7b124242b0c5..edac18951a75 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
> @@ -50,22 +50,7 @@ Required properties:
>  
>  HDMI PHY
>  ========
> -
> -The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
> -output and drives the HDMI pads.
> -
> -Required properties:
> -- compatible: "mediatek,<chip>-hdmi-phy"
> -- reg: Physical base address and length of the module's registers
> -- clocks: PLL reference clock
> -- clock-names: must contain "pll_ref"
> -- clock-output-names: must be "hdmitx_dig_cts" on mt8173
> -- #phy-cells: must be <0>
> -- #clock-cells: must be <0>
> -
> -Optional properties:
> -- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
> -- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
> +See phy/mediatek,hdmi-phy.yaml
>  
>  Example:
>  
> diff --git a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
> new file mode 100644
> index 000000000000..77df50204606
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
> @@ -0,0 +1,90 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2020 MediaTek
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek High Definition Multimedia Interface (HDMI) PHY binding
> +
> +maintainers:
> +  - CK Hu <ck.hu@mediatek.com>

I think you should remove "CK Hu <ck.hu@mediatek.com>" and add latest
mediatek drm maintainer:

DRM DRIVERS FOR MEDIATEK
M:	Chun-Kuang Hu <chunkuang.hu@kernel.org>
M:	Philipp Zabel <p.zabel@pengutronix.de>
L:	dri-devel@lists.freedesktop.org
S:	Supported
F:	Documentation/devicetree/bindings/display/mediatek/
F:	drivers/gpu/drm/mediatek/

Regards,
CK

> +  - Chunfeng Yun <chunfeng.yun@mediatek.com>
> +
> +description: |
> +  The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
> +  output and drives the HDMI pads.
> +
> +properties:
> +  $nodename:
> +    pattern: "^hdmi-phy@[0-9a-f]+$"
> +
> +  compatible:
> +    enum:
> +      - mediatek,mt2701-hdmi-phy
> +      - mediatek,mt8173-hdmi-phy
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: PLL reference clock
> +
> +  clock-names:
> +    items:
> +      - const: pll_ref
> +
> +  clock-output-names:
> +    items:
> +      - const: hdmitx_dig_cts
> +
> +  "#phy-cells":
> +    const: 0
> +
> +  "#clock-cells":
> +    const: 0
> +
> +  mediatek,ibias:
> +    description:
> +      TX DRV bias current for < 1.65Gbps
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 0
> +    maximum: 63
> +    default: 0xa
> +
> +  mediatek,ibias_up:
> +    description:
> +      TX DRV bias current for >= 1.65Gbps
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 0
> +    maximum: 63
> +    default: 0x1c
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - clock-output-names
> +  - "#phy-cells"
> +  - "#clock-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/mt8173-clk.h>
> +    hdmi_phy: hdmi-phy@10209100 {
> +        compatible = "mediatek,mt8173-hdmi-phy";
> +        reg = <0x10209100 0x24>;
> +        clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
> +        clock-names = "pll_ref";
> +        clock-output-names = "hdmitx_dig_cts";
> +        mediatek,ibias = <0xa>;
> +        mediatek,ibias_up = <0x1c>;
> +        #clock-cells = <0>;
> +        #phy-cells = <0>;
> +    };
> +
> +...

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Re: [PATCH v2 4/8] dt-bindings: phy: convert HDMI PHY binding to YAML schema

[Chunfeng Yun]

On Wed, 2020-10-14 at 12:44 +0800, CK Hu wrote:
> Hi, Chunfeng:
> 
> On Tue, 2020-10-13 at 16:52 +0800, Chunfeng Yun wrote:
> > Convert HDMI PHY binding to YAML schema mediatek,ufs-phy.yaml
> > 
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > ---
> > v2: fix binding check warning of reg in example
> > ---
> >  .../display/mediatek/mediatek,hdmi.txt        | 17 +---
> >  .../bindings/phy/mediatek,hdmi-phy.yaml       | 90 +++++++++++++++++++
> >  2 files changed, 91 insertions(+), 16 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
> > index 7b124242b0c5..edac18951a75 100644
> > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
> > @@ -50,22 +50,7 @@ Required properties:
> >  
> >  HDMI PHY
> >  ========
> > -
> > -The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
> > -output and drives the HDMI pads.
> > -
> > -Required properties:
> > -- compatible: "mediatek,<chip>-hdmi-phy"
> > -- reg: Physical base address and length of the module's registers
> > -- clocks: PLL reference clock
> > -- clock-names: must contain "pll_ref"
> > -- clock-output-names: must be "hdmitx_dig_cts" on mt8173
> > -- #phy-cells: must be <0>
> > -- #clock-cells: must be <0>
> > -
> > -Optional properties:
> > -- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
> > -- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
> > +See phy/mediatek,hdmi-phy.yaml
> >  
> >  Example:
> >  
> > diff --git a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
> > new file mode 100644
> > index 000000000000..77df50204606
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
> > @@ -0,0 +1,90 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +# Copyright (c) 2020 MediaTek
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MediaTek High Definition Multimedia Interface (HDMI) PHY binding
> > +
> > +maintainers:
> > +  - CK Hu <ck.hu@mediatek.com>
> 
> I think you should remove "CK Hu <ck.hu@mediatek.com>" and add latest
> mediatek drm maintainer:
Ok, will do it, thanks

> 
> DRM DRIVERS FOR MEDIATEK
> M:	Chun-Kuang Hu <chunkuang.hu@kernel.org>
> M:	Philipp Zabel <p.zabel@pengutronix.de>
> L:	dri-devel@lists.freedesktop.org
> S:	Supported
> F:	Documentation/devicetree/bindings/display/mediatek/
> F:	drivers/gpu/drm/mediatek/
> 
> Regards,
> CK

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Re: [PATCH v2 4/8] dt-bindings: phy: convert HDMI PHY binding to YAML schema

[Rob Herring]

On Tue, 13 Oct 2020 16:52:03 +0800, Chunfeng Yun wrote:
> Convert HDMI PHY binding to YAML schema mediatek,ufs-phy.yaml
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v2: fix binding check warning of reg in example
> ---
>  .../display/mediatek/mediatek,hdmi.txt        | 17 +---
>  .../bindings/phy/mediatek,hdmi-phy.yaml       | 90 +++++++++++++++++++
>  2 files changed, 91 insertions(+), 16 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
> 

Reviewed-by: Rob Herring <robh@kernel.org>

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Re: [PATCH v2 5/8] dt-bindings: usb: convert mediatek, musb.txt to YAML schema

[Rob Herring]

On Tue, 13 Oct 2020 16:52:04 +0800, Chunfeng Yun wrote:
> Convert mediatek,musb.txt to YAML schema mediatek,musb.yaml
> 
> Cc: Min Guo <min.guo@mediatek.com>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v2: new patch
> ---
>  .../devicetree/bindings/usb/mediatek,musb.txt |  57 ---------
>  .../bindings/usb/mediatek,musb.yaml           | 113 ++++++++++++++++++
>  2 files changed, 113 insertions(+), 57 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/usb/mediatek,musb.txt
>  create mode 100644 Documentation/devicetree/bindings/usb/mediatek,musb.yaml
> 

Reviewed-by: Rob Herring <robh@kernel.org>

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Re: [PATCH v2 6/8] dt-bindings: usb: convert mediatek,mtk-xhci.txt to YAML schema

[Rob Herring]

On Tue, Oct 13, 2020 at 04:52:05PM +0800, Chunfeng Yun wrote:
> Convert mediatek,mtk-xhci.txt to YAML schema mediatek,mtk-xhci.yaml
> 

There's some refactoring of usb-hcd.yaml and XHCI schema under review 
and this may need some refactoring on top of it.

> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v2: new patch
> ---
>  .../bindings/usb/mediatek,mtk-xhci.txt        | 121 ------------
>  .../bindings/usb/mediatek,mtk-xhci.yaml       | 180 ++++++++++++++++++
>  2 files changed, 180 insertions(+), 121 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
>  create mode 100644 Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml


> diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
> new file mode 100644
> index 000000000000..ea696c8f1269
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
> @@ -0,0 +1,180 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2020 MediaTek
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek USB3 xHCI Device Tree Bindings
> +
> +maintainers:
> +  - Chunfeng Yun <chunfeng.yun@mediatek.com>
> +
> +allOf:
> +  - $ref: "usb-hcd.yaml"
> +
> +description: |
> +  There are two scenarios:
> +  case 1: only supports xHCI driver;
> +  case 2: supports dual-role mode, and the host is based on xHCI driver.
> +
> +properties:
> +  #common properties for both case 1 and case 2
> +  compatible:
> +    items:
> +      - enum:
> +          - mediatek,mt2712-xhci
> +          - mediatek,mt7622-xhci
> +          - mediatek,mt7629-xhci
> +          - mediatek,mt8173-xhci
> +          - mediatek,mt8183-xhci
> +      - const: mediatek,mtk-xhci
> +
> +  reg:
> +    minItems: 1
> +    maxItems: 2
> +    items:
> +      - description: the registers of xHCI MAC
> +      - description: the registers of IP Port Control
> +
> +  reg-names:
> +    minItems: 1
> +    maxItems: 2
> +    items:
> +      - const: mac
> +      - const: ippc  #optional, only needed for case 1.
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle to USB power domain node to control USB's MTCMOS
> +    maxItems: 1
> +
> +  clocks:
> +    minItems: 1
> +    maxItems: 5
> +    items:
> +      - description: Controller clock used by normal mode
> +      - description: Reference clock used by low power mode etc
> +      - description: Mcu bus clock for register access
> +      - description: DMA bus clock for data transfer
> +      - description: controller clock
> +
> +  clock-names:
> +    minItems: 1
> +    maxItems: 5
> +    items:
> +      - const: sys_ck  #required, the following ones are optional
> +      - const: ref_ck
> +      - const: mcu_ck
> +      - const: dma_ck
> +      - const: xhci_ck
> +
> +  phys:
> +    $ref: /usb/usb-hcd.yaml#

That doesn't look right...

> +
> +  vusb33-supply:
> +    description: Regulator of USB AVDD3.3v
> +
> +  vbus-supply:
> +    description: Regulator of USB VBUS5v
> +
> +  usb3-lpm-capable:
> +    description: supports USB3.0 LPM
> +    type: boolean
> +
> +  imod-interval-ns:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description: |
> +      Interrupt moderation interval value, it is 8 times as much as that
> +      defined in the xHCI spec on MTK's controller.
> +    default: 5000
> +
> +  #the following properties are only used for case 1
> +  pinctrl-0:
> +    description: A phandle to the default pinctrl state.
> +
> +  pinctrl-names:
> +    description: A pinctrl state named "default" must be defined.
> +      See pinctrl/pinctrl-bindings.txt
> +    const: default

Don't need pinctrl-* properties. They are always allowed.

> +
> +  wakeup-source:
> +    description: enable USB remote wakeup, see power/wakeup-source.txt
> +    type: boolean
> +
> +  mediatek,syscon-wakeup:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +    description: |
> +      A phandle to syscon used to access the register of the USB wakeup glue
> +      layer between xHCI and SPM, the field should always be a multiple of
> +      3 cells long.

A multiple of 3? How would there be more than 3 cells?

> +
> +      items:
> +        - description:
> +            The first cell represents a phandle to syscon
> +        - description:
> +            The second cell represents the register base address of the glue
> +            layer in syscon
> +        - description:
> +            The third cell represents the hardware version of the glue layer,
> +            1 is used by mt8173 etc, 2 is used by mt2712 etc
> +          enum: [1, 2]
> +
> +  mediatek,u3p-dis-msk:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description: The mask to disable u3ports, bit0 for u3port0,
> +      bit1 for u3port1, ... etc
> +
> +  "#address-cells":
> +    const: 1
> +
> +  "#size-cells":
> +    const: 0
> +
> +patternProperties:
> +  "^[a-f]+@[0-9a-f]+$":
> +    $ref: /usb/usb-hcd.yaml#
> +    type: object
> +    description: The hard wired USB devices.
> +
> +dependencies:
> +  wakeup-source: [ 'mediatek,syscon-wakeup' ]
> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - interrupts
> +  - clocks
> +  - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/mt8173-clk.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +    #include <dt-bindings/phy/phy.h>
> +    #include <dt-bindings/power/mt8173-power.h>
> +
> +    usb3: usb@11270000 {
> +        compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci";
> +        reg = <0x11270000 0x1000>, <0x11280700 0x0100>;
> +        reg-names = "mac", "ippc";
> +        interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
> +        power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
> +        clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
> +        clock-names = "sys_ck", "ref_ck";
> +        phys = <&u3port0 PHY_TYPE_USB3>, <&u2port1 PHY_TYPE_USB2>;
> +        vusb33-supply = <&mt6397_vusb_reg>;
> +        vbus-supply = <&usb_p1_vbus>;
> +        imod-interval-ns = <10000>;
> +        mediatek,syscon-wakeup = <&pericfg 0x400 1>;
> +        wakeup-source;
> +        usb3-lpm-capable;
> +    };
> +...
> -- 
> 2.18.0

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Re: [PATCH v2 6/8] dt-bindings: usb: convert mediatek,mtk-xhci.txt to YAML schema

[Chunfeng Yun]

On Fri, 2020-10-16 at 12:14 -0500, Rob Herring wrote:
> On Tue, Oct 13, 2020 at 04:52:05PM +0800, Chunfeng Yun wrote:
> > Convert mediatek,mtk-xhci.txt to YAML schema mediatek,mtk-xhci.yaml
> > 
> 
> There's some refactoring of usb-hcd.yaml and XHCI schema under review 
> and this may need some refactoring on top of it.
Ok, will do it 
> 
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > ---
> > v2: new patch
> > ---
> >  .../bindings/usb/mediatek,mtk-xhci.txt        | 121 ------------
> >  .../bindings/usb/mediatek,mtk-xhci.yaml       | 180 ++++++++++++++++++
> >  2 files changed, 180 insertions(+), 121 deletions(-)
> >  delete mode 100644 Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
> >  create mode 100644 Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
> 
> 
> > diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
> > new file mode 100644
> > index 000000000000..ea696c8f1269
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
> > @@ -0,0 +1,180 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +# Copyright (c) 2020 MediaTek
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MediaTek USB3 xHCI Device Tree Bindings
> > +
> > +maintainers:
> > +  - Chunfeng Yun <chunfeng.yun@mediatek.com>
> > +
> > +allOf:
> > +  - $ref: "usb-hcd.yaml"
> > +
> > +description: |
> > +  There are two scenarios:
> > +  case 1: only supports xHCI driver;
> > +  case 2: supports dual-role mode, and the host is based on xHCI driver.
> > +
> > +properties:
> > +  #common properties for both case 1 and case 2
> > +  compatible:
> > +    items:
> > +      - enum:
> > +          - mediatek,mt2712-xhci
> > +          - mediatek,mt7622-xhci
> > +          - mediatek,mt7629-xhci
> > +          - mediatek,mt8173-xhci
> > +          - mediatek,mt8183-xhci
> > +      - const: mediatek,mtk-xhci
> > +
> > +  reg:
> > +    minItems: 1
> > +    maxItems: 2
> > +    items:
> > +      - description: the registers of xHCI MAC
> > +      - description: the registers of IP Port Control
> > +
> > +  reg-names:
> > +    minItems: 1
> > +    maxItems: 2
> > +    items:
> > +      - const: mac
> > +      - const: ippc  #optional, only needed for case 1.
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle to USB power domain node to control USB's MTCMOS
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    minItems: 1
> > +    maxItems: 5
> > +    items:
> > +      - description: Controller clock used by normal mode
> > +      - description: Reference clock used by low power mode etc
> > +      - description: Mcu bus clock for register access
> > +      - description: DMA bus clock for data transfer
> > +      - description: controller clock
> > +
> > +  clock-names:
> > +    minItems: 1
> > +    maxItems: 5
> > +    items:
> > +      - const: sys_ck  #required, the following ones are optional
> > +      - const: ref_ck
> > +      - const: mcu_ck
> > +      - const: dma_ck
> > +      - const: xhci_ck
> > +
> > +  phys:
> > +    $ref: /usb/usb-hcd.yaml#
> 
> That doesn't look right...
No need refer to it again?

usb-hcd.yaml describes how to use phys/phy-names

> 
> > +
> > +  vusb33-supply:
> > +    description: Regulator of USB AVDD3.3v
> > +
> > +  vbus-supply:
> > +    description: Regulator of USB VBUS5v
> > +
> > +  usb3-lpm-capable:
> > +    description: supports USB3.0 LPM
> > +    type: boolean
> > +
> > +  imod-interval-ns:
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    description: |
> > +      Interrupt moderation interval value, it is 8 times as much as that
> > +      defined in the xHCI spec on MTK's controller.
> > +    default: 5000
> > +
> > +  #the following properties are only used for case 1
> > +  pinctrl-0:
> > +    description: A phandle to the default pinctrl state.
> > +
> > +  pinctrl-names:
> > +    description: A pinctrl state named "default" must be defined.
> > +      See pinctrl/pinctrl-bindings.txt
> > +    const: default
> 
> Don't need pinctrl-* properties. They are always allowed.
Ok
> 
> > +
> > +  wakeup-source:
> > +    description: enable USB remote wakeup, see power/wakeup-source.txt
> > +    type: boolean
> > +
> > +  mediatek,syscon-wakeup:
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    maxItems: 1
> > +    description: |
> > +      A phandle to syscon used to access the register of the USB wakeup glue
> > +      layer between xHCI and SPM, the field should always be a multiple of
> > +      3 cells long.
> 
> A multiple of 3?
Seems wrong, only support one, will modify it
>  How would there be more than 3 cells?
others will be ignored

> 
> > +
> > +      items:
> > +        - description:
> > +            The first cell represents a phandle to syscon
> > +        - description:
> > +            The second cell represents the register base address of the glue
> > +            layer in syscon
> > +        - description:
> > +            The third cell represents the hardware version of the glue layer,
> > +            1 is used by mt8173 etc, 2 is used by mt2712 etc
> > +          enum: [1, 2]
> > +
> > +  mediatek,u3p-dis-msk:
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    description: The mask to disable u3ports, bit0 for u3port0,
> > +      bit1 for u3port1, ... etc
> > +
> > +  "#address-cells":
> > +    const: 1
> > +
> > +  "#size-cells":
> > +    const: 0
> > +
> > +patternProperties:
> > +  "^[a-f]+@[0-9a-f]+$":
> > +    $ref: /usb/usb-hcd.yaml#
> > +    type: object
> > +    description: The hard wired USB devices.
> > +
> > +dependencies:
> > +  wakeup-source: [ 'mediatek,syscon-wakeup' ]
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - reg-names
> > +  - interrupts
> > +  - clocks
> > +  - clock-names
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/mt8173-clk.h>
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +    #include <dt-bindings/interrupt-controller/irq.h>
> > +    #include <dt-bindings/phy/phy.h>
> > +    #include <dt-bindings/power/mt8173-power.h>
> > +
> > +    usb3: usb@11270000 {
> > +        compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci";
> > +        reg = <0x11270000 0x1000>, <0x11280700 0x0100>;
> > +        reg-names = "mac", "ippc";
> > +        interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
> > +        power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
> > +        clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
> > +        clock-names = "sys_ck", "ref_ck";
> > +        phys = <&u3port0 PHY_TYPE_USB3>, <&u2port1 PHY_TYPE_USB2>;
> > +        vusb33-supply = <&mt6397_vusb_reg>;
> > +        vbus-supply = <&usb_p1_vbus>;
> > +        imod-interval-ns = <10000>;
> > +        mediatek,syscon-wakeup = <&pericfg 0x400 1>;
> > +        wakeup-source;
> > +        usb3-lpm-capable;
> > +    };
> > +...
> > -- 
> > 2.18.0

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