From: Hanks Chen <hanks.chen@mediatek.com>
To: Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <maz@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Russell King <linux@armlinux.org.uk>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>
Cc: CC Hwang <cc.hwang@mediatek.com>,
Kuohong Wang <kuohong.wang@mediatek.com>,
Hanks Chen <hanks.chen@mediatek.com>,
Loda Chou <loda.chou@mediatek.com>,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: Support 1 of N SPI interrupt for interrupt distribution
Date: Fri, 27 Nov 2020 22:15:28 +0800 [thread overview]
Message-ID: <1606486531-25719-1-git-send-email-hanks.chen@mediatek.com> (raw)
*** BLURB HERE ***
The GICv3 supports 1 of N selection of SPI interrupts.
When the GICD_IROUTERn.Interrupt_Routing_Mode == 1, the GIC selects
the appropriate core for a SPI.
Actually, dispatch the interrupt by hardware Interrupt Control Unit
is more efficient than irqbalance of software logic
and no need to implement software contoller to decide the targeted CPU
on various platform.
In order to reduce interrupt latency, all interrupts are targeted to
each online CPU defaultly by 1 of N selection of SPI interrupts.
That is, SPI interrupts might be serviced simultaneously on different CPUs.
[default policy]
AS-IS (target to boot CPU)
CPU0 CPU1 CPU2 CPU3
29: 92 0 0 0 GICv3 141 Level ttyS0
TO-BE (enable ARM_IRQ_TARGET_ALL)
CPU0 CPU1 CPU2 CPU3
29: 23 23 24 22 GICv3 141 Level ttyS0
Hanks Chen (3):
irqchip/gic: enable irq target all
arm: disable irq on cpu shutdown flow
arm64: disable irq on cpu shutdown flow
arch/arm/kernel/smp.c | 10 ++-
arch/arm64/kernel/smp.c | 9 ++-
drivers/irqchip/Kconfig | 12 ++++
drivers/irqchip/irq-gic-v3.c | 107 +++++++++++++++++++++--------
include/linux/irqchip/arm-gic-v3.h | 1 +
kernel/irq/cpuhotplug.c | 22 ++++++
kernel/irq/manage.c | 7 ++
7 files changed, 138 insertions(+), 30 deletions(-)
--
2.18.0
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next reply other threads:[~2020-11-27 14:25 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-27 14:15 Hanks Chen [this message]
2020-11-27 14:15 ` [PATCH v1 1/3] irqchip/gic: enable irq target all Hanks Chen
2020-11-27 18:11 ` Marc Zyngier
2020-11-27 18:56 ` Catalin Marinas
2020-11-27 19:43 ` Marc Zyngier
2020-12-01 13:54 ` Hanks Chen
2020-12-02 11:09 ` Thomas Gleixner
2020-11-27 14:15 ` [PATCH v1 2/3] arm: disable irq on cpu shutdown flow Hanks Chen
2020-11-27 14:15 ` [PATCH v1 3/3] arm64: " Hanks Chen
2020-11-27 18:27 ` Marc Zyngier
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