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Fri, 27 Nov 2020 06:24:29 -0800 Received: from mtkmbs08n1.mediatek.inc (172.21.101.55) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 27 Nov 2020 06:15:46 -0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 27 Nov 2020 22:15:32 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 27 Nov 2020 22:15:32 +0800 From: Hanks Chen To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Matthias Brugger , Russell King , Catalin Marinas , Will Deacon , Mark Rutland Subject: Support 1 of N SPI interrupt for interrupt distribution Date: Fri, 27 Nov 2020 22:15:28 +0800 Message-ID: <1606486531-25719-1-git-send-email-hanks.chen@mediatek.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201127_092417_185415_30511491 X-CRM114-Status: GOOD ( 11.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: CC Hwang , Kuohong Wang , Hanks Chen , Loda Chou , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org *** BLURB HERE *** The GICv3 supports 1 of N selection of SPI interrupts. When the GICD_IROUTERn.Interrupt_Routing_Mode == 1, the GIC selects the appropriate core for a SPI. Actually, dispatch the interrupt by hardware Interrupt Control Unit is more efficient than irqbalance of software logic and no need to implement software contoller to decide the targeted CPU on various platform. In order to reduce interrupt latency, all interrupts are targeted to each online CPU defaultly by 1 of N selection of SPI interrupts. That is, SPI interrupts might be serviced simultaneously on different CPUs. [default policy] AS-IS (target to boot CPU) CPU0 CPU1 CPU2 CPU3 29: 92 0 0 0 GICv3 141 Level ttyS0 TO-BE (enable ARM_IRQ_TARGET_ALL) CPU0 CPU1 CPU2 CPU3 29: 23 23 24 22 GICv3 141 Level ttyS0 Hanks Chen (3): irqchip/gic: enable irq target all arm: disable irq on cpu shutdown flow arm64: disable irq on cpu shutdown flow arch/arm/kernel/smp.c | 10 ++- arch/arm64/kernel/smp.c | 9 ++- drivers/irqchip/Kconfig | 12 ++++ drivers/irqchip/irq-gic-v3.c | 107 +++++++++++++++++++++-------- include/linux/irqchip/arm-gic-v3.h | 1 + kernel/irq/cpuhotplug.c | 22 ++++++ kernel/irq/manage.c | 7 ++ 7 files changed, 138 insertions(+), 30 deletions(-) -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel